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12963e79ca
We have several device tree files already and may have more in the future so add a new dtb subdirectory and move device tree files there so they are not mixed with ROM binaries. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <57f179bd3904c1f2ca062ca4d4ff9592bb4f4daa.1745402140.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
283 lines
7.9 KiB
Plaintext
283 lines
7.9 KiB
Plaintext
/*
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* Copyright (c) 2020 Xilinx Inc.
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/ {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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compatible = "xlnx,microblaze";
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model = "testing";
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memory@90000000 {
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device_type = "memory";
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reg = <0x90000000 0x8000000>;
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};
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chosen {
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bootargs = "console=ttyUL0,115200";
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stdout-path = "/plb/serial@84000000";
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};
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cpus {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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#cpus = <0x01>;
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cpu@0 {
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clock-frequency = <0x3b9aca0>;
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compatible = "xlnx,microblaze-7.10.d";
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d-cache-baseaddr = <0x90000000>;
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d-cache-highaddr = <0x97ffffff>;
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d-cache-line-size = <0x10>;
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d-cache-size = <0x800>;
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device_type = "cpu";
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i-cache-baseaddr = <0x90000000>;
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i-cache-highaddr = <0x97ffffff>;
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i-cache-line-size = <0x10>;
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i-cache-size = <0x800>;
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model = "microblaze,7.10.d";
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reg = <0x00>;
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timebase-frequency = <0x3b9aca0>;
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xlnx,addr-tag-bits = <0x10>;
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xlnx,allow-dcache-wr = <0x01>;
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xlnx,allow-icache-wr = <0x01>;
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xlnx,area-optimized = <0x00>;
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xlnx,cache-byte-size = <0x800>;
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xlnx,d-lmb = <0x01>;
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xlnx,d-opb = <0x00>;
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xlnx,d-plb = <0x01>;
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xlnx,data-size = <0x20>;
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xlnx,dcache-addr-tag = <0x10>;
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xlnx,dcache-always-used = <0x00>;
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xlnx,dcache-byte-size = <0x800>;
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xlnx,dcache-line-len = <0x04>;
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xlnx,dcache-use-fsl = <0x01>;
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xlnx,debug-enabled = <0x01>;
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xlnx,div-zero-exception = <0x00>;
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xlnx,dopb-bus-exception = <0x00>;
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xlnx,dynamic-bus-sizing = <0x01>;
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xlnx,edge-is-positive = <0x01>;
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xlnx,family = "spartan3adsp";
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xlnx,fpu-exception = <0x00>;
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xlnx,fsl-data-size = <0x20>;
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xlnx,fsl-exception = <0x00>;
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xlnx,fsl-links = <0x00>;
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xlnx,i-lmb = <0x01>;
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xlnx,i-opb = <0x00>;
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xlnx,i-plb = <0x01>;
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xlnx,icache-always-used = <0x00>;
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xlnx,icache-line-len = <0x04>;
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xlnx,icache-use-fsl = <0x01>;
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xlnx,ill-opcode-exception = <0x00>;
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xlnx,instance = "microblaze_0";
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xlnx,interconnect = <0x01>;
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xlnx,interrupt-is-edge = <0x00>;
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xlnx,iopb-bus-exception = <0x00>;
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xlnx,mmu-dtlb-size = <0x04>;
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xlnx,mmu-itlb-size = <0x02>;
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xlnx,mmu-tlb-access = <0x03>;
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xlnx,mmu-zones = <0x10>;
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xlnx,number-of-pc-brk = <0x03>;
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xlnx,number-of-rd-addr-brk = <0x02>;
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xlnx,number-of-wr-addr-brk = <0x02>;
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xlnx,opcode-0x0-illegal = <0x00>;
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xlnx,pvr = <0x01>;
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xlnx,pvr-user1 = <0x00>;
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xlnx,pvr-user2 = <0x00>;
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xlnx,reset-msr = <0x00>;
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xlnx,sco = <0x00>;
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xlnx,unaligned-exceptions = <0x01>;
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xlnx,use-barrel = <0x01>;
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xlnx,use-dcache = <0x01>;
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xlnx,use-div = <0x00>;
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xlnx,use-ext-brk = <0x01>;
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xlnx,use-ext-nm-brk = <0x01>;
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xlnx,use-extended-fsl-instr = <0x00>;
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xlnx,use-fpu = <0x00>;
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xlnx,use-hw-mul = <0x01>;
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xlnx,use-icache = <0x01>;
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xlnx,use-interrupt = <0x01>;
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xlnx,use-mmu = <0x03>;
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xlnx,use-msr-instr = <0x01>;
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xlnx,use-pcmp-instr = <0x01>;
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};
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};
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plb {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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compatible = "xlnx,plb-v46-1.03.a\0simple-bus";
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ranges;
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ethernet@81000000 {
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compatible = "xlnx,xps-ethernetlite-2.00.a";
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device_type = "network";
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interrupt-parent = <0x01>;
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interrupts = <0x01 0x00>;
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local-mac-address = [02 00 00 00 00 00];
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reg = <0x81000000 0x10000>;
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xlnx,duplex = <0x01>;
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xlnx,family = "spartan3adsp";
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xlnx,rx-ping-pong = <0x00>;
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xlnx,tx-ping-pong = <0x00>;
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};
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flash@a0000000 {
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bank-width = <0x01>;
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compatible = "xlnx,xps-mch-emc-2.00.a\0cfi-flash";
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reg = <0xa0000000 0x1000000>;
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xlnx,family = "spartan3adsp";
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xlnx,include-datawidth-matching-0 = <0x01>;
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xlnx,include-datawidth-matching-1 = <0x00>;
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xlnx,include-datawidth-matching-2 = <0x00>;
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xlnx,include-datawidth-matching-3 = <0x00>;
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xlnx,include-negedge-ioregs = <0x00>;
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xlnx,include-plb-ipif = <0x01>;
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xlnx,include-wrbuf = <0x01>;
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xlnx,max-mem-width = <0x08>;
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xlnx,mch-native-dwidth = <0x20>;
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xlnx,mch-plb-clk-period-ps = <0x3e80>;
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xlnx,mch-splb-awidth = <0x20>;
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xlnx,mch0-accessbuf-depth = <0x10>;
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xlnx,mch0-protocol = <0x00>;
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xlnx,mch0-rddatabuf-depth = <0x10>;
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xlnx,mch1-accessbuf-depth = <0x10>;
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xlnx,mch1-protocol = <0x00>;
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xlnx,mch1-rddatabuf-depth = <0x10>;
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xlnx,mch2-accessbuf-depth = <0x10>;
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xlnx,mch2-protocol = <0x00>;
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xlnx,mch2-rddatabuf-depth = <0x10>;
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xlnx,mch3-accessbuf-depth = <0x10>;
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xlnx,mch3-protocol = <0x00>;
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xlnx,mch3-rddatabuf-depth = <0x10>;
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xlnx,mem0-width = <0x08>;
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xlnx,mem1-width = <0x20>;
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xlnx,mem2-width = <0x20>;
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xlnx,mem3-width = <0x20>;
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xlnx,num-banks-mem = <0x01>;
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xlnx,num-channels = <0x00>;
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xlnx,priority-mode = <0x00>;
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xlnx,synch-mem-0 = <0x00>;
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xlnx,synch-mem-1 = <0x00>;
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xlnx,synch-mem-2 = <0x00>;
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xlnx,synch-mem-3 = <0x00>;
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xlnx,synch-pipedelay-0 = <0x02>;
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xlnx,synch-pipedelay-1 = <0x02>;
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xlnx,synch-pipedelay-2 = <0x02>;
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xlnx,synch-pipedelay-3 = <0x02>;
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xlnx,tavdv-ps-mem-0 = <0x11170>;
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xlnx,tavdv-ps-mem-1 = <0x3a98>;
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xlnx,tavdv-ps-mem-2 = <0x3a98>;
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xlnx,tavdv-ps-mem-3 = <0x3a98>;
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xlnx,tcedv-ps-mem-0 = <0x11170>;
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xlnx,tcedv-ps-mem-1 = <0x3a98>;
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xlnx,tcedv-ps-mem-2 = <0x3a98>;
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xlnx,tcedv-ps-mem-3 = <0x3a98>;
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xlnx,thzce-ps-mem-0 = <0x61a8>;
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xlnx,thzce-ps-mem-1 = <0x1b58>;
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xlnx,thzce-ps-mem-2 = <0x1b58>;
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xlnx,thzce-ps-mem-3 = <0x1b58>;
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xlnx,thzoe-ps-mem-0 = <0x61a8>;
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xlnx,thzoe-ps-mem-1 = <0x1b58>;
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xlnx,thzoe-ps-mem-2 = <0x1b58>;
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xlnx,thzoe-ps-mem-3 = <0x1b58>;
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xlnx,tlzwe-ps-mem-0 = <0x1388>;
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xlnx,tlzwe-ps-mem-1 = <0x00>;
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xlnx,tlzwe-ps-mem-2 = <0x00>;
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xlnx,tlzwe-ps-mem-3 = <0x00>;
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xlnx,twc-ps-mem-0 = <0x11170>;
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xlnx,twc-ps-mem-1 = <0x3a98>;
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xlnx,twc-ps-mem-2 = <0x3a98>;
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xlnx,twc-ps-mem-3 = <0x3a98>;
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xlnx,twp-ps-mem-0 = <0xafc8>;
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xlnx,twp-ps-mem-1 = <0x2ee0>;
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xlnx,twp-ps-mem-2 = <0x2ee0>;
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xlnx,twp-ps-mem-3 = <0x2ee0>;
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xlnx,xcl0-linesize = <0x04>;
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xlnx,xcl0-writexfer = <0x01>;
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xlnx,xcl1-linesize = <0x04>;
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xlnx,xcl1-writexfer = <0x01>;
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xlnx,xcl2-linesize = <0x04>;
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xlnx,xcl2-writexfer = <0x01>;
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xlnx,xcl3-linesize = <0x04>;
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xlnx,xcl3-writexfer = <0x01>;
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};
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gpio@81400000 {
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compatible = "xlnx,xps-gpio-1.00.a";
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interrupt-parent = <0x01>;
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interrupts = <0x02 0x02>;
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reg = <0x81400000 0x10000>;
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xlnx,all-inputs = <0x00>;
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xlnx,all-inputs-2 = <0x00>;
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xlnx,dout-default = <0x00>;
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xlnx,dout-default-2 = <0x00>;
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xlnx,family = "spartan3adsp";
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xlnx,gpio-width = <0x08>;
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xlnx,interrupt-present = <0x01>;
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xlnx,is-bidir = <0x00>;
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xlnx,is-bidir-2 = <0x01>;
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xlnx,is-dual = <0x00>;
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xlnx,tri-default = <0xffffffff>;
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xlnx,tri-default-2 = <0xffffffff>;
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};
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serial@84000000 {
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clock-frequency = <0x3b9aca0>;
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compatible = "xlnx,xps-uartlite-1.00.a";
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current-speed = <0x1c200>;
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device_type = "serial";
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interrupt-parent = <0x01>;
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interrupts = <0x03 0x00>;
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port-number = <0x00>;
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reg = <0x84000000 0x10000>;
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xlnx,baudrate = <0x1c200>;
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xlnx,data-bits = <0x08>;
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xlnx,family = "spartan3adsp";
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xlnx,odd-parity = <0x00>;
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xlnx,use-parity = <0x00>;
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};
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debug@84400000 {
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compatible = "xlnx,mdm-1.00.d";
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reg = <0x84400000 0x10000>;
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xlnx,family = "spartan3adsp";
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xlnx,interconnect = <0x01>;
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xlnx,jtag-chain = <0x02>;
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xlnx,mb-dbg-ports = <0x01>;
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xlnx,uart-width = <0x08>;
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xlnx,use-uart = <0x01>;
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xlnx,write-fsl-ports = <0x00>;
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};
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interrupt-controller@81800000 {
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#interrupt-cells = <0x02>;
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compatible = "xlnx,xps-intc-1.00.a";
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interrupt-controller;
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reg = <0x81800000 0x10000>;
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xlnx,kind-of-intr = <0x0a>;
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xlnx,num-intr-inputs = <0x04>;
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linux,phandle = <0x01>;
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};
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timer@83c00000 {
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compatible = "xlnx,xps-timer-1.00.a";
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x02>;
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reg = <0x83c00000 0x10000>;
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xlnx,count-width = <0x20>;
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xlnx,family = "spartan3adsp";
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xlnx,gen0-assert = <0x01>;
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xlnx,gen1-assert = <0x01>;
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xlnx,one-timer-only = <0x00>;
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xlnx,trig0-assert = <0x01>;
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xlnx,trig1-assert = <0x01>;
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};
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};
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};
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