2017-12-21 00:45:38 +01:00
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/*
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2022-02-01 14:49:57 +00:00
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* Copyright (C) 2018-2022 Intel Corporation
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2017-12-21 00:45:38 +01:00
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*
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2018-09-18 09:11:08 +02:00
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* SPDX-License-Identifier: MIT
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2017-12-21 00:45:38 +01:00
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*
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*/
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2020-02-23 22:44:01 +01:00
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#include "shared/source/execution_environment/execution_environment.h"
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2022-08-08 19:04:04 +00:00
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#include "shared/source/helpers/hw_info.h"
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2022-02-01 14:49:57 +00:00
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#include "shared/source/helpers/register_offsets.h"
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2020-02-23 22:44:01 +01:00
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#include "shared/source/os_interface/linux/drm_null_device.h"
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2021-01-21 13:10:13 +01:00
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#include "shared/test/common/helpers/debug_manager_state_restore.h"
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2021-12-14 17:40:08 +00:00
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#include "shared/test/common/test_macros/test.h"
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2020-02-24 10:22:30 +01:00
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2020-02-23 15:20:22 +01:00
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#include "opencl/test/unit_test/linux/drm_wrap.h"
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#include "opencl/test/unit_test/linux/mock_os_layer.h"
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2020-02-22 22:50:57 +01:00
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2019-03-28 12:53:48 +01:00
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#include <memory>
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2019-02-27 11:39:32 +01:00
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2019-03-26 11:59:46 +01:00
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using namespace NEO;
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2017-12-21 00:45:38 +01:00
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2021-07-20 10:13:23 +00:00
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extern const DeviceDescriptor NEO::deviceDescriptorTable[];
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2017-12-21 00:45:38 +01:00
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class DrmNullDeviceTestsFixture {
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public:
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2022-08-16 14:51:17 +00:00
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void setUp() {
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2021-07-20 10:13:23 +00:00
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if (deviceDescriptorTable[0].deviceId == 0) {
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GTEST_SKIP();
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}
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2017-12-21 00:45:38 +01:00
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// Create nullDevice drm
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DebugManager.flags.EnableNullHardware.set(true);
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2020-01-29 19:10:49 +01:00
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executionEnvironment.prepareRootDeviceEnvironments(1);
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2020-02-11 17:48:40 +01:00
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drmNullDevice = DrmWrap::createDrm(*executionEnvironment.rootDeviceEnvironments[0]);
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2017-12-21 00:45:38 +01:00
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ASSERT_NE(drmNullDevice, nullptr);
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}
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2022-08-16 14:51:17 +00:00
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void tearDown() {
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2017-12-21 00:45:38 +01:00
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}
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2022-07-19 17:13:51 +00:00
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std::unique_ptr<DrmWrap, std::function<void(Drm *)>> drmNullDevice;
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2020-01-29 19:10:49 +01:00
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ExecutionEnvironment executionEnvironment;
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2017-12-21 00:45:38 +01:00
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protected:
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2019-03-28 12:53:48 +01:00
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DebugManagerStateRestore dbgRestorer;
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2017-12-21 00:45:38 +01:00
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};
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2022-08-16 14:51:17 +00:00
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typedef Test<DrmNullDeviceTestsFixture> DrmNullDeviceTests;
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2017-12-21 00:45:38 +01:00
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2022-10-05 00:31:08 -07:00
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TEST_F(DrmNullDeviceTests, GivenDrmNullDeviceWhenCallGetDeviceIdThenReturnProperDeviceId) {
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2022-06-08 12:43:51 +00:00
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int ret = drmNullDevice->queryDeviceIdAndRevision();
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EXPECT_TRUE(ret);
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2022-08-08 19:04:04 +00:00
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auto hwInfo = drmNullDevice->getRootDeviceEnvironment().getMutableHardwareInfo();
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EXPECT_EQ(deviceId, hwInfo->platform.usDeviceID);
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EXPECT_EQ(revisionId, hwInfo->platform.usRevId);
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2017-12-21 00:45:38 +01:00
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}
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2022-10-05 00:31:08 -07:00
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TEST_F(DrmNullDeviceTests, GivenDrmNullDeviceWhenCallIoctlThenAlwaysSuccess) {
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2022-05-25 17:05:52 +00:00
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EXPECT_EQ(drmNullDevice->ioctl(DrmIoctl::GemExecbuffer2, nullptr), 0);
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2017-12-21 00:45:38 +01:00
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}
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2022-10-05 00:31:08 -07:00
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TEST_F(DrmNullDeviceTests, GivenDrmNullDeviceWhenRegReadOtherThenTimestampReadThenAlwaysSuccessIsReturned) {
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2022-05-12 13:46:22 +00:00
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RegisterRead arg;
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2017-12-21 00:45:38 +01:00
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arg.offset = 0;
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ASSERT_EQ(drmNullDevice->ioctl(DrmIoctl::RegRead, &arg), 0);
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2017-12-21 00:45:38 +01:00
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}
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2022-10-05 00:31:08 -07:00
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TEST_F(DrmNullDeviceTests, GivenDrmNullDeviceWhenGetGpuTimestamp32bOr64bThenErrorIsReturned) {
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2022-05-12 13:46:22 +00:00
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RegisterRead arg;
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2017-12-21 00:45:38 +01:00
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2022-02-01 14:49:57 +00:00
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arg.offset = REG_GLOBAL_TIMESTAMP_LDW;
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2022-05-25 17:05:52 +00:00
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ASSERT_EQ(drmNullDevice->ioctl(DrmIoctl::RegRead, &arg), -1);
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2017-12-21 00:45:38 +01:00
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2022-02-01 14:49:57 +00:00
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arg.offset = REG_GLOBAL_TIMESTAMP_UN;
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2022-05-25 17:05:52 +00:00
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ASSERT_EQ(drmNullDevice->ioctl(DrmIoctl::RegRead, &arg), -1);
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2017-12-21 00:45:38 +01:00
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}
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2022-10-05 00:31:08 -07:00
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TEST_F(DrmNullDeviceTests, GivenDrmNullDeviceWhenGetGpuTimestamp36bThenProperValuesAreReturned) {
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2022-05-12 13:46:22 +00:00
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RegisterRead arg;
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2017-12-21 00:45:38 +01:00
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2022-02-01 14:49:57 +00:00
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arg.offset = REG_GLOBAL_TIMESTAMP_LDW | 1;
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2022-05-25 17:05:52 +00:00
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ASSERT_EQ(drmNullDevice->ioctl(DrmIoctl::RegRead, &arg), 0);
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2022-05-12 13:46:22 +00:00
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EXPECT_EQ(arg.value, 1000ULL);
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2017-12-21 00:45:38 +01:00
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2022-05-25 17:05:52 +00:00
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ASSERT_EQ(drmNullDevice->ioctl(DrmIoctl::RegRead, &arg), 0);
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2022-05-12 13:46:22 +00:00
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EXPECT_EQ(arg.value, 2000ULL);
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2017-12-21 00:45:38 +01:00
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2022-05-25 17:05:52 +00:00
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ASSERT_EQ(drmNullDevice->ioctl(DrmIoctl::RegRead, &arg), 0);
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2022-05-12 13:46:22 +00:00
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EXPECT_EQ(arg.value, 3000ULL);
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2017-12-21 00:45:38 +01:00
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}
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