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9bd0c699139c8fab2c1332fc7f2bc9b2dddba7c5
compute-runtime/shared/source/memory_manager/memory_banks.h

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Refactor PhysicalAddressAllocator - create allocator dynamically in AUB & TBX CSRs Change-Id: I3b01a3fc2f4824b552ef27cbda5bdcc140e92e53
2018-09-20 13:54:19 -07:00
/*
Changing include paths Change-Id: I3b878463289083c956382e68da3473788cf5c15f
2020-02-22 09:28:27 +01:00
* Copyright (C) 2018-2020 Intel Corporation
Refactor PhysicalAddressAllocator - create allocator dynamically in AUB & TBX CSRs Change-Id: I3b01a3fc2f4824b552ef27cbda5bdcc140e92e53
2018-09-20 13:54:19 -07:00
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include <cstdint>
namespace MemoryBanks {
constexpr uint32_t BankNotSpecified{0};
constexpr uint32_t MainBank{0};
Add DG1 support to OpenCL and Level Zero (2/n) Source location of Linux kernel DRM/i915 interface headers: https://repositories.intel.com/graphics/kernel-api/index.html Related-To: NEO-4744 Change-Id: I08a9ab651d8594e9a04d6a83dc48682d4fa53702 Signed-off-by: Slawomir Milczarek <slawomir.milczarek@intel.com>
2020-06-22 14:34:44 +02:00
constexpr uint32_t Bank0{1};
Refactor PhysicalAddressAllocator - create allocator dynamically in AUB & TBX CSRs Change-Id: I3b01a3fc2f4824b552ef27cbda5bdcc140e92e53
2018-09-20 13:54:19 -07:00
inline uint32_t getBank(uint32_t deviceOrdinal) {
return MemoryBanks::MainBank;
}
} // namespace MemoryBanks
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