Define GPGPU engines per gen

Change-Id: Ie0e565d11184c5355b5bf09f5b10a567deb5c106
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski
2019-01-10 13:57:40 +01:00
committed by sys_ocldev
parent 84d35c8951
commit 06600f169b
52 changed files with 226 additions and 171 deletions

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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2018 Intel Corporation
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -33,21 +33,13 @@ struct EngineInstanceT {
int id;
};
constexpr EngineInstanceT lowPriorityGpgpuEngine{ENGINE_RCS, 1};
static constexpr std::array<EngineInstanceT, EngineInstanceConstants::numAllEngineInstances> allEngineInstances = {{
{ENGINE_RCS, 0},
{ENGINE_RCS, 1},
lowPriorityGpgpuEngine,
{ENGINE_BCS},
{ENGINE_VCS},
{ENGINE_VECS},
}};
static constexpr std::array<EngineInstanceT, EngineInstanceConstants::numGpgpuEngineInstances> gpgpuEngineInstances = {{
{ENGINE_RCS, 0},
{ENGINE_RCS, 1},
}};
static_assert(gpgpuEngineInstances[EngineInstanceConstants::lowPriorityGpgpuEngineIndex].type == EngineType::ENGINE_RCS &&
gpgpuEngineInstances[EngineInstanceConstants::lowPriorityGpgpuEngineIndex].id == 1,
"{RCS,1} is low priority engine");
} // namespace OCLRT

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@@ -84,9 +84,7 @@ Device::~Device() {
}
for (auto &engine : engines) {
if (engine.commandStreamReceiver) {
engine.commandStreamReceiver->flushBatchedSubmissions();
}
engine.commandStreamReceiver->flushBatchedSubmissions();
}
if (deviceInfo.sourceLevelDebuggerActive && executionEnvironment->sourceLevelDebugger) {
@@ -166,26 +164,27 @@ bool Device::createDeviceImpl(const HardwareInfo *pHwInfo, Device &outDevice) {
bool Device::createEngines(const HardwareInfo *pHwInfo, Device &outDevice) {
auto executionEnvironment = outDevice.executionEnvironment;
auto defaultEngineType = getChosenEngineType(*pHwInfo);
auto &gpgpuEngines = HwHelper::get(pHwInfo->pPlatform->eRenderCoreFamily).getGpgpuEngineInstances();
for (uint32_t deviceCsrIndex = 0; deviceCsrIndex < gpgpuEngineInstances.size(); deviceCsrIndex++) {
for (uint32_t deviceCsrIndex = 0; deviceCsrIndex < gpgpuEngines.size(); deviceCsrIndex++) {
if (!executionEnvironment->initializeCommandStreamReceiver(pHwInfo, outDevice.getDeviceIndex(), deviceCsrIndex)) {
return false;
}
executionEnvironment->initializeMemoryManager(outDevice.getEnabled64kbPages(), outDevice.getEnableLocalMemory(),
outDevice.getDeviceIndex(), deviceCsrIndex);
auto osContext = executionEnvironment->memoryManager->createAndRegisterOsContext(gpgpuEngineInstances[deviceCsrIndex], outDevice.preemptionMode);
auto osContext = executionEnvironment->memoryManager->createAndRegisterOsContext(gpgpuEngines[deviceCsrIndex], outDevice.preemptionMode);
auto commandStreamReceiver = executionEnvironment->commandStreamReceivers[outDevice.getDeviceIndex()][deviceCsrIndex].get();
commandStreamReceiver->setupContext(*osContext);
if (!commandStreamReceiver->initializeTagAllocation()) {
return false;
}
if (gpgpuEngineInstances[deviceCsrIndex].type == defaultEngineType && gpgpuEngineInstances[deviceCsrIndex].id == 0) {
if (gpgpuEngines[deviceCsrIndex].type == defaultEngineType && gpgpuEngines[deviceCsrIndex].id == 0) {
outDevice.defaultEngineIndex = deviceCsrIndex;
}
outDevice.engines[deviceCsrIndex] = {commandStreamReceiver, osContext};
outDevice.engines.push_back({commandStreamReceiver, osContext});
}
return true;
}
@@ -271,9 +270,7 @@ bool Device::isSourceLevelDebuggerActive() const {
void Device::initMaxPowerSavingMode() {
for (auto &engine : engines) {
if (engine.commandStreamReceiver) {
engine.commandStreamReceiver->peekKmdNotifyHelper()->initMaxPowerSavingMode();
}
engine.commandStreamReceiver->peekKmdNotifyHelper()->initMaxPowerSavingMode();
}
}
} // namespace OCLRT

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@@ -151,7 +151,7 @@ class Device : public BaseObject<_cl_device_id> {
std::unique_ptr<DriverInfo> driverInfo;
std::unique_ptr<PerformanceCounters> performanceCounters;
std::array<EngineControl, EngineInstanceConstants::numGpgpuEngineInstances> engines = {{}};
std::vector<EngineControl> engines;
void *slmWindowStartAddress = nullptr;

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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018 Intel Corporation
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -38,6 +38,9 @@ bool ExecutionEnvironment::initializeCommandStreamReceiver(const HardwareInfo *p
commandStreamReceivers.resize(deviceIndex + 1);
}
if (deviceCsrIndex + 1 > commandStreamReceivers[deviceIndex].size()) {
commandStreamReceivers[deviceIndex].resize(deviceCsrIndex + 1);
}
if (this->commandStreamReceivers[deviceIndex][deviceCsrIndex]) {
return true;
}

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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018 Intel Corporation
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -24,7 +24,7 @@ class BuiltIns;
struct HardwareInfo;
class OSInterface;
using CsrContainer = std::vector<std::array<std::unique_ptr<CommandStreamReceiver>, EngineInstanceConstants::numGpgpuEngineInstances>>;
using CsrContainer = std::vector<std::vector<std::unique_ptr<CommandStreamReceiver>>>;
class ExecutionEnvironment : public ReferenceTrackedObject<ExecutionEnvironment> {
private:

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@@ -1,12 +1,12 @@
/*
* Copyright (C) 2017-2018 Intel Corporation
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "runtime/api/cl_types.h"
#include "CL/cl.h"
#include "runtime/gen_common/aub_mapper.h"
#include "runtime/gen_common/hw_cmds.h"
#include "runtime/command_stream/linear_stream.h"
@@ -54,6 +54,7 @@ class HwHelper {
uint32_t surfaceType,
bool forceNonAuxMode) = 0;
virtual size_t getScratchSpaceOffsetFor64bit() = 0;
virtual const std::vector<EngineInstanceT> getGpgpuEngineInstances() const = 0;
protected:
HwHelper() = default;
@@ -133,6 +134,8 @@ class HwHelperHw : public HwHelper {
size_t getScratchSpaceOffsetFor64bit() override;
const std::vector<EngineInstanceT> getGpgpuEngineInstances() const override;
protected:
HwHelperHw() = default;
};

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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2018 Intel Corporation
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -162,4 +162,11 @@ size_t HwHelperHw<Family>::getScratchSpaceOffsetFor64bit() {
return 4096;
}
template <typename Family>
const std::vector<EngineInstanceT> HwHelperHw<Family>::getGpgpuEngineInstances() const {
constexpr std::array<EngineInstanceT, 2> gpgpuEngineInstances = {{{ENGINE_RCS, 0},
lowPriorityGpgpuEngine}};
return std::vector<EngineInstanceT>(gpgpuEngineInstances.begin(), gpgpuEngineInstances.end());
};
} // namespace OCLRT

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@@ -145,14 +145,12 @@ void MemoryManager::checkGpuUsageAndDestroyGraphicsAllocations(GraphicsAllocatio
}
for (auto &deviceCsrs : getCommandStreamReceivers()) {
for (auto &csr : deviceCsrs) {
if (csr) {
auto osContextId = csr->getOsContext().getContextId();
auto allocationTaskCount = gfxAllocation->getTaskCount(osContextId);
if (gfxAllocation->isUsedByOsContext(osContextId) &&
allocationTaskCount > *csr->getTagAddress()) {
csr->getInternalAllocationStorage()->storeAllocation(std::unique_ptr<GraphicsAllocation>(gfxAllocation), TEMPORARY_ALLOCATION);
return;
}
auto osContextId = csr->getOsContext().getContextId();
auto allocationTaskCount = gfxAllocation->getTaskCount(osContextId);
if (gfxAllocation->isUsedByOsContext(osContextId) &&
allocationTaskCount > *csr->getTagAddress()) {
csr->getInternalAllocationStorage()->storeAllocation(std::unique_ptr<GraphicsAllocation>(gfxAllocation), TEMPORARY_ALLOCATION);
return;
}
}
}

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@@ -28,7 +28,7 @@ struct ImageInfo;
enum class PreemptionMode : uint32_t;
using CsrContainer = std::vector<std::array<std::unique_ptr<CommandStreamReceiver>, EngineInstanceConstants::numGpgpuEngineInstances>>;
using CsrContainer = std::vector<std::vector<std::unique_ptr<CommandStreamReceiver>>>;
enum AllocationUsage {
TEMPORARY_ALLOCATION,

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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2018 Intel Corporation
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -11,7 +11,7 @@
#include "engine_node.h"
namespace OCLRT {
constexpr uint32_t maxOsContextCount = 4u * static_cast<uint32_t>(gpgpuEngineInstances.size());
constexpr uint32_t maxOsContextCount = 4u * static_cast<uint32_t>(EngineInstanceConstants::numGpgpuEngineInstances);
struct ResidencyData {
ResidencyData() {

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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018 Intel Corporation
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -26,8 +26,8 @@ OsContextLinux::OsContextImpl(Drm &drm, EngineInstanceT engineType) : drm(drm) {
engineFlag = DrmEngineMapper::engineNodeMap(engineType.type);
this->drmContextId = drm.createDrmContext();
if (drm.isPreemptionSupported() &&
engineType.type == gpgpuEngineInstances[EngineInstanceConstants::lowPriorityGpgpuEngineIndex].type &&
engineType.id == gpgpuEngineInstances[EngineInstanceConstants::lowPriorityGpgpuEngineIndex].id) {
engineType.type == lowPriorityGpgpuEngine.type &&
engineType.id == lowPriorityGpgpuEngine.id) {
drm.setLowPriorityContextParam(this->drmContextId);
}
}