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https://github.com/intel/compute-runtime.git
synced 2026-01-08 22:12:59 +08:00
Define GPGPU engines per gen
Change-Id: Ie0e565d11184c5355b5bf09f5b10a567deb5c106 Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
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sys_ocldev
parent
84d35c8951
commit
06600f169b
@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -33,21 +33,13 @@ struct EngineInstanceT {
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int id;
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};
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constexpr EngineInstanceT lowPriorityGpgpuEngine{ENGINE_RCS, 1};
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static constexpr std::array<EngineInstanceT, EngineInstanceConstants::numAllEngineInstances> allEngineInstances = {{
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{ENGINE_RCS, 0},
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{ENGINE_RCS, 1},
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lowPriorityGpgpuEngine,
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{ENGINE_BCS},
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{ENGINE_VCS},
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{ENGINE_VECS},
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}};
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static constexpr std::array<EngineInstanceT, EngineInstanceConstants::numGpgpuEngineInstances> gpgpuEngineInstances = {{
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{ENGINE_RCS, 0},
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{ENGINE_RCS, 1},
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}};
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static_assert(gpgpuEngineInstances[EngineInstanceConstants::lowPriorityGpgpuEngineIndex].type == EngineType::ENGINE_RCS &&
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gpgpuEngineInstances[EngineInstanceConstants::lowPriorityGpgpuEngineIndex].id == 1,
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"{RCS,1} is low priority engine");
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} // namespace OCLRT
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@@ -84,9 +84,7 @@ Device::~Device() {
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}
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for (auto &engine : engines) {
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if (engine.commandStreamReceiver) {
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engine.commandStreamReceiver->flushBatchedSubmissions();
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}
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engine.commandStreamReceiver->flushBatchedSubmissions();
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}
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if (deviceInfo.sourceLevelDebuggerActive && executionEnvironment->sourceLevelDebugger) {
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@@ -166,26 +164,27 @@ bool Device::createDeviceImpl(const HardwareInfo *pHwInfo, Device &outDevice) {
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bool Device::createEngines(const HardwareInfo *pHwInfo, Device &outDevice) {
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auto executionEnvironment = outDevice.executionEnvironment;
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auto defaultEngineType = getChosenEngineType(*pHwInfo);
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auto &gpgpuEngines = HwHelper::get(pHwInfo->pPlatform->eRenderCoreFamily).getGpgpuEngineInstances();
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for (uint32_t deviceCsrIndex = 0; deviceCsrIndex < gpgpuEngineInstances.size(); deviceCsrIndex++) {
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for (uint32_t deviceCsrIndex = 0; deviceCsrIndex < gpgpuEngines.size(); deviceCsrIndex++) {
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if (!executionEnvironment->initializeCommandStreamReceiver(pHwInfo, outDevice.getDeviceIndex(), deviceCsrIndex)) {
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return false;
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}
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executionEnvironment->initializeMemoryManager(outDevice.getEnabled64kbPages(), outDevice.getEnableLocalMemory(),
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outDevice.getDeviceIndex(), deviceCsrIndex);
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auto osContext = executionEnvironment->memoryManager->createAndRegisterOsContext(gpgpuEngineInstances[deviceCsrIndex], outDevice.preemptionMode);
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auto osContext = executionEnvironment->memoryManager->createAndRegisterOsContext(gpgpuEngines[deviceCsrIndex], outDevice.preemptionMode);
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auto commandStreamReceiver = executionEnvironment->commandStreamReceivers[outDevice.getDeviceIndex()][deviceCsrIndex].get();
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commandStreamReceiver->setupContext(*osContext);
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if (!commandStreamReceiver->initializeTagAllocation()) {
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return false;
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}
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if (gpgpuEngineInstances[deviceCsrIndex].type == defaultEngineType && gpgpuEngineInstances[deviceCsrIndex].id == 0) {
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if (gpgpuEngines[deviceCsrIndex].type == defaultEngineType && gpgpuEngines[deviceCsrIndex].id == 0) {
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outDevice.defaultEngineIndex = deviceCsrIndex;
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}
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outDevice.engines[deviceCsrIndex] = {commandStreamReceiver, osContext};
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outDevice.engines.push_back({commandStreamReceiver, osContext});
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}
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return true;
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}
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@@ -271,9 +270,7 @@ bool Device::isSourceLevelDebuggerActive() const {
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void Device::initMaxPowerSavingMode() {
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for (auto &engine : engines) {
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if (engine.commandStreamReceiver) {
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engine.commandStreamReceiver->peekKmdNotifyHelper()->initMaxPowerSavingMode();
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}
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engine.commandStreamReceiver->peekKmdNotifyHelper()->initMaxPowerSavingMode();
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}
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}
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} // namespace OCLRT
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@@ -151,7 +151,7 @@ class Device : public BaseObject<_cl_device_id> {
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std::unique_ptr<DriverInfo> driverInfo;
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std::unique_ptr<PerformanceCounters> performanceCounters;
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std::array<EngineControl, EngineInstanceConstants::numGpgpuEngineInstances> engines = {{}};
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std::vector<EngineControl> engines;
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void *slmWindowStartAddress = nullptr;
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2018 Intel Corporation
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* Copyright (C) 2018-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -38,6 +38,9 @@ bool ExecutionEnvironment::initializeCommandStreamReceiver(const HardwareInfo *p
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commandStreamReceivers.resize(deviceIndex + 1);
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}
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if (deviceCsrIndex + 1 > commandStreamReceivers[deviceIndex].size()) {
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commandStreamReceivers[deviceIndex].resize(deviceCsrIndex + 1);
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}
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if (this->commandStreamReceivers[deviceIndex][deviceCsrIndex]) {
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return true;
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}
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2018 Intel Corporation
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* Copyright (C) 2018-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -24,7 +24,7 @@ class BuiltIns;
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struct HardwareInfo;
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class OSInterface;
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using CsrContainer = std::vector<std::array<std::unique_ptr<CommandStreamReceiver>, EngineInstanceConstants::numGpgpuEngineInstances>>;
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using CsrContainer = std::vector<std::vector<std::unique_ptr<CommandStreamReceiver>>>;
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class ExecutionEnvironment : public ReferenceTrackedObject<ExecutionEnvironment> {
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private:
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@@ -1,12 +1,12 @@
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "runtime/api/cl_types.h"
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#include "CL/cl.h"
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#include "runtime/gen_common/aub_mapper.h"
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#include "runtime/gen_common/hw_cmds.h"
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#include "runtime/command_stream/linear_stream.h"
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@@ -54,6 +54,7 @@ class HwHelper {
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uint32_t surfaceType,
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bool forceNonAuxMode) = 0;
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virtual size_t getScratchSpaceOffsetFor64bit() = 0;
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virtual const std::vector<EngineInstanceT> getGpgpuEngineInstances() const = 0;
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protected:
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HwHelper() = default;
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@@ -133,6 +134,8 @@ class HwHelperHw : public HwHelper {
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size_t getScratchSpaceOffsetFor64bit() override;
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const std::vector<EngineInstanceT> getGpgpuEngineInstances() const override;
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protected:
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HwHelperHw() = default;
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};
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -162,4 +162,11 @@ size_t HwHelperHw<Family>::getScratchSpaceOffsetFor64bit() {
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return 4096;
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}
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template <typename Family>
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const std::vector<EngineInstanceT> HwHelperHw<Family>::getGpgpuEngineInstances() const {
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constexpr std::array<EngineInstanceT, 2> gpgpuEngineInstances = {{{ENGINE_RCS, 0},
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lowPriorityGpgpuEngine}};
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return std::vector<EngineInstanceT>(gpgpuEngineInstances.begin(), gpgpuEngineInstances.end());
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};
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} // namespace OCLRT
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@@ -145,14 +145,12 @@ void MemoryManager::checkGpuUsageAndDestroyGraphicsAllocations(GraphicsAllocatio
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}
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for (auto &deviceCsrs : getCommandStreamReceivers()) {
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for (auto &csr : deviceCsrs) {
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if (csr) {
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auto osContextId = csr->getOsContext().getContextId();
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auto allocationTaskCount = gfxAllocation->getTaskCount(osContextId);
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if (gfxAllocation->isUsedByOsContext(osContextId) &&
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allocationTaskCount > *csr->getTagAddress()) {
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csr->getInternalAllocationStorage()->storeAllocation(std::unique_ptr<GraphicsAllocation>(gfxAllocation), TEMPORARY_ALLOCATION);
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return;
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}
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auto osContextId = csr->getOsContext().getContextId();
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auto allocationTaskCount = gfxAllocation->getTaskCount(osContextId);
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if (gfxAllocation->isUsedByOsContext(osContextId) &&
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allocationTaskCount > *csr->getTagAddress()) {
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csr->getInternalAllocationStorage()->storeAllocation(std::unique_ptr<GraphicsAllocation>(gfxAllocation), TEMPORARY_ALLOCATION);
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return;
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}
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}
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}
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@@ -28,7 +28,7 @@ struct ImageInfo;
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enum class PreemptionMode : uint32_t;
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using CsrContainer = std::vector<std::array<std::unique_ptr<CommandStreamReceiver>, EngineInstanceConstants::numGpgpuEngineInstances>>;
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using CsrContainer = std::vector<std::vector<std::unique_ptr<CommandStreamReceiver>>>;
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enum AllocationUsage {
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TEMPORARY_ALLOCATION,
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -11,7 +11,7 @@
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#include "engine_node.h"
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namespace OCLRT {
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constexpr uint32_t maxOsContextCount = 4u * static_cast<uint32_t>(gpgpuEngineInstances.size());
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constexpr uint32_t maxOsContextCount = 4u * static_cast<uint32_t>(EngineInstanceConstants::numGpgpuEngineInstances);
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struct ResidencyData {
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ResidencyData() {
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2018 Intel Corporation
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* Copyright (C) 2018-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -26,8 +26,8 @@ OsContextLinux::OsContextImpl(Drm &drm, EngineInstanceT engineType) : drm(drm) {
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engineFlag = DrmEngineMapper::engineNodeMap(engineType.type);
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this->drmContextId = drm.createDrmContext();
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if (drm.isPreemptionSupported() &&
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engineType.type == gpgpuEngineInstances[EngineInstanceConstants::lowPriorityGpgpuEngineIndex].type &&
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engineType.id == gpgpuEngineInstances[EngineInstanceConstants::lowPriorityGpgpuEngineIndex].id) {
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engineType.type == lowPriorityGpgpuEngine.type &&
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engineType.id == lowPriorityGpgpuEngine.id) {
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drm.setLowPriorityContextParam(this->drmContextId);
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}
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}
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