diff --git a/level_zero/core/test/unit_tests/sources/cmdlist/test_cmdlist_xehp_and_later.cpp b/level_zero/core/test/unit_tests/sources/cmdlist/test_cmdlist_xehp_and_later.cpp index 9b83061f13..3a39be2bb6 100644 --- a/level_zero/core/test/unit_tests/sources/cmdlist/test_cmdlist_xehp_and_later.cpp +++ b/level_zero/core/test/unit_tests/sources/cmdlist/test_cmdlist_xehp_and_later.cpp @@ -113,9 +113,6 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, CommandListTests, whenCommandListIsCreatedThenPCAnd } EXPECT_EQ(gmmHelper->getMOCS(GMM_RESOURCE_USAGE_OCL_BUFFER_CONST), cmdSba->getStatelessDataPortAccessMemoryObjectControlState()); - - EXPECT_TRUE(cmdSba->getDisableSupportForMultiGpuPartialWritesForStatelessMessages()); - EXPECT_FALSE(cmdSba->getDisableSupportForMultiGpuAtomicsForStatelessAccesses()); } HWTEST2_F(CommandListTests, whenCommandListIsCreatedAndProgramExtendedPipeControlPriorToNonPipelinedStateCommandIsEnabledThenPCAndStateBaseAddressCmdsAreAddedAndCorrectlyProgrammed, IsAtLeastXeHpCore) { @@ -204,9 +201,6 @@ HWTEST2_F(CommandListTests, whenCommandListIsCreatedAndProgramExtendedPipeContro } EXPECT_EQ(gmmHelper->getMOCS(GMM_RESOURCE_USAGE_OCL_BUFFER_CONST), cmdSba->getStatelessDataPortAccessMemoryObjectControlState()); - - EXPECT_TRUE(cmdSba->getDisableSupportForMultiGpuPartialWritesForStatelessMessages()); - EXPECT_FALSE(cmdSba->getDisableSupportForMultiGpuAtomicsForStatelessAccesses()); } using CommandListTestsReserveSize = Test; diff --git a/opencl/test/unit_test/helpers/test_preamble_xehp_and_later.cpp b/opencl/test/unit_test/helpers/test_preamble_xehp_and_later.cpp index 6d372df7ad..7341ab6b0a 100644 --- a/opencl/test/unit_test/helpers/test_preamble_xehp_and_later.cpp +++ b/opencl/test/unit_test/helpers/test_preamble_xehp_and_later.cpp @@ -358,23 +358,17 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, XeHpCommandStreamReceiverFlushTaskTests, whenFlushi HWCMDTEST_F(IGFX_XE_HP_CORE, XeHpCommandStreamReceiverFlushTaskTests, givenDebugKeysThatOverrideMultiGpuSettingWhenStateBaseAddressIsProgrammedThenValuesMatch) { DebugManagerStateRestore restorer; - using STATE_BASE_ADDRESS = typename FamilyType::STATE_BASE_ADDRESS; auto &commandStreamReceiver = pDevice->getUltCommandStreamReceiver(); if (commandStreamReceiver.heaplessStateInitialized) { GTEST_SKIP(); } - debugManager.flags.ForceMultiGpuAtomics.set(0); - debugManager.flags.ForceMultiGpuPartialWrites.set(0); flushTask(commandStreamReceiver); HardwareParse hwParserCsr; hwParserCsr.parseCommands(commandStreamReceiver.commandStream, 0); hwParserCsr.findHardwareCommands(); ASSERT_NE(nullptr, hwParserCsr.cmdStateBaseAddress); - auto stateBaseAddress = static_cast(hwParserCsr.cmdStateBaseAddress); - EXPECT_EQ(0u, stateBaseAddress->getDisableSupportForMultiGpuAtomicsForStatelessAccesses()); - EXPECT_EQ(0u, stateBaseAddress->getDisableSupportForMultiGpuPartialWritesForStatelessMessages()); } using StateBaseAddressXeHPAndLaterTests = XeHpCommandStreamReceiverFlushTaskTests; diff --git a/shared/source/debug_settings/debug_variables_base.inl b/shared/source/debug_settings/debug_variables_base.inl index 513ce84bf0..17da567e6f 100644 --- a/shared/source/debug_settings/debug_variables_base.inl +++ b/shared/source/debug_settings/debug_variables_base.inl @@ -162,8 +162,6 @@ DECLARE_DEBUG_VARIABLE(int32_t, ForceMemoryBankIndexOverride, -1, "-1: default, DECLARE_DEBUG_VARIABLE(int32_t, EnablePrivateScratchSlot1, -1, "-1: default, 0: disable, 1: enable Allows using private scratch space") DECLARE_DEBUG_VARIABLE(int32_t, DisablePipeControlPrecedingPostSyncCommand, -1, "-1 default - disabled adding PIPE_CONTROL, 0 - disabled adding PIPE_CONTROL, 1 - enabled adding PIPE_CONTROL") DECLARE_DEBUG_VARIABLE(int32_t, FormatForStatelessCompressionWithUnifiedMemory, 0xF, "Format for stateless compression with unified memory") -DECLARE_DEBUG_VARIABLE(int32_t, ForceMultiGpuPartialWrites, -1, "-1: default - 0 for multiOsContext capable, 0: program value 0 in MultiGpuPartialWrites controls 1: program value 1 in MultiGpuPartialWrites controls") -DECLARE_DEBUG_VARIABLE(int32_t, ForceMultiGpuAtomics, -1, "-1: default - 0 for multiOsContext capable, 0: program value 0 in MultiGpuAtomics controls 1: program value 1 in MultiGpuAtomics controls") DECLARE_DEBUG_VARIABLE(int32_t, ForceBufferCompressionFormat, -1, "-1: default, >0: Format value") DECLARE_DEBUG_VARIABLE(int32_t, EnableHwGenerationLocalIds, -1, "-1: default, 0: disable, 1: enable : Enables generation of local ids on HW") DECLARE_DEBUG_VARIABLE(int32_t, WalkerPartitionPreferHighestDimension, -1, "-1: default, 0: prefer biggest dimension, 1: prefer Z over Y over X if they divide partition count evenly") diff --git a/shared/source/generated/xe2_hpg_core/hw_cmds_generated_xe2_hpg_core.inl b/shared/source/generated/xe2_hpg_core/hw_cmds_generated_xe2_hpg_core.inl index db0627a327..3ecb5e6995 100644 --- a/shared/source/generated/xe2_hpg_core/hw_cmds_generated_xe2_hpg_core.inl +++ b/shared/source/generated/xe2_hpg_core/hw_cmds_generated_xe2_hpg_core.inl @@ -2909,9 +2909,7 @@ typedef struct tagSTATE_BASE_ADDRESS { uint64_t Reserved_43 : BITFIELD_RANGE(11, 11); uint64_t GeneralStateBaseAddress : BITFIELD_RANGE(12, 63); // DWORD 3 - uint32_t Reserved_96 : BITFIELD_RANGE(0, 13); - uint32_t DisableSupportForMultiGpuAtomicsForStatelessAccesses : BITFIELD_RANGE(14, 14); - uint32_t DisableSupportForMultiGpuPartialWritesForStatelessMessages : BITFIELD_RANGE(15, 15); + uint32_t Reserved_96 : BITFIELD_RANGE(0, 15); uint32_t StatelessDataPortAccessMemoryObjectControlStateEncryptedData : BITFIELD_RANGE(16, 16); uint32_t StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(17, 22); uint32_t L1CacheControlCachePolicy : BITFIELD_RANGE(23, 25); @@ -3061,18 +3059,6 @@ typedef struct tagSTATE_BASE_ADDRESS { inline uint64_t getGeneralStateBaseAddress() const { return TheStructure.Common.GeneralStateBaseAddress << GENERALSTATEBASEADDRESS_BIT_SHIFT; } - inline void setDisableSupportForMultiGpuAtomicsForStatelessAccesses(const bool value) { - TheStructure.Common.DisableSupportForMultiGpuAtomicsForStatelessAccesses = value; - } - inline bool getDisableSupportForMultiGpuAtomicsForStatelessAccesses() const { - return TheStructure.Common.DisableSupportForMultiGpuAtomicsForStatelessAccesses; - } - inline void setDisableSupportForMultiGpuPartialWritesForStatelessMessages(const bool value) { - TheStructure.Common.DisableSupportForMultiGpuPartialWritesForStatelessMessages = value; - } - inline bool getDisableSupportForMultiGpuPartialWritesForStatelessMessages() const { - return TheStructure.Common.DisableSupportForMultiGpuPartialWritesForStatelessMessages; - } inline void setStatelessDataPortAccessMemoryObjectControlStateEncryptedData(const bool value) { TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateEncryptedData = value; } diff --git a/shared/source/generated/xe3_core/hw_cmds_generated_xe3_core.inl b/shared/source/generated/xe3_core/hw_cmds_generated_xe3_core.inl index 951dd3e017..a09445182c 100644 --- a/shared/source/generated/xe3_core/hw_cmds_generated_xe3_core.inl +++ b/shared/source/generated/xe3_core/hw_cmds_generated_xe3_core.inl @@ -2899,9 +2899,7 @@ typedef struct tagSTATE_BASE_ADDRESS { uint64_t Reserved_43 : BITFIELD_RANGE(11, 11); uint64_t GeneralStateBaseAddress : BITFIELD_RANGE(12, 63); // DWORD 3 - uint32_t Reserved_96 : BITFIELD_RANGE(0, 13); - uint32_t DisableSupportForMultiGpuAtomicsForStatelessAccesses : BITFIELD_RANGE(14, 14); - uint32_t DisableSupportForMultiGpuPartialWritesForStatelessMessages : BITFIELD_RANGE(15, 15); + uint32_t Reserved_96 : BITFIELD_RANGE(0, 15); uint32_t StatelessDataPortAccessMemoryObjectControlStateEncryptedData : BITFIELD_RANGE(16, 16); uint32_t StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(17, 22); uint32_t L1CacheControlCachePolicy : BITFIELD_RANGE(23, 25); @@ -3051,18 +3049,6 @@ typedef struct tagSTATE_BASE_ADDRESS { inline uint64_t getGeneralStateBaseAddress() const { return TheStructure.Common.GeneralStateBaseAddress << GENERALSTATEBASEADDRESS_BIT_SHIFT; } - inline void setDisableSupportForMultiGpuAtomicsForStatelessAccesses(const bool value) { - TheStructure.Common.DisableSupportForMultiGpuAtomicsForStatelessAccesses = value; - } - inline bool getDisableSupportForMultiGpuAtomicsForStatelessAccesses() const { - return TheStructure.Common.DisableSupportForMultiGpuAtomicsForStatelessAccesses; - } - inline void setDisableSupportForMultiGpuPartialWritesForStatelessMessages(const bool value) { - TheStructure.Common.DisableSupportForMultiGpuPartialWritesForStatelessMessages = value; - } - inline bool getDisableSupportForMultiGpuPartialWritesForStatelessMessages() const { - return TheStructure.Common.DisableSupportForMultiGpuPartialWritesForStatelessMessages; - } inline void setStatelessDataPortAccessMemoryObjectControlStateEncryptedData(const bool value) { TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateEncryptedData = value; } diff --git a/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl b/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl index 53d752199c..a2e22b437c 100644 --- a/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl +++ b/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl @@ -2913,9 +2913,7 @@ typedef struct tagSTATE_BASE_ADDRESS { // DWORD 3 uint32_t CoherencySettingModifyEnable : BITFIELD_RANGE(0, 0); uint32_t Reserved_97 : BITFIELD_RANGE(1, 12); - uint32_t EnableMemoryCompressionForAllStatelessAccesses : BITFIELD_RANGE(13, 13); - uint32_t DisableSupportForMultiGpuAtomicsForStatelessAccesses : BITFIELD_RANGE(14, 14); - uint32_t DisableSupportForMultiGpuPartialWritesForStatelessMessages : BITFIELD_RANGE(15, 15); + uint32_t EnableMemoryCompressionForAllStatelessAccesses : BITFIELD_RANGE(13, 15); uint32_t StatelessDataPortAccessMemoryObjectControlStateReserved_112 : BITFIELD_RANGE(16, 16); uint32_t StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(17, 22); uint32_t L1CachePolicyL1CacheControl : BITFIELD_RANGE(23, 25); @@ -3078,18 +3076,6 @@ typedef struct tagSTATE_BASE_ADDRESS { inline ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES getEnableMemoryCompressionForAllStatelessAccesses() const { return static_cast(TheStructure.Common.EnableMemoryCompressionForAllStatelessAccesses); } - inline void setDisableSupportForMultiGpuAtomicsForStatelessAccesses(const bool value) { - TheStructure.Common.DisableSupportForMultiGpuAtomicsForStatelessAccesses = value; - } - inline bool getDisableSupportForMultiGpuAtomicsForStatelessAccesses() const { - return TheStructure.Common.DisableSupportForMultiGpuAtomicsForStatelessAccesses; - } - inline void setDisableSupportForMultiGpuPartialWritesForStatelessMessages(const bool value) { - TheStructure.Common.DisableSupportForMultiGpuPartialWritesForStatelessMessages = value; - } - inline bool getDisableSupportForMultiGpuPartialWritesForStatelessMessages() const { - return TheStructure.Common.DisableSupportForMultiGpuPartialWritesForStatelessMessages; - } inline void setStatelessDataPortAccessMemoryObjectControlState(const uint32_t value) { // patched TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateReserved_112 = value; TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables = (value >> 1); diff --git a/shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl b/shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl index e2be7f3118..2aac76d1d9 100644 --- a/shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl +++ b/shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl @@ -2661,8 +2661,7 @@ typedef struct tagSTATE_BASE_ADDRESS { // DWORD 3 uint32_t Reserved_96 : BITFIELD_RANGE(0, 12); uint32_t EnableMemoryCompressionForAllStatelessAccesses : BITFIELD_RANGE(13, 13); - uint32_t DisableSupportForMultiGpuAtomicsForStatelessAccesses : BITFIELD_RANGE(14, 14); - uint32_t DisableSupportForMultiGpuPartialWritesForStatelessMessages : BITFIELD_RANGE(15, 15); + uint32_t Reserved_110 : BITFIELD_RANGE(14, 15); uint32_t StatelessDataPortAccessMemoryObjectControlState_Reserved : BITFIELD_RANGE(16, 16); uint32_t StatelessDataPortAccessMemoryObjectControlState_IndexToMocsTables : BITFIELD_RANGE(17, 22); uint32_t L1CachePolicyL1CacheControl : BITFIELD_RANGE(23, 25); @@ -2821,18 +2820,6 @@ typedef struct tagSTATE_BASE_ADDRESS { inline ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES getEnableMemoryCompressionForAllStatelessAccesses() const { return static_cast(TheStructure.Common.EnableMemoryCompressionForAllStatelessAccesses); } - inline void setDisableSupportForMultiGpuAtomicsForStatelessAccesses(const bool value) { - TheStructure.Common.DisableSupportForMultiGpuAtomicsForStatelessAccesses = value; - } - inline bool getDisableSupportForMultiGpuAtomicsForStatelessAccesses() const { - return (TheStructure.Common.DisableSupportForMultiGpuAtomicsForStatelessAccesses); - } - inline void setDisableSupportForMultiGpuPartialWritesForStatelessMessages(const bool value) { - TheStructure.Common.DisableSupportForMultiGpuPartialWritesForStatelessMessages = value; - } - inline bool getDisableSupportForMultiGpuPartialWritesForStatelessMessages() const { - return (TheStructure.Common.DisableSupportForMultiGpuPartialWritesForStatelessMessages); - } inline void setStatelessDataPortAccessMemoryObjectControlStateReserved(const uint32_t value) { TheStructure.Common.StatelessDataPortAccessMemoryObjectControlState_Reserved = value; } diff --git a/shared/source/helpers/state_base_address_xehp_and_later.inl b/shared/source/helpers/state_base_address_xehp_and_later.inl index 18a7d1670a..7ebd5b9a5c 100644 --- a/shared/source/helpers/state_base_address_xehp_and_later.inl +++ b/shared/source/helpers/state_base_address_xehp_and_later.inl @@ -83,16 +83,6 @@ void StateBaseAddressHelper::appendStateBaseAddressParameters( args.stateBaseAddressCmd->setBindlessSurfaceStateMemoryObjectControlState(heapMocsValue); args.stateBaseAddressCmd->setBindlessSamplerStateMemoryObjectControlState(heapMocsValue); - args.stateBaseAddressCmd->setDisableSupportForMultiGpuPartialWritesForStatelessMessages(!args.isMultiOsContextCapable); - - if (debugManager.flags.ForceMultiGpuAtomics.get() != -1) { - args.stateBaseAddressCmd->setDisableSupportForMultiGpuAtomicsForStatelessAccesses(!!debugManager.flags.ForceMultiGpuAtomics.get()); - } - - if (debugManager.flags.ForceMultiGpuPartialWrites.get() != -1) { - args.stateBaseAddressCmd->setDisableSupportForMultiGpuPartialWritesForStatelessMessages(!!debugManager.flags.ForceMultiGpuPartialWrites.get()); - } - if (args.memoryCompressionState != MemoryCompressionState::notApplicable) { setSbaStatelessCompressionParams(args.stateBaseAddressCmd, args.memoryCompressionState); } diff --git a/shared/test/common/test_files/igdrcl.config b/shared/test/common/test_files/igdrcl.config index 24bb9d329b..411ff2d3c5 100644 --- a/shared/test/common/test_files/igdrcl.config +++ b/shared/test/common/test_files/igdrcl.config @@ -320,8 +320,6 @@ OverrideMultiStoragePlacement = -1 ForceMultiTileAllocPlacement = 0 ForceSingleTileAllocPlacement = 0 FormatForStatelessCompressionWithUnifiedMemory = 0xF -ForceMultiGpuPartialWrites = -1 -ForceMultiGpuAtomics = -1 ForceBufferCompressionFormat = -1 ExperimentalSetWalkerPartitionCount = 0 EnableStatelessCompressionWithUnifiedMemory = 0