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Enable L1 cache for Tigerlake

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Change-Id: I33513ed084f9d06ceca11315cac03f1b682db535
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
Related-To: NEO-4832
This commit is contained in:
Maciej Dziuban
2020-10-01 12:22:54 +02:00
committed by sys_ocldev
parent ec054a87da
commit 138f04bdcd
19 changed files with 352 additions and 12 deletions
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5
opencl/source/mem_obj/buffer_base.inl
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@@ -36,10 +36,11 @@ template <typename GfxFamily>
void BufferHw<GfxFamily>::setArgStateful(void *memory, bool forceNonAuxMode, bool disableL3, bool alignSizeForAuxTranslation, bool isReadOnlyArgument, const Device &device) {
auto rootDeviceIndex = device.getRootDeviceIndex();
auto graphicsAllocation = multiGraphicsAllocation.getGraphicsAllocation(rootDeviceIndex);
const auto isReadOnly = isValueSet(getFlags(), CL_MEM_READ_ONLY) || isReadOnlyArgument;
EncodeSurfaceState<GfxFamily>::encodeBuffer(memory, getBufferAddress(rootDeviceIndex),
getSurfaceSize(alignSizeForAuxTranslation, rootDeviceIndex),
getMocsValue(disableL3, isReadOnlyArgument, rootDeviceIndex),
true, forceNonAuxMode, device.getNumAvailableDevices(),
getMocsValue(disableL3, isReadOnly, rootDeviceIndex),
true, forceNonAuxMode, isReadOnly, device.getNumAvailableDevices(),
graphicsAllocation, device.getGmmHelper());
appendSurfaceStateExt(memory);
}