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Enable L1 cache for Tigerlake
Change-Id: I33513ed084f9d06ceca11315cac03f1b682db535 Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com> Related-To: NEO-4832
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sys_ocldev
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@@ -47,6 +47,24 @@ void EncodeWA<Family>::encodeAdditionalPipelineSelect(Device &device, LinearStre
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}
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}
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template <>
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void EncodeSurfaceState<Family>::encodeExtraBufferParams(R_SURFACE_STATE *surfaceState, GraphicsAllocation *allocation, GmmHelper *gmmHelper,
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bool isReadOnly, uint32_t numAvailableDevices) {
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const bool isL3Allowed = surfaceState->getMemoryObjectControlState() == gmmHelper->getMOCS(GMM_RESOURCE_USAGE_OCL_BUFFER);
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if (isL3Allowed) {
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const bool isConstantSurface = allocation && allocation->getAllocationType() == GraphicsAllocation::AllocationType::CONSTANT_SURFACE;
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bool useL1 = isReadOnly || isConstantSurface;
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if (DebugManager.flags.ForceL1Caching.get() != -1) {
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useL1 = !!DebugManager.flags.ForceL1Caching.get();
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}
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if (useL1) {
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surfaceState->setMemoryObjectControlState(gmmHelper->getMOCS(GMM_RESOURCE_USAGE_OCL_BUFFER_CONST));
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}
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}
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}
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template struct EncodeDispatchKernel<Family>;
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template struct EncodeStates<Family>;
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template struct EncodeMath<Family>;
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