Add HW commands const definitions

Change-Id: If2e9d7f7f707b7b8c7bd8dbd3853ab3b6dad0c9a
2026-01-09 22:43:00 +08:00 · 2019-01-17 17:10:12 +01:00
parent 0c2f5aa491
commit 158f200476
48 changed files with 371 additions and 154 deletions
--- a/runtime/command_queue/gpgpu_walker.inl
+++ b/runtime/command_queue/gpgpu_walker.inl
@@ -39,14 +39,14 @@ void GpgpuWalkerHelper<GfxFamily>::addAluReadModifyWriteRegister(
    typedef typename GfxFamily::MI_MATH MI_MATH;
    typedef typename GfxFamily::MI_MATH_ALU_INST_INLINE MI_MATH_ALU_INST_INLINE;
    auto pCmd = reinterpret_cast<MI_LOAD_REGISTER_REG *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_REG)));
-    *pCmd = MI_LOAD_REGISTER_REG::sInit();
+    *pCmd = GfxFamily::cmdInitLoadRegisterReg;
    pCmd->setSourceRegisterAddress(aluRegister);
    pCmd->setDestinationRegisterAddress(CS_GPR_R0);

    // Load "Mask" into CS_GPR_R1
    typedef typename GfxFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
    auto pCmd2 = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM)));
-    *pCmd2 = MI_LOAD_REGISTER_IMM::sInit();
+    *pCmd2 = GfxFamily::cmdInitLoadRegisterImm;
    pCmd2->setRegisterOffset(CS_GPR_R1);
    pCmd2->setDataDword(mask);

@@ -85,13 +85,13 @@ void GpgpuWalkerHelper<GfxFamily>::addAluReadModifyWriteRegister(

    // LOAD value of CS_GPR_R0 into "Register"
    auto pCmd4 = reinterpret_cast<MI_LOAD_REGISTER_REG *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_REG)));
-    *pCmd4 = MI_LOAD_REGISTER_REG::sInit();
+    *pCmd4 = GfxFamily::cmdInitLoadRegisterReg;
    pCmd4->setSourceRegisterAddress(CS_GPR_R0);
    pCmd4->setDestinationRegisterAddress(aluRegister);

    // Add PIPE_CONTROL to flush caches
    auto pCmd5 = reinterpret_cast<PIPE_CONTROL *>(pCommandStream->getSpace(sizeof(PIPE_CONTROL)));
-    *pCmd5 = PIPE_CONTROL::sInit();
+    *pCmd5 = GfxFamily::cmdInitPipeControl;
    pCmd5->setCommandStreamerStallEnable(true);
    pCmd5->setDcFlushEnable(true);
    pCmd5->setTextureCacheInvalidationEnable(true);
@@ -115,7 +115,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchProfilingCommandsStart(

    //low part
    auto pMICmdLow = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
-    *pMICmdLow = MI_STORE_REGISTER_MEM::sInit();
+    *pMICmdLow = GfxFamily::cmdInitStoreRegisterMem;
    adjustMiStoreRegMemMode(pMICmdLow);
    pMICmdLow->setRegisterAddress(GP_THREAD_TIME_REG_ADDRESS_OFFSET_LOW);
    pMICmdLow->setMemoryAddress(TimeStampAddress);
@@ -130,7 +130,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchProfilingCommandsEnd(

    // PIPE_CONTROL for global timestamp
    auto pPipeControlCmd = (PIPE_CONTROL *)commandStream->getSpace(sizeof(PIPE_CONTROL));
-    *pPipeControlCmd = PIPE_CONTROL::sInit();
+    *pPipeControlCmd = GfxFamily::cmdInitPipeControl;
    pPipeControlCmd->setCommandStreamerStallEnable(true);

    //MI_STORE_REGISTER_MEM for context local timestamp
@@ -138,7 +138,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchProfilingCommandsEnd(

    //low part
    auto pMICmdLow = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
-    *pMICmdLow = MI_STORE_REGISTER_MEM::sInit();
+    *pMICmdLow = GfxFamily::cmdInitStoreRegisterMem;
    adjustMiStoreRegMemMode(pMICmdLow);
    pMICmdLow->setRegisterAddress(GP_THREAD_TIME_REG_ADDRESS_OFFSET_LOW);
    pMICmdLow->setMemoryAddress(TimeStampAddress);
@@ -157,7 +157,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersNoopidRegisterCommands(
                             : reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.DMAFenceIdEnd));

    auto pNoopIdRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
-    *pNoopIdRegister = MI_STORE_REGISTER_MEM::sInit();
+    *pNoopIdRegister = GfxFamily::cmdInitStoreRegisterMem;
    pNoopIdRegister->setRegisterAddress(OCLRT::INSTR_MMIO_NOOPID);
    pNoopIdRegister->setMemoryAddress(address);
 }
@@ -175,7 +175,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersReadFreqRegisterCommands(
                             : reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.CoreFreqEnd));

    auto pCoreFreqRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
-    *pCoreFreqRegister = MI_STORE_REGISTER_MEM::sInit();
+    *pCoreFreqRegister = GfxFamily::cmdInitStoreRegisterMem;
    pCoreFreqRegister->setRegisterAddress(OCLRT::INSTR_MMIO_RPSTAT1);
    pCoreFreqRegister->setMemoryAddress(address);
 }
@@ -195,7 +195,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersGeneralPurposeCounterComm
    // Read General Purpose counters
    for (uint16_t i = 0; i < OCLRT::INSTR_GENERAL_PURPOSE_COUNTERS_COUNT; i++) {
        auto pGeneralPurposeRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
-        *pGeneralPurposeRegister = MI_STORE_REGISTER_MEM::sInit();
+        *pGeneralPurposeRegister = GfxFamily::cmdInitStoreRegisterMem;
        uint32_t regAddr = INSTR_GFX_OFFSETS::INSTR_PERF_CNT_1_DW0 + i * sizeof(cl_uint);
        pGeneralPurposeRegister->setRegisterAddress(regAddr);
        //Gp field is 2*uint64 wide so it can hold 4 uint32
@@ -223,7 +223,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersUserCounterCommands(

    for (uint32_t i = 0; i < userRegs->RegsCount; i++) {
        auto pRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
-        *pRegister = MI_STORE_REGISTER_MEM::sInit();
+        *pRegister = GfxFamily::cmdInitStoreRegisterMem;

        regAddr = userRegs->Reg[i].Offset;
        pRegister->setRegisterAddress(regAddr);
@@ -234,7 +234,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersUserCounterCommands(

        if (userRegs->Reg[i].BitSize > 32) {
            pRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
-            *pRegister = MI_STORE_REGISTER_MEM::sInit();
+            *pRegister = GfxFamily::cmdInitStoreRegisterMem;

            regAddr += sizeof(cl_uint);
            pRegister->setRegisterAddress(regAddr);
@@ -256,21 +256,21 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersOABufferStateCommands(
    uint64_t address = 0;
    //OA Status
    auto pOaRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
-    *pOaRegister = MI_STORE_REGISTER_MEM::sInit();
+    *pOaRegister = GfxFamily::cmdInitStoreRegisterMem;
    pOaRegister->setRegisterAddress(INSTR_GFX_OFFSETS::INSTR_OA_STATUS);
    address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.OaStatus));
    pOaRegister->setMemoryAddress(address);

    //OA Head
    pOaRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
-    *pOaRegister = MI_STORE_REGISTER_MEM::sInit();
+    *pOaRegister = GfxFamily::cmdInitStoreRegisterMem;
    pOaRegister->setRegisterAddress(INSTR_GFX_OFFSETS::INSTR_OA_HEAD_PTR);
    address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.OaHead));
    pOaRegister->setMemoryAddress(address);

    //OA Tail
    pOaRegister = (MI_STORE_REGISTER_MEM *)commandStream->getSpace(sizeof(MI_STORE_REGISTER_MEM));
-    *pOaRegister = MI_STORE_REGISTER_MEM::sInit();
+    *pOaRegister = GfxFamily::cmdInitStoreRegisterMem;
    pOaRegister->setRegisterAddress(INSTR_GFX_OFFSETS::INSTR_OA_TAIL_PTR);
    address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.OaTail));
    pOaRegister->setMemoryAddress(address);
@@ -291,7 +291,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersCommandsStart(
    uint64_t address = 0;
    //flush command streamer
    auto pPipeControlCmd = (PIPE_CONTROL *)commandStream->getSpace(sizeof(PIPE_CONTROL));
-    *pPipeControlCmd = PIPE_CONTROL::sInit();
+    *pPipeControlCmd = GfxFamily::cmdInitPipeControl;
    pPipeControlCmd->setCommandStreamerStallEnable(true);

    //Store value of NOOPID register
@@ -303,7 +303,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersCommandsStart(
    GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersGeneralPurposeCounterCommands(commandQueue, hwPerfCounter, commandStream, true);

    auto pReportPerfCount = (MI_REPORT_PERF_COUNT *)commandStream->getSpace(sizeof(MI_REPORT_PERF_COUNT));
-    *pReportPerfCount = MI_REPORT_PERF_COUNT::sInit();
+    *pReportPerfCount = GfxFamily::cmdInitReportPerfCount;
    pReportPerfCount->setReportId(currentReportId);
    address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.HwPerfReportBegin.Oa));
    pReportPerfCount->setMemoryAddress(address);
@@ -333,7 +333,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersCommandsEnd(

    //flush command streamer
    auto pPipeControlCmd = (PIPE_CONTROL *)commandStream->getSpace(sizeof(PIPE_CONTROL));
-    *pPipeControlCmd = PIPE_CONTROL::sInit();
+    *pPipeControlCmd = GfxFamily::cmdInitPipeControl;
    pPipeControlCmd->setCommandStreamerStallEnable(true);

    GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersOABufferStateCommands(commandQueue, hwPerfCounter, commandStream);
@@ -343,7 +343,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersCommandsEnd(
    PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(commandStream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, address, 0llu);

    auto pReportPerfCount = (MI_REPORT_PERF_COUNT *)commandStream->getSpace(sizeof(MI_REPORT_PERF_COUNT));
-    *pReportPerfCount = MI_REPORT_PERF_COUNT::sInit();
+    *pReportPerfCount = GfxFamily::cmdInitReportPerfCount;
    pReportPerfCount->setReportId(currentReportId);
    address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWPerfCounters.HwPerfReportEnd.Oa));
    pReportPerfCount->setMemoryAddress(address);
--- a/runtime/command_queue/gpgpu_walker_base.inl
+++ b/runtime/command_queue/gpgpu_walker_base.inl
@@ -165,7 +165,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchScheduler(

        // Add BB Start Cmd to the SLB in the Primary Batch Buffer
        auto *bbStart = (MI_BATCH_BUFFER_START *)commandStream->getSpace(sizeof(MI_BATCH_BUFFER_START));
-        *bbStart = MI_BATCH_BUFFER_START::sInit();
+        *bbStart = GfxFamily::cmdInitBatchBufferStart;
        bbStart->setSecondLevelBatchBuffer(MI_BATCH_BUFFER_START::SECOND_LEVEL_BATCH_BUFFER_FIRST_LEVEL_BATCH);
        uint64_t slbAddress = devQueueHw.getSlbBuffer()->getGpuAddress();
        bbStart->setBatchBufferStartAddressGraphicsaddress472(slbAddress);
--- a/runtime/command_stream/aub_command_stream_receiver_hw.inl
+++ b/runtime/command_stream/aub_command_stream_receiver_hw.inl
@@ -478,7 +478,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::submitBatchBuffer(size_t engineIndex
            pTail = engineInfo.pRingBuffer;
        } else if (engineInfo.tailRingBuffer == 0) {
            // Add a LRI if this is our first submission
-            auto lri = MI_LOAD_REGISTER_IMM::sInit();
+            auto lri = GfxFamily::cmdInitLoadRegisterImm;
            lri.setRegisterOffset(AubMemDump::computeRegisterOffset(csTraits.mmioBase, 0x2244));
            lri.setDataDword(0x00010000);
            *(MI_LOAD_REGISTER_IMM *)pTail = lri;
@@ -486,7 +486,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::submitBatchBuffer(size_t engineIndex
        }

        // Add our BBS
-        auto bbs = MI_BATCH_BUFFER_START::sInit();
+        auto bbs = GfxFamily::cmdInitBatchBufferStart;
        bbs.setBatchBufferStartAddressGraphicsaddress472(static_cast<uint64_t>(batchBufferGpuAddress));
        bbs.setAddressSpaceIndicator(MI_BATCH_BUFFER_START::ADDRESS_SPACE_INDICATOR_PPGTT);
        *(MI_BATCH_BUFFER_START *)pTail = bbs;
@@ -497,7 +497,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::submitBatchBuffer(size_t engineIndex

        // Add NOOPs as needed as our tail needs to be aligned
        while (engineInfo.tailRingBuffer % tailAlignment) {
-            *(MI_NOOP *)pTail = MI_NOOP::sInit();
+            *(MI_NOOP *)pTail = GfxFamily::cmdInitNoop;
            pTail = ((MI_NOOP *)pTail) + 1;
            engineInfo.tailRingBuffer = (uint32_t)ptrDiff(pTail, engineInfo.pRingBuffer);
        }
@@ -789,7 +789,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::addGUCStartMessage(uint64_t batchBuf

    MI_BATCH_BUFFER_START *miBatchBufferStart = linearStream.getSpaceForCmd<MI_BATCH_BUFFER_START>();
    DEBUG_BREAK_IF(bufferSize != linearStream.getUsed());
-    miBatchBufferStart->init();
+    *miBatchBufferStart = GfxFamily::cmdInitBatchBufferStart;
    miBatchBufferStart->setBatchBufferStartAddressGraphicsaddress472(AUB::ptrToPPGTT(buffer.get()));
    miBatchBufferStart->setAddressSpaceIndicator(MI_BATCH_BUFFER_START::ADDRESS_SPACE_INDICATOR_PPGTT);

--- a/runtime/command_stream/command_stream_receiver_hw.inl
+++ b/runtime/command_stream/command_stream_receiver_hw.inl
@@ -265,7 +265,7 @@ CompletionStamp CommandStreamReceiverHw<GfxFamily>::flushTask(
    if (stallingPipeControlOnNextFlushRequired) {
        stallingPipeControlOnNextFlushRequired = false;
        auto stallingPipeControlCmd = commandStream.getSpaceForCmd<PIPE_CONTROL>();
-        *stallingPipeControlCmd = PIPE_CONTROL::sInit();
+        *stallingPipeControlCmd = GfxFamily::cmdInitPipeControl;
        stallingPipeControlCmd->setCommandStreamerStallEnable(true);
    }
    initPageTableManagerRegisters(commandStreamCSR);
--- a/runtime/command_stream/experimental_command_buffer.inl
+++ b/runtime/command_stream/experimental_command_buffer.inl
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Intel Corporation
+ * Copyright (C) 2018-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -94,7 +94,7 @@ void ExperimentalCommandBuffer::addExperimentalCommands() {
    uint64_t gpuAddr = experimentalAllocation->getGpuAddress() + experimentalAllocationOffset;

    auto semaphoreCmd = reinterpret_cast<MI_SEMAPHORE_WAIT *>(currentStream->getSpace(sizeof(MI_SEMAPHORE_WAIT)));
-    *semaphoreCmd = MI_SEMAPHORE_WAIT::sInit();
+    *semaphoreCmd = GfxFamily::cmdInitMiSemaphoreWait;
    semaphoreCmd->setCompareOperation(MI_SEMAPHORE_WAIT::COMPARE_OPERATION_SAD_EQUAL_SDD);
    semaphoreCmd->setSemaphoreDataDword(*semaphoreData);
    semaphoreCmd->setSemaphoreGraphicsAddress(gpuAddr);
--- a/runtime/command_stream/preemption.inl
+++ b/runtime/command_stream/preemption.inl
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2018 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -36,7 +36,7 @@ void PreemptionHelper::applyPreemptionWaCmdsBegin(LinearStream *pCommandStream,
        preemptionMode == PreemptionMode::MidThread) {
        if (device.getWaTable()->waModifyVFEStateAfterGPGPUPreemption) {
            auto pCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM)));
-            *pCmd = MI_LOAD_REGISTER_IMM::sInit();
+            *pCmd = GfxFamily::cmdInitLoadRegisterImm;
            pCmd->setRegisterOffset(CS_GPR_R0);
            pCmd->setDataDword(GPGPU_WALKER_COOKIE_VALUE_BEFORE_WALKER);
        }
@@ -51,7 +51,7 @@ void PreemptionHelper::applyPreemptionWaCmdsEnd(LinearStream *pCommandStream, co
        preemptionMode == PreemptionMode::MidThread) {
        if (device.getWaTable()->waModifyVFEStateAfterGPGPUPreemption) {
            auto pCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM)));
-            *pCmd = MI_LOAD_REGISTER_IMM::sInit();
+            *pCmd = GfxFamily::cmdInitLoadRegisterImm;
            pCmd->setRegisterOffset(CS_GPR_R0);
            pCmd->setDataDword(GPGPU_WALKER_COOKIE_VALUE_AFTER_WALKER);
        }
@@ -66,7 +66,7 @@ void PreemptionHelper::programCsrBaseAddress(LinearStream &preambleCmdStream, De
        UNRECOVERABLE_IF(nullptr == preemptionCsr);

        auto csr = reinterpret_cast<GPGPU_CSR_BASE_ADDRESS *>(preambleCmdStream.getSpace(sizeof(GPGPU_CSR_BASE_ADDRESS)));
-        csr->init();
+        *csr = GfxFamily::cmdInitGpgpuCsrBaseAddress;
        csr->setGpgpuCsrBaseAddress(preemptionCsr->getGpuAddressToPatch());
    }
 }
@@ -79,7 +79,7 @@ void PreemptionHelper::programStateSip(LinearStream &preambleCmdStream, Device &

    if (isMidThreadPreemption || sourceLevelDebuggerActive) {
        auto sip = reinterpret_cast<STATE_SIP *>(preambleCmdStream.getSpace(sizeof(STATE_SIP)));
-        sip->init();
+        *sip = GfxFamily::cmdInitStateSip;
        auto sipType = SipKernel::getSipKernelType(device.getHardwareInfo().pPlatform->eRenderCoreFamily, sourceLevelDebuggerActive);
        sip->setSystemInstructionPointer(device.getExecutionEnvironment()->getBuiltIns()->getSipKernel(sipType, device).getSipAllocation()->getGpuAddressToPatch());
    }
--- a/runtime/command_stream/tbx_command_stream_receiver_hw.inl
+++ b/runtime/command_stream/tbx_command_stream_receiver_hw.inl
@@ -275,7 +275,7 @@ void TbxCommandStreamReceiverHw<GfxFamily>::submitBatchBuffer(size_t engineIndex
            pTail = engineInfo.pRingBuffer;
        } else if (engineInfo.tailRingBuffer == 0) {
            // Add a LRI if this is our first submission
-            auto lri = MI_LOAD_REGISTER_IMM::sInit();
+            auto lri = GfxFamily::cmdInitLoadRegisterImm;
            lri.setRegisterOffset(AubMemDump::computeRegisterOffset(csTraits.mmioBase, 0x2244));
            lri.setDataDword(0x00010000);
            *(MI_LOAD_REGISTER_IMM *)pTail = lri;
@@ -283,14 +283,14 @@ void TbxCommandStreamReceiverHw<GfxFamily>::submitBatchBuffer(size_t engineIndex
        }

        // Add our BBS
-        auto bbs = MI_BATCH_BUFFER_START::sInit();
+        auto bbs = GfxFamily::cmdInitBatchBufferStart;
        bbs.setBatchBufferStartAddressGraphicsaddress472(AUB::ptrToPPGTT(batchBuffer));
        bbs.setAddressSpaceIndicator(MI_BATCH_BUFFER_START::ADDRESS_SPACE_INDICATOR_PPGTT);
        *(MI_BATCH_BUFFER_START *)pTail = bbs;
        pTail = ((MI_BATCH_BUFFER_START *)pTail) + 1;

        // Add a NOOP as our tail needs to be aligned to a QWORD
-        *(MI_NOOP *)pTail = MI_NOOP::sInit();
+        *(MI_NOOP *)pTail = GfxFamily::cmdInitNoop;
        pTail = ((MI_NOOP *)pTail) + 1;

        // Compute our new ring tail.
--- a/runtime/device_queue/device_queue_hw.inl
+++ b/runtime/device_queue/device_queue_hw.inl
@@ -104,7 +104,7 @@ size_t DeviceQueueHw<GfxFamily>::getMinimumSlbSize() {

 template <typename GfxFamily>
 void DeviceQueueHw<GfxFamily>::initPipeControl(PIPE_CONTROL *pc) {
-    *pc = PIPE_CONTROL::sInit();
+    *pc = GfxFamily::cmdInitPipeControl;
    pc->setStateCacheInvalidationEnable(0x1);
    pc->setDcFlushEnable(true);
    pc->setPipeControlFlushEnable(true);
@@ -136,14 +136,14 @@ void DeviceQueueHw<GfxFamily>::buildSlbDummyCommands() {

    for (size_t i = 0; i < numEnqueues; i++) {
        auto mediaStateFlush = slbCS.getSpaceForCmd<MEDIA_STATE_FLUSH>();
-        *mediaStateFlush = MEDIA_STATE_FLUSH::sInit();
+        *mediaStateFlush = GfxFamily::cmdInitMediaStateFlush;

        addArbCheckCmdWa();

        addMiAtomicCmdWa((uint64_t)&igilCmdQueue->m_controls.m_DummyAtomicOperationPlaceholder);

        auto mediaIdLoad = slbCS.getSpaceForCmd<MEDIA_INTERFACE_DESCRIPTOR_LOAD>();
-        *mediaIdLoad = MEDIA_INTERFACE_DESCRIPTOR_LOAD::sInit();
+        *mediaIdLoad = GfxFamily::cmdInitMediaInterfaceDescriptorLoad;
        mediaIdLoad->setInterfaceDescriptorTotalLength(2048);

        auto dataStartAddress = colorCalcStateSize;
@@ -164,7 +164,7 @@ void DeviceQueueHw<GfxFamily>::buildSlbDummyCommands() {
        }

        auto gpgpuWalker = slbCS.getSpaceForCmd<GPGPU_WALKER>();
-        *gpgpuWalker = GPGPU_WALKER::sInit();
+        *gpgpuWalker = GfxFamily::cmdInitGpgpuWalker;
        gpgpuWalker->setSimdSize(GPGPU_WALKER::SIMD_SIZE::SIMD_SIZE_SIMD16);
        gpgpuWalker->setThreadGroupIdXDimension(1);
        gpgpuWalker->setThreadGroupIdYDimension(1);
@@ -173,7 +173,7 @@ void DeviceQueueHw<GfxFamily>::buildSlbDummyCommands() {
        gpgpuWalker->setBottomExecutionMask(0xFFFFFFFF);

        mediaStateFlush = slbCS.getSpaceForCmd<MEDIA_STATE_FLUSH>();
-        *mediaStateFlush = MEDIA_STATE_FLUSH::sInit();
+        *mediaStateFlush = GfxFamily::cmdInitMediaStateFlush;

        addArbCheckCmdWa();

@@ -193,7 +193,7 @@ void DeviceQueueHw<GfxFamily>::buildSlbDummyCommands() {
    slbCS.getSpace(bbStartOffset);

    auto bbStart = slbCS.getSpaceForCmd<MI_BATCH_BUFFER_START>();
-    *bbStart = MI_BATCH_BUFFER_START::sInit();
+    *bbStart = GfxFamily::cmdInitBatchBufferStart;
    auto slbPtr = reinterpret_cast<uintptr_t>(slbBuffer->getUnderlyingBuffer());
    bbStart->setBatchBufferStartAddressGraphicsaddress472(slbPtr);

@@ -240,7 +240,7 @@ void DeviceQueueHw<GfxFamily>::addExecutionModelCleanUpSection(Kernel *parentKer
    addMediaStateClearCmds();

    auto pBBE = slbCS.getSpaceForCmd<MI_BATCH_BUFFER_END>();
-    *pBBE = MI_BATCH_BUFFER_END::sInit();
+    *pBBE = GfxFamily::cmdInitBatchBufferEnd;

    igilQueue->m_controls.m_CleanupSectionSize = (uint32_t)(slbCS.getUsed() - offset);
 }
@@ -385,7 +385,7 @@ template <typename GfxFamily>
 void DeviceQueueHw<GfxFamily>::addLriCmd(bool setArbCheck) {
    using MI_LOAD_REGISTER_IMM = typename GfxFamily::MI_LOAD_REGISTER_IMM;
    auto lri = slbCS.getSpaceForCmd<MI_LOAD_REGISTER_IMM>();
-    *lri = MI_LOAD_REGISTER_IMM::sInit();
+    *lri = GfxFamily::cmdInitLoadRegisterImm;
    lri->setRegisterOffset(0x2248); // CTXT_PREMP_DBG offset
    if (setArbCheck)
        lri->setDataDword(0x00000100); // set only bit 8 (Preempt On MI_ARB_CHK Only)
@@ -400,7 +400,7 @@ void DeviceQueueHw<GfxFamily>::addMediaStateClearCmds() {
    addPipeControlCmdWa();

    auto pipeControl = slbCS.getSpaceForCmd<PIPE_CONTROL>();
-    *pipeControl = PIPE_CONTROL::sInit();
+    *pipeControl = GfxFamily::cmdInitPipeControl;
    pipeControl->setGenericMediaStateClear(true);
    pipeControl->setCommandStreamerStallEnable(true);

--- a/runtime/device_queue/device_queue_hw_profiling.inl
+++ b/runtime/device_queue/device_queue_hw_profiling.inl
@@ -11,12 +11,12 @@ template <typename GfxFamily>
 void DeviceQueueHw<GfxFamily>::addProfilingEndCmds(uint64_t timestampAddress) {

    auto pPipeControlCmd = (PIPE_CONTROL *)slbCS.getSpace(sizeof(PIPE_CONTROL));
-    *pPipeControlCmd = PIPE_CONTROL::sInit();
+    *pPipeControlCmd = GfxFamily::cmdInitPipeControl;
    pPipeControlCmd->setCommandStreamerStallEnable(true);

    //low part
    auto pMICmdLow = (MI_STORE_REGISTER_MEM *)slbCS.getSpace(sizeof(MI_STORE_REGISTER_MEM));
-    *pMICmdLow = MI_STORE_REGISTER_MEM::sInit();
+    *pMICmdLow = GfxFamily::cmdInitStoreRegisterMem;
    GpgpuWalkerHelper<GfxFamily>::adjustMiStoreRegMemMode(pMICmdLow);
    pMICmdLow->setRegisterAddress(GP_THREAD_TIME_REG_ADDRESS_OFFSET_LOW);
    pMICmdLow->setMemoryAddress(timestampAddress);
--- a/runtime/gen10/command_stream_receiver_hw_gen10.cpp
+++ b/runtime/gen10/command_stream_receiver_hw_gen10.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2018 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -66,5 +66,23 @@ const Family::MI_BATCH_BUFFER_START Family::cmdInitBatchBufferStart = Family::MI
 const Family::MI_BATCH_BUFFER_END Family::cmdInitBatchBufferEnd = Family::MI_BATCH_BUFFER_END::sInit();
 const Family::PIPE_CONTROL Family::cmdInitPipeControl = Family::PIPE_CONTROL::sInit();
 const Family::MI_SEMAPHORE_WAIT Family::cmdInitMiSemaphoreWait = Family::MI_SEMAPHORE_WAIT::sInit();
-const Family::RENDER_SURFACE_STATE Family::cmdRenderSurfaceState = Family::RENDER_SURFACE_STATE::sInit();
+const Family::RENDER_SURFACE_STATE Family::cmdInitRenderSurfaceState = Family::RENDER_SURFACE_STATE::sInit();
+const Family::MI_LOAD_REGISTER_IMM Family::cmdInitLoadRegisterImm = Family::MI_LOAD_REGISTER_IMM::sInit();
+const Family::MI_LOAD_REGISTER_REG Family::cmdInitLoadRegisterReg = Family::MI_LOAD_REGISTER_REG::sInit();
+const Family::MI_LOAD_REGISTER_MEM Family::cmdInitLoadRegisterMem = Family::MI_LOAD_REGISTER_MEM::sInit();
+const Family::MI_STORE_DATA_IMM Family::cmdInitStoreDataImm = Family::MI_STORE_DATA_IMM::sInit();
+const Family::MI_STORE_REGISTER_MEM Family::cmdInitStoreRegisterMem = Family::MI_STORE_REGISTER_MEM::sInit();
+const Family::MI_NOOP Family::cmdInitNoop = Family::MI_NOOP::sInit();
+const Family::MI_REPORT_PERF_COUNT Family::cmdInitReportPerfCount = Family::MI_REPORT_PERF_COUNT::sInit();
+const Family::MI_ATOMIC Family::cmdInitAtomic = Family::MI_ATOMIC::sInit();
+const Family::PIPELINE_SELECT Family::cmdInitPipelineSelect = Family::PIPELINE_SELECT::sInit();
+const Family::MI_ARB_CHECK Family::cmdInitArbCheck = Family::MI_ARB_CHECK::sInit();
+const Family::MEDIA_VFE_STATE Family::cmdInitMediaVfeState = Family::MEDIA_VFE_STATE::sInit();
+const Family::STATE_BASE_ADDRESS Family::cmdInitStateBaseAddress = Family::STATE_BASE_ADDRESS::sInit();
+const Family::MEDIA_SURFACE_STATE Family::cmdInitMediaSurfaceState = Family::MEDIA_SURFACE_STATE::sInit();
+const Family::SAMPLER_STATE Family::cmdInitSamplerState = Family::SAMPLER_STATE::sInit();
+const Family::GPGPU_CSR_BASE_ADDRESS Family::cmdInitGpgpuCsrBaseAddress = Family::GPGPU_CSR_BASE_ADDRESS::sInit();
+const Family::STATE_SIP Family::cmdInitStateSip = Family::STATE_SIP::sInit();
+const Family::BINDING_TABLE_STATE Family::cmdInitBindingTableState = Family::BINDING_TABLE_STATE::sInit();
+const Family::MI_USER_INTERRUPT Family::cmdInitUserInterrupt = Family::MI_USER_INTERRUPT::sInit();
 } // namespace OCLRT
--- a/runtime/gen10/hw_cmds.h
+++ b/runtime/gen10/hw_cmds.h
@@ -35,7 +35,25 @@ struct CNLFamily : public GEN10 {
    static const MI_BATCH_BUFFER_START cmdInitBatchBufferStart;
    static const PIPE_CONTROL cmdInitPipeControl;
    static const MI_SEMAPHORE_WAIT cmdInitMiSemaphoreWait;
-    static const RENDER_SURFACE_STATE cmdRenderSurfaceState;
+    static const RENDER_SURFACE_STATE cmdInitRenderSurfaceState;
+    static const MI_LOAD_REGISTER_IMM cmdInitLoadRegisterImm;
+    static const MI_LOAD_REGISTER_REG cmdInitLoadRegisterReg;
+    static const MI_LOAD_REGISTER_MEM cmdInitLoadRegisterMem;
+    static const MI_STORE_DATA_IMM cmdInitStoreDataImm;
+    static const MI_STORE_REGISTER_MEM cmdInitStoreRegisterMem;
+    static const MI_NOOP cmdInitNoop;
+    static const MI_REPORT_PERF_COUNT cmdInitReportPerfCount;
+    static const MI_ATOMIC cmdInitAtomic;
+    static const PIPELINE_SELECT cmdInitPipelineSelect;
+    static const MI_ARB_CHECK cmdInitArbCheck;
+    static const MEDIA_VFE_STATE cmdInitMediaVfeState;
+    static const STATE_BASE_ADDRESS cmdInitStateBaseAddress;
+    static const MEDIA_SURFACE_STATE cmdInitMediaSurfaceState;
+    static const SAMPLER_STATE cmdInitSamplerState;
+    static const GPGPU_CSR_BASE_ADDRESS cmdInitGpgpuCsrBaseAddress;
+    static const STATE_SIP cmdInitStateSip;
+    static const BINDING_TABLE_STATE cmdInitBindingTableState;
+    static const MI_USER_INTERRUPT cmdInitUserInterrupt;

    static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
        return cmdSetBaseFamily == IGFX_GEN8_CORE;
--- a/runtime/gen8/command_stream_receiver_hw_gen8.cpp
+++ b/runtime/gen8/command_stream_receiver_hw_gen8.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Intel Corporation
+ * Copyright (C) 2018-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -59,5 +59,23 @@ const Family::MI_BATCH_BUFFER_START Family::cmdInitBatchBufferStart = Family::MI
 const Family::MI_BATCH_BUFFER_END Family::cmdInitBatchBufferEnd = Family::MI_BATCH_BUFFER_END::sInit();
 const Family::PIPE_CONTROL Family::cmdInitPipeControl = Family::PIPE_CONTROL::sInit();
 const Family::MI_SEMAPHORE_WAIT Family::cmdInitMiSemaphoreWait = Family::MI_SEMAPHORE_WAIT::sInit();
-const Family::RENDER_SURFACE_STATE Family::cmdRenderSurfaceState = Family::RENDER_SURFACE_STATE::sInit();
+const Family::RENDER_SURFACE_STATE Family::cmdInitRenderSurfaceState = Family::RENDER_SURFACE_STATE::sInit();
+const Family::MI_LOAD_REGISTER_IMM Family::cmdInitLoadRegisterImm = Family::MI_LOAD_REGISTER_IMM::sInit();
+const Family::MI_LOAD_REGISTER_REG Family::cmdInitLoadRegisterReg = Family::MI_LOAD_REGISTER_REG::sInit();
+const Family::MI_LOAD_REGISTER_MEM Family::cmdInitLoadRegisterMem = Family::MI_LOAD_REGISTER_MEM::sInit();
+const Family::MI_STORE_DATA_IMM Family::cmdInitStoreDataImm = Family::MI_STORE_DATA_IMM::sInit();
+const Family::MI_STORE_REGISTER_MEM Family::cmdInitStoreRegisterMem = Family::MI_STORE_REGISTER_MEM::sInit();
+const Family::MI_NOOP Family::cmdInitNoop = Family::MI_NOOP::sInit();
+const Family::MI_REPORT_PERF_COUNT Family::cmdInitReportPerfCount = Family::MI_REPORT_PERF_COUNT::sInit();
+const Family::MI_ATOMIC Family::cmdInitAtomic = Family::MI_ATOMIC::sInit();
+const Family::PIPELINE_SELECT Family::cmdInitPipelineSelect = Family::PIPELINE_SELECT::sInit();
+const Family::MI_ARB_CHECK Family::cmdInitArbCheck = Family::MI_ARB_CHECK::sInit();
+const Family::MEDIA_VFE_STATE Family::cmdInitMediaVfeState = Family::MEDIA_VFE_STATE::sInit();
+const Family::STATE_BASE_ADDRESS Family::cmdInitStateBaseAddress = Family::STATE_BASE_ADDRESS::sInit();
+const Family::MEDIA_SURFACE_STATE Family::cmdInitMediaSurfaceState = Family::MEDIA_SURFACE_STATE::sInit();
+const Family::SAMPLER_STATE Family::cmdInitSamplerState = Family::SAMPLER_STATE::sInit();
+const Family::GPGPU_CSR_BASE_ADDRESS Family::cmdInitGpgpuCsrBaseAddress = Family::GPGPU_CSR_BASE_ADDRESS::sInit();
+const Family::STATE_SIP Family::cmdInitStateSip = Family::STATE_SIP::sInit();
+const Family::BINDING_TABLE_STATE Family::cmdInitBindingTableState = Family::BINDING_TABLE_STATE::sInit();
+const Family::MI_USER_INTERRUPT Family::cmdInitUserInterrupt = Family::MI_USER_INTERRUPT::sInit();
 } // namespace OCLRT
--- a/runtime/gen8/device_queue_gen8.cpp
+++ b/runtime/gen8/device_queue_gen8.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2018 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -33,7 +33,7 @@ void DeviceQueueHw<Family>::addArbCheckCmdWa() {}
 template <>
 void DeviceQueueHw<Family>::addMiAtomicCmdWa(uint64_t atomicOpPlaceholder) {
    auto miAtomic = slbCS.getSpaceForCmd<Family::MI_ATOMIC>();
-    *miAtomic = Family::MI_ATOMIC::sInit();
+    *miAtomic = Family::cmdInitAtomic;
    miAtomic->setAtomicOpcode(Family::MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_8B_INCREMENT);
    miAtomic->setReturnDataControl(0x1);
    miAtomic->setCsStall(0x1);
@@ -45,7 +45,7 @@ void DeviceQueueHw<Family>::addMiAtomicCmdWa(uint64_t atomicOpPlaceholder) {
 template <>
 void DeviceQueueHw<Family>::addLriCmdWa(bool setArbCheck) {
    auto lri = slbCS.getSpaceForCmd<Family::MI_LOAD_REGISTER_IMM>();
-    *lri = Family::MI_LOAD_REGISTER_IMM::sInit();
+    *lri = Family::cmdInitLoadRegisterImm;
    lri->setRegisterOffset(0x2248); // CTXT_PREMP_DBG offset
    if (setArbCheck)
        lri->setDataDword(0x00000100); // set only bit 8 (Preempt On MI_ARB_CHK Only)
@@ -59,7 +59,7 @@ void DeviceQueueHw<Family>::addPipeControlCmdWa(bool isNoopCmd) {}
 template <>
 void DeviceQueueHw<Family>::addProfilingEndCmds(uint64_t timestampAddress) {
    auto pPipeControlCmd = (PIPE_CONTROL *)slbCS.getSpace(sizeof(PIPE_CONTROL));
-    *pPipeControlCmd = PIPE_CONTROL::sInit();
+    *pPipeControlCmd = Family::cmdInitPipeControl;
    pPipeControlCmd->setCommandStreamerStallEnable(true);
    pPipeControlCmd->setPostSyncOperation(PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP);
    pPipeControlCmd->setAddressHigh(timestampAddress >> 32);
--- a/runtime/gen8/gpgpu_walker_gen8.cpp
+++ b/runtime/gen8/gpgpu_walker_gen8.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Intel Corporation
+ * Copyright (C) 2018-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -27,7 +27,7 @@ void GpgpuWalkerHelper<BDWFamily>::applyWADisableLSQCROPERFforOCL(OCLRT::LinearS
            // Add PIPE_CONTROL with CS_Stall to wait till GPU finishes its work
            typedef typename BDWFamily::PIPE_CONTROL PIPE_CONTROL;
            auto pCmd = reinterpret_cast<PIPE_CONTROL *>(pCommandStream->getSpace(sizeof(PIPE_CONTROL)));
-            *pCmd = PIPE_CONTROL::sInit();
+            *pCmd = BDWFamily::cmdInitPipeControl;
            pCmd->setCommandStreamerStallEnable(true);
            // Clear bit L3SQC_BIT_LQSC_RO_PERF_DIS in L3SQC_REG4
            GpgpuWalkerHelper<BDWFamily>::addAluReadModifyWriteRegister(pCommandStream, L3SQC_REG4, ALU_OPCODE_AND, ~L3SQC_BIT_LQSC_RO_PERF_DIS);
--- a/runtime/gen8/hw_cmds_base.h
+++ b/runtime/gen8/hw_cmds_base.h
@@ -34,7 +34,25 @@ struct BDWFamily : public GEN8 {
    static const MI_BATCH_BUFFER_START cmdInitBatchBufferStart;
    static const PIPE_CONTROL cmdInitPipeControl;
    static const MI_SEMAPHORE_WAIT cmdInitMiSemaphoreWait;
-    static const RENDER_SURFACE_STATE cmdRenderSurfaceState;
+    static const RENDER_SURFACE_STATE cmdInitRenderSurfaceState;
+    static const MI_LOAD_REGISTER_IMM cmdInitLoadRegisterImm;
+    static const MI_LOAD_REGISTER_REG cmdInitLoadRegisterReg;
+    static const MI_LOAD_REGISTER_MEM cmdInitLoadRegisterMem;
+    static const MI_STORE_DATA_IMM cmdInitStoreDataImm;
+    static const MI_STORE_REGISTER_MEM cmdInitStoreRegisterMem;
+    static const MI_NOOP cmdInitNoop;
+    static const MI_REPORT_PERF_COUNT cmdInitReportPerfCount;
+    static const MI_ATOMIC cmdInitAtomic;
+    static const PIPELINE_SELECT cmdInitPipelineSelect;
+    static const MI_ARB_CHECK cmdInitArbCheck;
+    static const MEDIA_VFE_STATE cmdInitMediaVfeState;
+    static const STATE_BASE_ADDRESS cmdInitStateBaseAddress;
+    static const MEDIA_SURFACE_STATE cmdInitMediaSurfaceState;
+    static const SAMPLER_STATE cmdInitSamplerState;
+    static const GPGPU_CSR_BASE_ADDRESS cmdInitGpgpuCsrBaseAddress;
+    static const STATE_SIP cmdInitStateSip;
+    static const BINDING_TABLE_STATE cmdInitBindingTableState;
+    static const MI_USER_INTERRUPT cmdInitUserInterrupt;

    static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
        return cmdSetBaseFamily == IGFX_GEN8_CORE;
--- a/runtime/gen8/preamble_gen8.cpp
+++ b/runtime/gen8/preamble_gen8.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Intel Corporation
+ * Copyright (C) 2018-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -12,7 +12,7 @@ namespace OCLRT {
 template <>
 void PreambleHelper<BDWFamily>::addPipeControlBeforeVfeCmd(LinearStream *pCommandStream, const HardwareInfo *hwInfo) {
    auto pipeControl = pCommandStream->getSpaceForCmd<PIPE_CONTROL>();
-    *pipeControl = PIPE_CONTROL::sInit();
+    *pipeControl = BDWFamily::cmdInitPipeControl;
    pipeControl->setCommandStreamerStallEnable(true);
    pipeControl->setDcFlushEnable(true);
 }
@@ -35,7 +35,7 @@ template <>
 void PreambleHelper<BDWFamily>::programPipelineSelect(LinearStream *pCommandStream, const DispatchFlags &dispatchFlags) {
    typedef typename BDWFamily::PIPELINE_SELECT PIPELINE_SELECT;
    auto pCmd = (PIPELINE_SELECT *)pCommandStream->getSpace(sizeof(PIPELINE_SELECT));
-    *pCmd = PIPELINE_SELECT::sInit();
+    *pCmd = BDWFamily::cmdInitPipelineSelect;
    pCmd->setMaskBits(pipelineSelectEnablePipelineSelectMaskBits);
    pCmd->setPipelineSelection(PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU);
 }
--- a/runtime/gen9/command_stream_receiver_hw_gen9.cpp
+++ b/runtime/gen9/command_stream_receiver_hw_gen9.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Intel Corporation
+ * Copyright (C) 2018-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -58,5 +58,23 @@ const Family::MI_BATCH_BUFFER_START Family::cmdInitBatchBufferStart = Family::MI
 const Family::MI_BATCH_BUFFER_END Family::cmdInitBatchBufferEnd = Family::MI_BATCH_BUFFER_END::sInit();
 const Family::PIPE_CONTROL Family::cmdInitPipeControl = Family::PIPE_CONTROL::sInit();
 const Family::MI_SEMAPHORE_WAIT Family::cmdInitMiSemaphoreWait = Family::MI_SEMAPHORE_WAIT::sInit();
-const Family::RENDER_SURFACE_STATE Family::cmdRenderSurfaceState = Family::RENDER_SURFACE_STATE::sInit();
+const Family::RENDER_SURFACE_STATE Family::cmdInitRenderSurfaceState = Family::RENDER_SURFACE_STATE::sInit();
+const Family::MI_LOAD_REGISTER_IMM Family::cmdInitLoadRegisterImm = Family::MI_LOAD_REGISTER_IMM::sInit();
+const Family::MI_LOAD_REGISTER_REG Family::cmdInitLoadRegisterReg = Family::MI_LOAD_REGISTER_REG::sInit();
+const Family::MI_LOAD_REGISTER_MEM Family::cmdInitLoadRegisterMem = Family::MI_LOAD_REGISTER_MEM::sInit();
+const Family::MI_STORE_DATA_IMM Family::cmdInitStoreDataImm = Family::MI_STORE_DATA_IMM::sInit();
+const Family::MI_STORE_REGISTER_MEM Family::cmdInitStoreRegisterMem = Family::MI_STORE_REGISTER_MEM::sInit();
+const Family::MI_NOOP Family::cmdInitNoop = Family::MI_NOOP::sInit();
+const Family::MI_REPORT_PERF_COUNT Family::cmdInitReportPerfCount = Family::MI_REPORT_PERF_COUNT::sInit();
+const Family::MI_ATOMIC Family::cmdInitAtomic = Family::MI_ATOMIC::sInit();
+const Family::PIPELINE_SELECT Family::cmdInitPipelineSelect = Family::PIPELINE_SELECT::sInit();
+const Family::MI_ARB_CHECK Family::cmdInitArbCheck = Family::MI_ARB_CHECK::sInit();
+const Family::MEDIA_VFE_STATE Family::cmdInitMediaVfeState = Family::MEDIA_VFE_STATE::sInit();
+const Family::STATE_BASE_ADDRESS Family::cmdInitStateBaseAddress = Family::STATE_BASE_ADDRESS::sInit();
+const Family::MEDIA_SURFACE_STATE Family::cmdInitMediaSurfaceState = Family::MEDIA_SURFACE_STATE::sInit();
+const Family::SAMPLER_STATE Family::cmdInitSamplerState = Family::SAMPLER_STATE::sInit();
+const Family::GPGPU_CSR_BASE_ADDRESS Family::cmdInitGpgpuCsrBaseAddress = Family::GPGPU_CSR_BASE_ADDRESS::sInit();
+const Family::STATE_SIP Family::cmdInitStateSip = Family::STATE_SIP::sInit();
+const Family::BINDING_TABLE_STATE Family::cmdInitBindingTableState = Family::BINDING_TABLE_STATE::sInit();
+const Family::MI_USER_INTERRUPT Family::cmdInitUserInterrupt = Family::MI_USER_INTERRUPT::sInit();
 } // namespace OCLRT
--- a/runtime/gen9/device_queue_gen9.cpp
+++ b/runtime/gen9/device_queue_gen9.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2018 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -33,13 +33,13 @@ size_t DeviceQueueHw<Family>::getWaCommandsSize() {
 template <>
 void DeviceQueueHw<Family>::addArbCheckCmdWa() {
    auto arbCheck = slbCS.getSpaceForCmd<Family::MI_ARB_CHECK>();
-    *arbCheck = Family::MI_ARB_CHECK::sInit();
+    *arbCheck = Family::cmdInitArbCheck;
 }

 template <>
 void DeviceQueueHw<Family>::addMiAtomicCmdWa(uint64_t atomicOpPlaceholder) {
    auto miAtomic = slbCS.getSpaceForCmd<Family::MI_ATOMIC>();
-    *miAtomic = Family::MI_ATOMIC::sInit();
+    *miAtomic = Family::cmdInitAtomic;
    miAtomic->setAtomicOpcode(Family::MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_8B_INCREMENT);
    miAtomic->setReturnDataControl(0x1);
    miAtomic->setCsStall(0x1);
--- a/runtime/gen9/gpgpu_walker_gen9.cpp
+++ b/runtime/gen9/gpgpu_walker_gen9.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Intel Corporation
+ * Copyright (C) 2018-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -27,7 +27,7 @@ void GpgpuWalkerHelper<SKLFamily>::applyWADisableLSQCROPERFforOCL(OCLRT::LinearS
            // Add PIPE_CONTROL with CS_Stall to wait till GPU finishes its work
            typedef typename SKLFamily::PIPE_CONTROL PIPE_CONTROL;
            auto pCmd = reinterpret_cast<PIPE_CONTROL *>(pCommandStream->getSpace(sizeof(PIPE_CONTROL)));
-            *pCmd = PIPE_CONTROL::sInit();
+            *pCmd = SKLFamily::cmdInitPipeControl;
            pCmd->setCommandStreamerStallEnable(true);
            // Clear bit L3SQC_BIT_LQSC_RO_PERF_DIS in L3SQC_REG4
            GpgpuWalkerHelper<SKLFamily>::addAluReadModifyWriteRegister(pCommandStream, L3SQC_REG4, ALU_OPCODE_AND, ~L3SQC_BIT_LQSC_RO_PERF_DIS);
--- a/runtime/gen9/hw_cmds_base.h
+++ b/runtime/gen9/hw_cmds_base.h
@@ -35,7 +35,25 @@ struct SKLFamily : public GEN9 {
    static const MI_BATCH_BUFFER_START cmdInitBatchBufferStart;
    static const PIPE_CONTROL cmdInitPipeControl;
    static const MI_SEMAPHORE_WAIT cmdInitMiSemaphoreWait;
-    static const RENDER_SURFACE_STATE cmdRenderSurfaceState;
+    static const RENDER_SURFACE_STATE cmdInitRenderSurfaceState;
+    static const MI_LOAD_REGISTER_IMM cmdInitLoadRegisterImm;
+    static const MI_LOAD_REGISTER_REG cmdInitLoadRegisterReg;
+    static const MI_LOAD_REGISTER_MEM cmdInitLoadRegisterMem;
+    static const MI_STORE_DATA_IMM cmdInitStoreDataImm;
+    static const MI_STORE_REGISTER_MEM cmdInitStoreRegisterMem;
+    static const MI_NOOP cmdInitNoop;
+    static const MI_REPORT_PERF_COUNT cmdInitReportPerfCount;
+    static const MI_ATOMIC cmdInitAtomic;
+    static const PIPELINE_SELECT cmdInitPipelineSelect;
+    static const MI_ARB_CHECK cmdInitArbCheck;
+    static const MEDIA_VFE_STATE cmdInitMediaVfeState;
+    static const STATE_BASE_ADDRESS cmdInitStateBaseAddress;
+    static const MEDIA_SURFACE_STATE cmdInitMediaSurfaceState;
+    static const SAMPLER_STATE cmdInitSamplerState;
+    static const GPGPU_CSR_BASE_ADDRESS cmdInitGpgpuCsrBaseAddress;
+    static const STATE_SIP cmdInitStateSip;
+    static const BINDING_TABLE_STATE cmdInitBindingTableState;
+    static const MI_USER_INTERRUPT cmdInitUserInterrupt;

    static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
        return cmdSetBaseFamily == IGFX_GEN8_CORE;
--- a/runtime/gen9/preamble_gen9.cpp
+++ b/runtime/gen9/preamble_gen9.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2018 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -32,7 +32,7 @@ void PreambleHelper<SKLFamily>::programPipelineSelect(LinearStream *pCommandStre
    typedef typename SKLFamily::PIPELINE_SELECT PIPELINE_SELECT;

    auto pCmd = (PIPELINE_SELECT *)pCommandStream->getSpace(sizeof(PIPELINE_SELECT));
-    *pCmd = PIPELINE_SELECT::sInit();
+    *pCmd = SKLFamily::cmdInitPipelineSelect;

    auto mask = pipelineSelectEnablePipelineSelectMaskBits | pipelineSelectMediaSamplerDopClockGateMaskBits;
    pCmd->setMaskBits(mask);
@@ -43,7 +43,7 @@ void PreambleHelper<SKLFamily>::programPipelineSelect(LinearStream *pCommandStre
 template <>
 void PreambleHelper<SKLFamily>::addPipeControlBeforeVfeCmd(LinearStream *pCommandStream, const HardwareInfo *hwInfo) {
    auto pipeControl = pCommandStream->getSpaceForCmd<PIPE_CONTROL>();
-    *pipeControl = PIPE_CONTROL::sInit();
+    *pipeControl = SKLFamily::cmdInitPipeControl;
    pipeControl->setCommandStreamerStallEnable(true);
    if (hwInfo->pWaTable->waSendMIFLUSHBeforeVFE) {
        pipeControl->setRenderTargetCacheFlushEnable(true);
@@ -62,11 +62,11 @@ void PreambleHelper<SKLFamily>::programThreadArbitration(LinearStream *pCommandS
    UNRECOVERABLE_IF(requiredThreadArbitrationPolicy == ThreadArbitrationPolicy::NotPresent);

    auto pipeControl = pCommandStream->getSpaceForCmd<PIPE_CONTROL>();
-    *pipeControl = PIPE_CONTROL::sInit();
+    *pipeControl = SKLFamily::cmdInitPipeControl;
    pipeControl->setCommandStreamerStallEnable(true);

    auto pCmd = pCommandStream->getSpaceForCmd<MI_LOAD_REGISTER_IMM>();
-    *pCmd = MI_LOAD_REGISTER_IMM::sInit();
+    *pCmd = SKLFamily::cmdInitLoadRegisterImm;

    pCmd->setRegisterOffset(DebugControlReg2::address);
    pCmd->setDataDword(DebugControlReg2::getRegData(requiredThreadArbitrationPolicy));
--- a/runtime/gtpin/gtpin_hw_helper.inl
+++ b/runtime/gtpin/gtpin_hw_helper.inl
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Intel Corporation
+ * Copyright (C) 2018-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -31,15 +31,13 @@ bool GTPinHwHelperHw<GfxFamily>::addSurfaceState(Kernel *pKernel) {
    char *pNewSsh = new char[sshSize + sizeToEnlarge];
    memcpy_s(pNewSsh, sshSize + sizeToEnlarge, pSsh, currSurfaceStateSize);
    RENDER_SURFACE_STATE *pSS = reinterpret_cast<RENDER_SURFACE_STATE *>(pNewSsh + currSurfaceStateSize);
-    pSS->init();
+    *pSS = GfxFamily::cmdInitRenderSurfaceState;
    size_t newSurfaceStateSize = currSurfaceStateSize + ssSize;
    size_t currBTCount = pKernel->getNumberOfBindingTableStates();
    memcpy_s(pNewSsh + newSurfaceStateSize, sshSize + sizeToEnlarge - newSurfaceStateSize, pSsh + currBTOffset, currBTCount * btsSize);
    BINDING_TABLE_STATE *pNewBTS = reinterpret_cast<BINDING_TABLE_STATE *>(pNewSsh + newSurfaceStateSize + currBTCount * btsSize);
-    BINDING_TABLE_STATE bti;
-    bti.init();
-    bti.setSurfaceStatePointer((uint64_t)currBTOffset);
-    *pNewBTS = bti;
+    *pNewBTS = GfxFamily::cmdInitBindingTableState;
+    pNewBTS->setSurfaceStatePointer((uint64_t)currBTOffset);
    pKernel->resizeSurfaceStateHeap(pNewSsh, sshSize + sizeToEnlarge, currBTCount + 1, newSurfaceStateSize);
    return true;
 }
--- a/runtime/helpers/flat_batch_buffer_helper_hw.inl
+++ b/runtime/helpers/flat_batch_buffer_helper_hw.inl
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Intel Corporation
+ * Copyright (C) 2018-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -127,7 +127,7 @@ GraphicsAllocation *FlatBatchBufferHelperHw<GfxFamily>::flattenBatchBuffer(Batch
        }

        auto pCmdMui = reinterpret_cast<MI_USER_INTERRUPT *>(ptr);
-        pCmdMui->init();
+        *pCmdMui = GfxFamily::cmdInitUserInterrupt;
        ptr += sizeof(MI_USER_INTERRUPT);

        auto pCmdBBend = reinterpret_cast<MI_BATCH_BUFFER_END *>(ptr);
@@ -162,7 +162,7 @@ char *FlatBatchBufferHelperHw<GfxFamily>::getIndirectPatchCommands(size_t &indir
    for (auto &patchInfoData : patchInfoCopy) {
        if (patchInfoData.requiresIndirectPatching()) {
            auto storeDataImmediate = indirectPatchCommandStream.getSpaceForCmd<MI_STORE_DATA_IMM>();
-            storeDataImmediate->init();
+            *storeDataImmediate = GfxFamily::cmdInitStoreDataImm;
            storeDataImmediate->setAddress(patchInfoData.targetAllocation + patchInfoData.targetAllocationOffset);
            storeDataImmediate->setStoreQword(patchInfoData.patchAddressSize != sizeof(uint32_t));
            storeDataImmediate->setDataDword0(static_cast<uint32_t>((patchInfoData.sourceAllocation + patchInfoData.sourceAllocationOffset) & 0x0000FFFFFFFFULL));
--- a/runtime/helpers/hw_helper.h
+++ b/runtime/helpers/hw_helper.h
@@ -159,7 +159,7 @@ struct LriHelper {

    static MI_LOAD_REGISTER_IMM *program(LinearStream *cmdStream, uint32_t address, uint32_t value) {
        auto lri = (MI_LOAD_REGISTER_IMM *)cmdStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM));
-        *lri = MI_LOAD_REGISTER_IMM::sInit();
+        *lri = GfxFamily::cmdInitLoadRegisterImm;
        lri->setRegisterOffset(address);
        lri->setDataDword(value);
        return lri;
--- a/runtime/helpers/hw_helper_common.inl
+++ b/runtime/helpers/hw_helper_common.inl
@@ -108,7 +108,7 @@ void HwHelperHw<Family>::setRenderSurfaceStateForBuffer(ExecutionEnvironment &ex

    auto gmmHelper = executionEnvironment.getGmmHelper();
    auto surfaceState = reinterpret_cast<RENDER_SURFACE_STATE *>(surfaceStateBuffer);
-    *surfaceState = Family::cmdRenderSurfaceState;
+    *surfaceState = Family::cmdInitRenderSurfaceState;
    auto surfaceSize = alignUp(bufferSize, 4);

    SURFACE_STATE_BUFFER_LENGTH Length = {0};
--- a/runtime/helpers/kernel_commands.inl
+++ b/runtime/helpers/kernel_commands.inl
@@ -203,8 +203,7 @@ size_t KernelCommandsHelper<GfxFamily>::pushBindingTableAndSurfaceStates(Indirec
    auto *dstBtiTableBase = reinterpret_cast<BINDING_TABLE_STATE *>(ptrOffset(dstSurfaceState, offsetOfBindingTable));
    DEBUG_BREAK_IF(reinterpret_cast<uintptr_t>(dstBtiTableBase) % INTERFACE_DESCRIPTOR_DATA::BINDINGTABLEPOINTER_ALIGN_SIZE != 0);
    auto *srcBtiTableBase = reinterpret_cast<const BINDING_TABLE_STATE *>(ptrOffset(srcSurfaceState, offsetOfBindingTable));
-    BINDING_TABLE_STATE bti;
-    bti.init(); // init whole DWORD - i.e. not just the SurfaceStatePointer bits
+    BINDING_TABLE_STATE bti = GfxFamily::cmdInitBindingTableState;
    for (uint32_t i = 0, e = (uint32_t)numberOfBindingTableStates; i != e; ++i) {
        uint32_t localSurfaceStateOffset = srcBtiTableBase[i].getSurfaceStatePointer();
        uint32_t offsetedSurfaceStateOffset = localSurfaceStateOffset + surfaceStatesOffset;
@@ -389,7 +388,7 @@ typename GfxFamily::MI_ATOMIC *KernelCommandsHelper<GfxFamily>::programMiAtomic(
                                                                                typename MI_ATOMIC::ATOMIC_OPCODES opcode,
                                                                                typename MI_ATOMIC::DATA_SIZE dataSize) {
    auto miAtomic = commandStream.getSpaceForCmd<MI_ATOMIC>();
-    *miAtomic = MI_ATOMIC::sInit();
+    *miAtomic = GfxFamily::cmdInitAtomic;
    miAtomic->setAtomicOpcode(opcode);
    miAtomic->setDataSize(dataSize);
    miAtomic->setMemoryAddress(static_cast<uint32_t>(writeAddress & 0x0000FFFFFFFFULL));
--- a/runtime/helpers/preamble.inl
+++ b/runtime/helpers/preamble.inl
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 Intel Corporation
+ * Copyright (C) 2018-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -49,7 +49,7 @@ void PreambleHelper<GfxFamily>::programVFEState(LinearStream *pCommandStream, co
    addPipeControlBeforeVfeCmd(pCommandStream, &hwInfo);

    auto pMediaVfeState = (MEDIA_VFE_STATE *)pCommandStream->getSpace(sizeof(MEDIA_VFE_STATE));
-    *pMediaVfeState = MEDIA_VFE_STATE::sInit();
+    *pMediaVfeState = GfxFamily::cmdInitMediaVfeState;
    pMediaVfeState->setMaximumNumberOfThreads(PreambleHelper<GfxFamily>::getMaxThreadsForVfe(hwInfo));
    pMediaVfeState->setNumberOfUrbEntries(1);
    pMediaVfeState->setUrbEntryAllocationSize(PreambleHelper<GfxFamily>::getUrbEntryAllocationSize());
@@ -64,7 +64,7 @@ void PreambleHelper<GfxFamily>::programVFEState(LinearStream *pCommandStream, co
 template <typename GfxFamily>
 void PreambleHelper<GfxFamily>::programL3(LinearStream *pCommandStream, uint32_t l3Config) {
    auto pCmd = (MI_LOAD_REGISTER_IMM *)pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM));
-    *pCmd = MI_LOAD_REGISTER_IMM::sInit();
+    *pCmd = GfxFamily::cmdInitLoadRegisterImm;

    pCmd->setRegisterOffset(L3CNTLRegisterOffset<GfxFamily>::registerOffset);
    pCmd->setDataDword(l3Config);
@@ -95,12 +95,12 @@ uint32_t PreambleHelper<GfxFamily>::getUrbEntryAllocationSize() {
 template <typename GfxFamily>
 void PreambleHelper<GfxFamily>::programKernelDebugging(LinearStream *pCommandStream) {
    auto pCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM)));
-    *pCmd = MI_LOAD_REGISTER_IMM::sInit();
+    *pCmd = GfxFamily::cmdInitLoadRegisterImm;
    pCmd->setRegisterOffset(DebugModeRegisterOffset::registerOffset);
    pCmd->setDataDword(DebugModeRegisterOffset::debugEnabledValue);

    auto pCmd2 = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(pCommandStream->getSpace(sizeof(MI_LOAD_REGISTER_IMM)));
-    *pCmd2 = MI_LOAD_REGISTER_IMM::sInit();
+    *pCmd2 = GfxFamily::cmdInitLoadRegisterImm;
    pCmd2->setRegisterOffset(TdDebugControlRegisterOffset::registerOffset);
    pCmd2->setDataDword(TdDebugControlRegisterOffset::debugEnabledValue);
 }
--- a/runtime/helpers/state_base_address.inl
+++ b/runtime/helpers/state_base_address.inl
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2018 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -25,7 +25,7 @@ void StateBaseAddressHelper<GfxFamily>::programStateBaseAddress(
    GmmHelper *gmmHelper) {

    auto pCmd = static_cast<STATE_BASE_ADDRESS *>(commandStream.getSpace(sizeof(STATE_BASE_ADDRESS)));
-    *pCmd = STATE_BASE_ADDRESS::sInit();
+    *pCmd = GfxFamily::cmdInitStateBaseAddress;

    pCmd->setDynamicStateBaseAddressModifyEnable(true);
    pCmd->setGeneralStateBaseAddressModifyEnable(true);
--- a/runtime/mem_obj/image.inl
+++ b/runtime/mem_obj/image.inl
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2018 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
 *
 * SPDX-License-Identifier: MIT
 *
@@ -207,7 +207,7 @@ void ImageHw<GfxFamily>::setMediaImageArg(void *memory) {

    auto gmmHelper = executionEnvironment->getGmmHelper();
    auto surfaceState = reinterpret_cast<MEDIA_SURFACE_STATE *>(memory);
-    *surfaceState = MEDIA_SURFACE_STATE::sInit();
+    *surfaceState = GfxFamily::cmdInitMediaSurfaceState;

    setMediaSurfaceRotation(reinterpret_cast<void *>(surfaceState));