Opensource adln

Related-To: NEO-6818
Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>
This commit is contained in:
Naklicki, Mateusz
2022-06-02 15:12:55 +00:00
committed by Compute-Runtime-Automation
parent adfc3a1e7a
commit 1b7555a49d
39 changed files with 850 additions and 5 deletions

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@@ -0,0 +1,29 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
template <>
uint32_t HwInfoConfigHw<gfxProduct>::getHwRevIdFromStepping(uint32_t stepping, const HardwareInfo &hwInfo) const {
switch (stepping) {
case REVISION_A0:
return 0x0;
}
return CommonConstants::invalidStepping;
}
template <>
PRODUCT_CONFIG HwInfoConfigHw<gfxProduct>::getProductConfigFromHwInfo(const HardwareInfo &hwInfo) const {
return PRODUCT_CONFIG::ADL_N;
}
template <>
uint32_t HwInfoConfigHw<gfxProduct>::getSteppingFromHwRevId(const HardwareInfo &hwInfo) const {
switch (hwInfo.platform.usRevId) {
case 0x0:
return REVISION_A0;
}
return CommonConstants::invalidStepping;
}

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@@ -0,0 +1,6 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/

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@@ -0,0 +1,15 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
const uint64_t ADLN::defaultHardwareInfoConfig = 0x0;
const HardwareInfo ADLN::hwInfo = ADLN_CONFIG::hwInfo;
void setupADLNHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig) {
ADLN_CONFIG::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
}
void (*ADLN::setupHardwareInfo)(HardwareInfo *, bool, const uint64_t) = setupADLNHardwareInfoImpl;

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@@ -35,4 +35,8 @@ static EnableCompilerHwInfoConfig<IGFX_ALDERLAKE_S> enableCompilerHwInfoConfigAD
static EnableGfxProductHw<IGFX_ALDERLAKE_P> enableGfxProductHwADLP;
static EnableCompilerHwInfoConfig<IGFX_ALDERLAKE_P> enableCompilerHwInfoConfigADLP;
#endif
#ifdef SUPPORT_ADLN
static EnableGfxProductHw<IGFX_ALDERLAKE_N> enableGfxProductHwADLN;
static EnableCompilerHwInfoConfig<IGFX_ALDERLAKE_N> enableCompilerHwInfoConfigADLN;
#endif
} // namespace NEO

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@@ -0,0 +1,15 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/gen12lp/hw_cmds.h"
#include "shared/source/os_interface/hw_info_config.h"
namespace NEO {
static EnableProductHwInfoConfig<IGFX_ALDERLAKE_N> enableADLN;
} // namespace NEO

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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Intel Corporation
* Copyright (C) 2019-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -22,3 +22,6 @@
#ifdef SUPPORT_ADLP
#include "hw_cmds_adlp.h"
#endif
#ifdef SUPPORT_ADLN
#include "hw_cmds_adln.h"
#endif

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@@ -0,0 +1,38 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "shared/source/gen12lp/hw_cmds_base.h"
namespace NEO {
struct ADLN : public TGLLPFamily {
static const PLATFORM platform;
static const HardwareInfo hwInfo;
static const uint64_t defaultHardwareInfoConfig;
static FeatureTable featureTable;
static WorkaroundTable workaroundTable;
static const uint32_t threadsPerEu = 7;
static const uint32_t maxEuPerSubslice = 16;
static const uint32_t maxSlicesSupported = 1;
static const uint32_t maxSubslicesSupported = 6;
static const uint32_t maxDualSubslicesSupported = 12;
static const RuntimeCapabilityTable capabilityTable;
static void (*setupHardwareInfo)(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig);
static void setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo);
static void setupHardwareInfoBase(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable);
};
class ADLN_CONFIG : public ADLN {
public:
static void setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable);
static const HardwareInfo hwInfo;
private:
static GT_SYSTEM_INFO gtSystemInfo;
};
#include "hw_cmds_adln.inl"
} // namespace NEO

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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Intel Corporation
* Copyright (C) 2019-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -20,4 +20,7 @@
#endif
#ifdef SUPPORT_ADLP
#include "hw_info_adlp.h"
#endif
#ifdef SUPPORT_ADLN
#include "hw_info_adln.h"
#endif

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@@ -0,0 +1,162 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/aub_mem_dump/definitions/aub_services.h"
#include "shared/source/gen12lp/hw_cmds.h"
#include "shared/source/helpers/constants.h"
#include "engine_node.h"
namespace NEO {
const char *HwMapper<IGFX_ALDERLAKE_N>::abbreviation = "adln";
bool isSimulationADLN(unsigned short deviceId) {
return false;
};
const PLATFORM ADLN::platform = {
IGFX_ALDERLAKE_N,
PCH_UNKNOWN,
IGFX_GEN12LP_CORE,
IGFX_GEN12LP_CORE,
PLATFORM_NONE, // default init
0, // usDeviceID
0, // usRevId. 0 sets the stepping to A0
0, // usDeviceID_PCH
0, // usRevId_PCH
GTTYPE_UNDEFINED};
const RuntimeCapabilityTable ADLN::capabilityTable{
EngineDirectSubmissionInitVec{
{aub_stream::ENGINE_RCS, {true, true}},
{aub_stream::ENGINE_CCS, {true, true}}}, // directSubmissionEngines
{0, 0, 0, 0, false, false, false, false}, // kmdNotifyProperties
MemoryConstants::max64BitAppAddress, // gpuAddressSpace
0, // sharedSystemMemCapabilities
83.333, // defaultProfilingTimerResolution
MemoryConstants::pageSize, // requiredPreemptionSurfaceSize
&isSimulationADLN, // isSimulation
"lp", // platformType
"", // deviceName
PreemptionMode::MidThread, // defaultPreemptionMode
aub_stream::ENGINE_RCS, // defaultEngineType
0, // maxRenderFrequency
30, // clVersionSupport
CmdServicesMemTraceVersion::DeviceValues::Adln, // aubDeviceId
1, // extraQuantityThreadsPerEU
64, // slmSize
sizeof(ADLN::GRF), // grfSize
36u, // timestampValidBits
32u, // kernelTimestampValidBits
false, // blitterOperationsSupported
true, // ftrSupportsInteger64BitAtomics
false, // ftrSupportsFP64
false, // ftrSupports64BitMath
true, // ftrSvm
false, // ftrSupportsCoherency
false, // ftrSupportsVmeAvcTextureSampler
false, // ftrSupportsVmeAvcPreemption
false, // ftrRenderCompressedBuffers
false, // ftrRenderCompressedImages
true, // instrumentationEnabled
true, // ftr64KBpages
true, // sourceLevelDebuggerSupported
false, // supportsVme
false, // supportCacheFlushAfterWalker
true, // supportsImages
false, // supportsDeviceEnqueue
false, // supportsPipes
true, // supportsOcl21Features
false, // supportsOnDemandPageFaults
false, // supportsIndependentForwardProgress
false, // hostPtrTrackingEnabled
true, // levelZeroSupported
true, // isIntegratedDevice
true, // supportsMediaBlock
false, // p2pAccessSupported
false, // p2pAtomicAccessSupported
true // fusedEuEnabled
};
WorkaroundTable ADLN::workaroundTable = {};
FeatureTable ADLN::featureTable = {};
void ADLN::setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo) {
FeatureTable *featureTable = &hwInfo->featureTable;
WorkaroundTable *workaroundTable = &hwInfo->workaroundTable;
featureTable->flags.ftrL3IACoherency = true;
featureTable->flags.ftrPPGTT = true;
featureTable->flags.ftrSVM = true;
featureTable->flags.ftrIA32eGfxPTEs = true;
featureTable->flags.ftrStandardMipTailFormat = true;
featureTable->flags.ftrTranslationTable = true;
featureTable->flags.ftrUserModeTranslationTable = true;
featureTable->flags.ftrTileMappedResource = true;
featureTable->flags.ftrEnableGuC = true;
featureTable->flags.ftrFbc = true;
featureTable->flags.ftrFbc2AddressTranslation = true;
featureTable->flags.ftrFbcBlitterTracking = true;
featureTable->flags.ftrFbcCpuTracking = true;
featureTable->flags.ftrTileY = true;
featureTable->flags.ftrAstcHdr2D = true;
featureTable->flags.ftrAstcLdr2D = true;
featureTable->flags.ftr3dMidBatchPreempt = true;
featureTable->flags.ftrGpGpuMidBatchPreempt = true;
featureTable->flags.ftrGpGpuThreadGroupLevelPreempt = true;
featureTable->flags.ftrPerCtxtPreemptionGranularityControl = true;
workaroundTable->flags.wa4kAlignUVOffsetNV12LinearSurface = true;
workaroundTable->flags.waEnablePreemptionGranularityControlByUMD = true;
workaroundTable->flags.waUntypedBufferCompression = true;
};
void ADLN::setupHardwareInfoBase(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
gtSysInfo->ThreadCount = gtSysInfo->EUCount * ADLN::threadsPerEu;
gtSysInfo->TotalPsThreadsWindowerRange = 64;
gtSysInfo->CsrSizeInMb = 8;
gtSysInfo->MaxEuPerSubSlice = ADLN::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = ADLN::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = ADLN::maxSubslicesSupported;
gtSysInfo->MaxDualSubSlicesSupported = ADLN::maxDualSubslicesSupported;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
if (setupFeatureTableAndWorkaroundTable) {
setupFeatureAndWorkaroundTable(hwInfo);
}
}
const HardwareInfo ADLN_CONFIG::hwInfo = {
&ADLN::platform,
&ADLN::featureTable,
&ADLN::workaroundTable,
&ADLN_CONFIG::gtSystemInfo,
ADLN::capabilityTable,
};
GT_SYSTEM_INFO ADLN_CONFIG::gtSystemInfo = {0};
void ADLN_CONFIG::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
ADLN::setupHardwareInfoBase(hwInfo, setupFeatureTableAndWorkaroundTable);
GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
gtSysInfo->L3CacheSizeInKb = 1920;
gtSysInfo->L3BankCount = 4;
gtSysInfo->MaxFillRate = 8;
gtSysInfo->CCSInfo.IsValid = true;
gtSysInfo->CCSInfo.NumberOfCCSEnabled = 1;
gtSysInfo->CCSInfo.Instances.CCSEnableMask = 0b1;
};
#include "hw_info_setup_adln.inl"
} // namespace NEO

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@@ -0,0 +1,23 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "shared/source/gen12lp/hw_info_gen12lp.h"
namespace NEO {
struct ADLN;
template <>
struct HwMapper<IGFX_ALDERLAKE_N> {
enum { gfxFamily = IGFX_GEN12LP_CORE };
static const char *abbreviation;
using GfxFamily = GfxFamilyMapper<static_cast<GFXCORE_FAMILY>(gfxFamily)>::GfxFamily;
using GfxProduct = ADLN;
};
} // namespace NEO

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@@ -0,0 +1,21 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/gen12lp/hw_cmds_base.h"
#include "shared/source/helpers/hw_info.h"
#include "shared/source/os_interface/hw_info_config.h"
#include "shared/source/os_interface/hw_info_config.inl"
#include "shared/source/os_interface/hw_info_config_bdw_and_later.inl"
namespace NEO {
constexpr static auto gfxProduct = IGFX_ALDERLAKE_N;
#include "shared/source/gen12lp/adln/os_agnostic_hw_info_config_adln.inl"
#include "shared/source/gen12lp/os_agnostic_hw_info_config_gen12lp.inl"
template class HwInfoConfigHw<gfxProduct>;
} // namespace NEO

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@@ -0,0 +1,21 @@
/*
* Copyright (C) 2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/gen12lp/hw_cmds_base.h"
#include "shared/source/helpers/hw_info.h"
#include "shared/source/os_interface/hw_info_config.h"
#include "shared/source/os_interface/hw_info_config.inl"
#include "shared/source/os_interface/hw_info_config_bdw_and_later.inl"
namespace NEO {
constexpr static auto gfxProduct = IGFX_ALDERLAKE_N;
#include "shared/source/gen12lp/adln/os_agnostic_hw_info_config_adln.inl"
#include "shared/source/gen12lp/os_agnostic_hw_info_config_gen12lp.inl"
template class HwInfoConfigHw<gfxProduct>;
} // namespace NEO