mirror of
https://github.com/intel/compute-runtime.git
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Opensource adln
Related-To: NEO-6818 Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>
This commit is contained in:
committed by
Compute-Runtime-Automation
parent
adfc3a1e7a
commit
1b7555a49d
@@ -0,0 +1,29 @@
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/*
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* Copyright (C) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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template <>
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uint32_t HwInfoConfigHw<gfxProduct>::getHwRevIdFromStepping(uint32_t stepping, const HardwareInfo &hwInfo) const {
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switch (stepping) {
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case REVISION_A0:
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return 0x0;
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}
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return CommonConstants::invalidStepping;
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}
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template <>
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PRODUCT_CONFIG HwInfoConfigHw<gfxProduct>::getProductConfigFromHwInfo(const HardwareInfo &hwInfo) const {
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return PRODUCT_CONFIG::ADL_N;
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}
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template <>
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uint32_t HwInfoConfigHw<gfxProduct>::getSteppingFromHwRevId(const HardwareInfo &hwInfo) const {
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switch (hwInfo.platform.usRevId) {
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case 0x0:
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return REVISION_A0;
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}
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return CommonConstants::invalidStepping;
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}
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6
shared/source/gen12lp/definitions/hw_cmds_adln.inl
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6
shared/source/gen12lp/definitions/hw_cmds_adln.inl
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@@ -0,0 +1,6 @@
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/*
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* Copyright (C) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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15
shared/source/gen12lp/definitions/hw_info_setup_adln.inl
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15
shared/source/gen12lp/definitions/hw_info_setup_adln.inl
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@@ -0,0 +1,15 @@
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/*
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* Copyright (C) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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const uint64_t ADLN::defaultHardwareInfoConfig = 0x0;
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const HardwareInfo ADLN::hwInfo = ADLN_CONFIG::hwInfo;
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void setupADLNHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig) {
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ADLN_CONFIG::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
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}
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void (*ADLN::setupHardwareInfo)(HardwareInfo *, bool, const uint64_t) = setupADLNHardwareInfoImpl;
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@@ -35,4 +35,8 @@ static EnableCompilerHwInfoConfig<IGFX_ALDERLAKE_S> enableCompilerHwInfoConfigAD
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static EnableGfxProductHw<IGFX_ALDERLAKE_P> enableGfxProductHwADLP;
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static EnableCompilerHwInfoConfig<IGFX_ALDERLAKE_P> enableCompilerHwInfoConfigADLP;
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#endif
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#ifdef SUPPORT_ADLN
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static EnableGfxProductHw<IGFX_ALDERLAKE_N> enableGfxProductHwADLN;
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static EnableCompilerHwInfoConfig<IGFX_ALDERLAKE_N> enableCompilerHwInfoConfigADLN;
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#endif
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} // namespace NEO
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15
shared/source/gen12lp/enable_hw_info_config_adln.cpp
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15
shared/source/gen12lp/enable_hw_info_config_adln.cpp
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/*
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* Copyright (C) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "shared/source/gen12lp/hw_cmds.h"
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#include "shared/source/os_interface/hw_info_config.h"
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namespace NEO {
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static EnableProductHwInfoConfig<IGFX_ALDERLAKE_N> enableADLN;
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} // namespace NEO
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2019-2021 Intel Corporation
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* Copyright (C) 2019-2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -22,3 +22,6 @@
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#ifdef SUPPORT_ADLP
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#include "hw_cmds_adlp.h"
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#endif
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#ifdef SUPPORT_ADLN
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#include "hw_cmds_adln.h"
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#endif
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38
shared/source/gen12lp/hw_cmds_adln.h
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38
shared/source/gen12lp/hw_cmds_adln.h
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/*
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* Copyright (C) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "shared/source/gen12lp/hw_cmds_base.h"
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namespace NEO {
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struct ADLN : public TGLLPFamily {
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static const PLATFORM platform;
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static const HardwareInfo hwInfo;
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static const uint64_t defaultHardwareInfoConfig;
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static FeatureTable featureTable;
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static WorkaroundTable workaroundTable;
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static const uint32_t threadsPerEu = 7;
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static const uint32_t maxEuPerSubslice = 16;
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static const uint32_t maxSlicesSupported = 1;
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static const uint32_t maxSubslicesSupported = 6;
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static const uint32_t maxDualSubslicesSupported = 12;
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static const RuntimeCapabilityTable capabilityTable;
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static void (*setupHardwareInfo)(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig);
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static void setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo);
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static void setupHardwareInfoBase(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable);
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};
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class ADLN_CONFIG : public ADLN {
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public:
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static void setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable);
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static const HardwareInfo hwInfo;
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private:
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static GT_SYSTEM_INFO gtSystemInfo;
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};
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#include "hw_cmds_adln.inl"
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} // namespace NEO
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2019-2021 Intel Corporation
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* Copyright (C) 2019-2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -20,4 +20,7 @@
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#endif
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#ifdef SUPPORT_ADLP
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#include "hw_info_adlp.h"
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#endif
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#ifdef SUPPORT_ADLN
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#include "hw_info_adln.h"
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#endif
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162
shared/source/gen12lp/hw_info_adln.cpp
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162
shared/source/gen12lp/hw_info_adln.cpp
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@@ -0,0 +1,162 @@
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/*
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* Copyright (C) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "shared/source/aub_mem_dump/definitions/aub_services.h"
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#include "shared/source/gen12lp/hw_cmds.h"
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#include "shared/source/helpers/constants.h"
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#include "engine_node.h"
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namespace NEO {
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const char *HwMapper<IGFX_ALDERLAKE_N>::abbreviation = "adln";
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bool isSimulationADLN(unsigned short deviceId) {
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return false;
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};
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const PLATFORM ADLN::platform = {
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IGFX_ALDERLAKE_N,
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PCH_UNKNOWN,
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IGFX_GEN12LP_CORE,
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IGFX_GEN12LP_CORE,
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PLATFORM_NONE, // default init
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0, // usDeviceID
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0, // usRevId. 0 sets the stepping to A0
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0, // usDeviceID_PCH
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0, // usRevId_PCH
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GTTYPE_UNDEFINED};
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const RuntimeCapabilityTable ADLN::capabilityTable{
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EngineDirectSubmissionInitVec{
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{aub_stream::ENGINE_RCS, {true, true}},
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{aub_stream::ENGINE_CCS, {true, true}}}, // directSubmissionEngines
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{0, 0, 0, 0, false, false, false, false}, // kmdNotifyProperties
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MemoryConstants::max64BitAppAddress, // gpuAddressSpace
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0, // sharedSystemMemCapabilities
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83.333, // defaultProfilingTimerResolution
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MemoryConstants::pageSize, // requiredPreemptionSurfaceSize
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&isSimulationADLN, // isSimulation
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"lp", // platformType
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"", // deviceName
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PreemptionMode::MidThread, // defaultPreemptionMode
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aub_stream::ENGINE_RCS, // defaultEngineType
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0, // maxRenderFrequency
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30, // clVersionSupport
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CmdServicesMemTraceVersion::DeviceValues::Adln, // aubDeviceId
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1, // extraQuantityThreadsPerEU
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64, // slmSize
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sizeof(ADLN::GRF), // grfSize
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36u, // timestampValidBits
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32u, // kernelTimestampValidBits
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false, // blitterOperationsSupported
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true, // ftrSupportsInteger64BitAtomics
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false, // ftrSupportsFP64
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false, // ftrSupports64BitMath
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true, // ftrSvm
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false, // ftrSupportsCoherency
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false, // ftrSupportsVmeAvcTextureSampler
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false, // ftrSupportsVmeAvcPreemption
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false, // ftrRenderCompressedBuffers
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false, // ftrRenderCompressedImages
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true, // instrumentationEnabled
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true, // ftr64KBpages
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true, // sourceLevelDebuggerSupported
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false, // supportsVme
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false, // supportCacheFlushAfterWalker
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true, // supportsImages
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false, // supportsDeviceEnqueue
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false, // supportsPipes
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true, // supportsOcl21Features
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false, // supportsOnDemandPageFaults
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false, // supportsIndependentForwardProgress
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false, // hostPtrTrackingEnabled
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true, // levelZeroSupported
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true, // isIntegratedDevice
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true, // supportsMediaBlock
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false, // p2pAccessSupported
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false, // p2pAtomicAccessSupported
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true // fusedEuEnabled
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};
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WorkaroundTable ADLN::workaroundTable = {};
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FeatureTable ADLN::featureTable = {};
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void ADLN::setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo) {
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FeatureTable *featureTable = &hwInfo->featureTable;
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WorkaroundTable *workaroundTable = &hwInfo->workaroundTable;
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featureTable->flags.ftrL3IACoherency = true;
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featureTable->flags.ftrPPGTT = true;
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featureTable->flags.ftrSVM = true;
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featureTable->flags.ftrIA32eGfxPTEs = true;
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featureTable->flags.ftrStandardMipTailFormat = true;
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featureTable->flags.ftrTranslationTable = true;
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featureTable->flags.ftrUserModeTranslationTable = true;
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featureTable->flags.ftrTileMappedResource = true;
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featureTable->flags.ftrEnableGuC = true;
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featureTable->flags.ftrFbc = true;
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featureTable->flags.ftrFbc2AddressTranslation = true;
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featureTable->flags.ftrFbcBlitterTracking = true;
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featureTable->flags.ftrFbcCpuTracking = true;
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featureTable->flags.ftrTileY = true;
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featureTable->flags.ftrAstcHdr2D = true;
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featureTable->flags.ftrAstcLdr2D = true;
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featureTable->flags.ftr3dMidBatchPreempt = true;
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featureTable->flags.ftrGpGpuMidBatchPreempt = true;
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featureTable->flags.ftrGpGpuThreadGroupLevelPreempt = true;
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featureTable->flags.ftrPerCtxtPreemptionGranularityControl = true;
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workaroundTable->flags.wa4kAlignUVOffsetNV12LinearSurface = true;
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workaroundTable->flags.waEnablePreemptionGranularityControlByUMD = true;
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workaroundTable->flags.waUntypedBufferCompression = true;
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};
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void ADLN::setupHardwareInfoBase(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
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GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
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gtSysInfo->ThreadCount = gtSysInfo->EUCount * ADLN::threadsPerEu;
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gtSysInfo->TotalPsThreadsWindowerRange = 64;
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gtSysInfo->CsrSizeInMb = 8;
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gtSysInfo->MaxEuPerSubSlice = ADLN::maxEuPerSubslice;
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gtSysInfo->MaxSlicesSupported = ADLN::maxSlicesSupported;
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gtSysInfo->MaxSubSlicesSupported = ADLN::maxSubslicesSupported;
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gtSysInfo->MaxDualSubSlicesSupported = ADLN::maxDualSubslicesSupported;
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gtSysInfo->IsL3HashModeEnabled = false;
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gtSysInfo->IsDynamicallyPopulated = false;
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if (setupFeatureTableAndWorkaroundTable) {
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setupFeatureAndWorkaroundTable(hwInfo);
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}
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}
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const HardwareInfo ADLN_CONFIG::hwInfo = {
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&ADLN::platform,
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&ADLN::featureTable,
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&ADLN::workaroundTable,
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&ADLN_CONFIG::gtSystemInfo,
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ADLN::capabilityTable,
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};
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GT_SYSTEM_INFO ADLN_CONFIG::gtSystemInfo = {0};
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void ADLN_CONFIG::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
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ADLN::setupHardwareInfoBase(hwInfo, setupFeatureTableAndWorkaroundTable);
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GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
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gtSysInfo->L3CacheSizeInKb = 1920;
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gtSysInfo->L3BankCount = 4;
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gtSysInfo->MaxFillRate = 8;
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gtSysInfo->CCSInfo.IsValid = true;
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gtSysInfo->CCSInfo.NumberOfCCSEnabled = 1;
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gtSysInfo->CCSInfo.Instances.CCSEnableMask = 0b1;
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};
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#include "hw_info_setup_adln.inl"
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} // namespace NEO
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23
shared/source/gen12lp/hw_info_adln.h
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23
shared/source/gen12lp/hw_info_adln.h
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@@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "shared/source/gen12lp/hw_info_gen12lp.h"
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namespace NEO {
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struct ADLN;
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template <>
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struct HwMapper<IGFX_ALDERLAKE_N> {
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enum { gfxFamily = IGFX_GEN12LP_CORE };
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static const char *abbreviation;
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using GfxFamily = GfxFamilyMapper<static_cast<GFXCORE_FAMILY>(gfxFamily)>::GfxFamily;
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using GfxProduct = ADLN;
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};
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} // namespace NEO
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21
shared/source/gen12lp/linux/hw_info_config_adln.cpp
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21
shared/source/gen12lp/linux/hw_info_config_adln.cpp
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@@ -0,0 +1,21 @@
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/*
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* Copyright (C) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "shared/source/gen12lp/hw_cmds_base.h"
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#include "shared/source/helpers/hw_info.h"
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#include "shared/source/os_interface/hw_info_config.h"
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#include "shared/source/os_interface/hw_info_config.inl"
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#include "shared/source/os_interface/hw_info_config_bdw_and_later.inl"
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namespace NEO {
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constexpr static auto gfxProduct = IGFX_ALDERLAKE_N;
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#include "shared/source/gen12lp/adln/os_agnostic_hw_info_config_adln.inl"
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#include "shared/source/gen12lp/os_agnostic_hw_info_config_gen12lp.inl"
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template class HwInfoConfigHw<gfxProduct>;
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} // namespace NEO
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21
shared/source/gen12lp/windows/hw_info_config_adln.cpp
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21
shared/source/gen12lp/windows/hw_info_config_adln.cpp
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@@ -0,0 +1,21 @@
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/*
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* Copyright (C) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "shared/source/gen12lp/hw_cmds_base.h"
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#include "shared/source/helpers/hw_info.h"
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#include "shared/source/os_interface/hw_info_config.h"
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#include "shared/source/os_interface/hw_info_config.inl"
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#include "shared/source/os_interface/hw_info_config_bdw_and_later.inl"
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namespace NEO {
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constexpr static auto gfxProduct = IGFX_ALDERLAKE_N;
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#include "shared/source/gen12lp/adln/os_agnostic_hw_info_config_adln.inl"
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#include "shared/source/gen12lp/os_agnostic_hw_info_config_gen12lp.inl"
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template class HwInfoConfigHw<gfxProduct>;
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} // namespace NEO
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