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fix: use per product cache line size to align heaps

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Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
This commit is contained in:
Maciej Plewka
2024-07-24 15:50:00 +00:00
committed by Compute-Runtime-Automation
parent e233cf5127
commit 1cd00b5b89
15 changed files with 71 additions and 27 deletions
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1
shared/source/xe_hpc_core/hw_cmds_pvc.h
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@@ -63,7 +63,6 @@ struct PVC : public XeHpcCoreFamily {
}
static constexpr uint32_t pvcSteppingBits = 0b111;
static constexpr uint32_t cacheLineSize = 0x40;
static constexpr bool isDcFlushAllowed = false;
};

1
shared/source/xe_hpc_core/hw_cmds_xe_hpc_core_base.h
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@@ -74,6 +74,7 @@ struct XeHpcCore {
return bindlessSurfaceOffset << 6;
}
};
static constexpr uint32_t cacheLineSize = 0x40;
static_assert(sizeof(DataPortBindlessSurfaceExtendedMessageDescriptor) == sizeof(DataPortBindlessSurfaceExtendedMessageDescriptor::packed), "");
};