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Apply CamelCase for class and struct names 2/2

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Additionally change .clang-tidy not to ignore struct names.

Signed-off-by: Fabian Zwolinski <fabian.zwolinski@intel.com>
This commit is contained in:
Fabian Zwolinski
2023-04-24 17:17:08 +00:00
committed by Compute-Runtime-Automation
parent e48bb5ad6a
commit 2022592f3d
122 changed files with 636 additions and 630 deletions
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4
shared/source/debug_settings/debug_settings_manager.h
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@@ -82,8 +82,8 @@ struct DebugVarBase {
T defaultValue;
};
struct DebugVariables { // NOLINT(clang-analyzer-optin.performance.Padding)
struct DEBUGGER_LOG_BITMASK {
struct DebugVariables { // NOLINT(clang-analyzer-optin.performance.Padding)
struct DEBUGGER_LOG_BITMASK { // NOLINT(readability-identifier-naming)
constexpr static int32_t LOG_INFO{1}; // NOLINT(readability-identifier-naming)
constexpr static int32_t LOG_ERROR{1 << 1}; // NOLINT(readability-identifier-naming)
constexpr static int32_t LOG_THREADS{1 << 2}; // NOLINT(readability-identifier-naming)

8
shared/source/device/device.cpp
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@@ -797,7 +797,7 @@ bool Device::generateUuidFromPciBusInfo(const PhysicalDevicePciBusInfo &pciBusIn
* Consult other driver teams before changing this.
*/
struct device_uuid {
struct DeviceUUID {
uint16_t vendor_id;
uint16_t device_id;
uint16_t revision_id;
@@ -809,7 +809,7 @@ bool Device::generateUuidFromPciBusInfo(const PhysicalDevicePciBusInfo &pciBusIn
uint8_t sub_device_id;
};
device_uuid deviceUUID = {};
DeviceUUID deviceUUID = {};
deviceUUID.vendor_id = 0x8086; // Intel
deviceUUID.device_id = getHardwareInfo().platform.usDeviceID;
deviceUUID.revision_id = getHardwareInfo().platform.usRevId;
@@ -819,9 +819,9 @@ bool Device::generateUuidFromPciBusInfo(const PhysicalDevicePciBusInfo &pciBusIn
deviceUUID.pci_func = static_cast<uint8_t>(pciBusInfo.pciFunction);
deviceUUID.sub_device_id = isSubDevice() ? static_cast<SubDevice *>(this)->getSubDeviceIndex() + 1 : 0;
static_assert(sizeof(device_uuid) == ProductHelper::uuidSize);
static_assert(sizeof(DeviceUUID) == ProductHelper::uuidSize);
memcpy_s(uuid.data(), ProductHelper::uuidSize, &deviceUUID, sizeof(device_uuid));
memcpy_s(uuid.data(), ProductHelper::uuidSize, &deviceUUID, sizeof(DeviceUUID));
return true;
}

3
shared/source/generated/.clang-tidy Normal file
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@@ -0,0 +1,3 @@
---
Checks: '-*'
...

2
shared/source/helpers/uint16_avx2.h
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@@ -15,7 +15,7 @@
namespace NEO {
#if __AVX2__
struct uint16x16_t {
struct uint16x16_t { // NOLINT(readability-identifier-naming)
enum { numChannels = 16 };
__m256i value;

2
shared/source/helpers/uint16_sse4.h
View File

@@ -18,7 +18,7 @@
namespace NEO {
struct uint16x8_t {
struct uint16x8_t { // NOLINT(readability-identifier-naming)
enum { numChannels = 8 };
__m128i value;

10
shared/source/os_interface/linux/xe/ioctl_helper_xe.cpp
View File

@@ -40,7 +40,7 @@
namespace NEO {
#define VMBIND_FENCE_TAG 0x123987
struct xe_fake_ext_user_fence {
struct XeFakeExtUserFence {
uint32_t tag;
uint64_t addr;
uint64_t value;
@@ -382,7 +382,7 @@ int IoctlHelperXe::createGemExt(const MemRegionsVec &memClassInstances, size_t a
{
std::unique_lock<std::mutex> lock(xeLock);
bind_info b = {create.handle, 0, 0, create.size};
BindInfo b = {create.handle, 0, 0, create.size};
bindInfo.push_back(b);
}
@@ -628,7 +628,7 @@ void IoctlHelperXe::fillVmBindExtSetPat(VmBindExtSetPatT &vmBindExtSetPat, uint6
void IoctlHelperXe::fillVmBindExtUserFence(VmBindExtUserFenceT &vmBindExtUserFence, uint64_t fenceAddress, uint64_t fenceValue, uint64_t nextExtension) {
xeLog(" -> IoctlHelperXe::%s 0x%lx 0x%lx\n", __FUNCTION__, fenceAddress, fenceValue);
auto xeBindExtUserFence = reinterpret_cast<xe_fake_ext_user_fence *>(vmBindExtUserFence);
auto xeBindExtUserFence = reinterpret_cast<XeFakeExtUserFence *>(vmBindExtUserFence);
UNRECOVERABLE_IF(!xeBindExtUserFence);
xeBindExtUserFence->tag = VMBIND_FENCE_TAG;
xeBindExtUserFence->addr = fenceAddress;
@@ -895,7 +895,7 @@ int IoctlHelperXe::ioctl(DrmIoctl request, void *arg) {
d->handle = userPtrHandle++ | XE_USERPTR_FAKE_FLAG;
{
std::unique_lock<std::mutex> lock(xeLock);
bind_info b = {d->handle, d->userPtr, 0, d->userSize};
BindInfo b = {d->handle, d->userPtr, 0, d->userSize};
bindInfo.push_back(b);
}
ret = 0;
@@ -1189,7 +1189,7 @@ int IoctlHelperXe::xeVmBind(const VmBindParams &vmBindParams, bool bindOp) {
struct drm_xe_sync sync[1] = {};
sync[0].flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL;
extraBindFlag = XE_VM_BIND_FLAG_ASYNC;
auto xeBindExtUserFence = reinterpret_cast<xe_fake_ext_user_fence *>(vmBindParams.extensions);
auto xeBindExtUserFence = reinterpret_cast<XeFakeExtUserFence *>(vmBindParams.extensions);
UNRECOVERABLE_IF(!xeBindExtUserFence);
UNRECOVERABLE_IF(xeBindExtUserFence->tag != VMBIND_FENCE_TAG);
sync[0].addr = xeBindExtUserFence->addr;

4
shared/source/os_interface/linux/xe/ioctl_helper_xe.h
View File

@@ -25,7 +25,7 @@ struct drm_xe_engine_class_instance;
namespace NEO {
struct bind_info {
struct BindInfo {
uint32_t handle;
uint64_t userptr;
uint64_t addr;
@@ -127,7 +127,7 @@ class IoctlHelperXe : public IoctlHelper {
std::unique_ptr<struct drm_xe_engine_class_instance[]> hwEngines;
int xe_fileHandle = 0;
std::mutex xeLock;
std::vector<bind_info> bindInfo;
std::vector<BindInfo> bindInfo;
int instance = 0;
uint64_t xeMemoryRegions = 0;
uint32_t xeTimestampFrequency = 0;

4
shared/source/os_interface/windows/gfx_escape_wrapper.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -12,7 +12,7 @@
#ifdef _WIN32
#include "gfxEscape.h"
#else // !_WIN32
typedef struct GFX_ESCAPE_HEADER {
typedef struct GFX_ESCAPE_HEADER { // NOLINT(readability-identifier-naming)
union {
struct
{

12
shared/source/os_interface/windows/sharedata_wrapper.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -47,7 +47,7 @@ static constexpr COMMAND_BUFFER_HEADER initCommandBufferHeader(uint32_t umdConte
#endif
#else
struct SKU_FEATURE_TABLE_KMD : SKU_FEATURE_TABLE_GMM {
struct SKU_FEATURE_TABLE_KMD : SKU_FEATURE_TABLE_GMM { // NOLINT(readability-identifier-naming)
bool FtrGpGpuMidBatchPreempt : 1;
bool FtrGpGpuThreadGroupLevelPreempt : 1;
bool FtrGpGpuMidThreadLevelPreempt : 1;
@@ -94,7 +94,7 @@ struct SKU_FEATURE_TABLE_KMD : SKU_FEATURE_TABLE_GMM {
bool FtrLocalMemoryAllows4KB : 1;
};
struct WA_TABLE_KMD : WA_TABLE_GMM {
struct WA_TABLE_KMD : WA_TABLE_GMM { // NOLINT(readability-identifier-naming)
bool WaSendMIFLUSHBeforeVFE = false;
bool WaDisableLSQCROPERFforOCL = false;
@@ -118,7 +118,7 @@ struct WA_TABLE_KMD : WA_TABLE_GMM {
bool WaDisableFusedThreadScheduling = false;
};
typedef struct COMMAND_BUFFER_HEADER_REC {
typedef struct COMMAND_BUFFER_HEADER_REC { // NOLINT(readability-identifier-naming)
uint32_t UmdContextType : 4;
uint32_t UmdPatchList : 1;
@@ -149,7 +149,7 @@ typedef struct __GMM_GFX_PARTITIONING {
Heap32[4];
} GMM_GFX_PARTITIONING;
struct CREATECONTEXT_PVTDATA {
struct CREATECONTEXT_PVTDATA { // NOLINT(readability-identifier-naming)
unsigned long *pHwContextId;
uint32_t NumberOfHwContextIds;
@@ -161,7 +161,7 @@ struct CREATECONTEXT_PVTDATA {
BOOLEAN NoRingFlushes;
};
struct ADAPTER_INFO_KMD : ADAPTER_INFO_GMM {
struct ADAPTER_INFO_KMD : ADAPTER_INFO_GMM { // NOLINT(readability-identifier-naming)
SKU_FEATURE_TABLE_KMD SkuTable;
WA_TABLE_KMD WaTable;
GMM_GFX_PARTITIONING GfxPartition;

136
shared/source/tbx/tbx_proto.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -47,7 +47,7 @@ enum HAS_MSG_TYPE {
NUM_OF_MSG_TYPE
};
struct HAS_HDR {
struct HasHdr {
union {
uint32_t msg_type;
HAS_MSG_TYPE type;
@@ -62,7 +62,7 @@ enum {
MSG_TYPE_FUNNY_IO
};
struct HAS_MMIO_REQ {
struct HasMmioReq {
uint32_t write : 1;
uint32_t size : 3;
uint32_t dev_idx : 2;
@@ -78,8 +78,8 @@ struct HAS_MMIO_REQ {
};
};
struct HAS_MMIO_EXT_REQ {
struct HAS_MMIO_REQ mmio_req;
struct HasMmioExtReq {
struct HasMmioReq mmio_req;
uint32_t sourceid : 8;
uint32_t reserved1 : 24;
enum {
@@ -87,7 +87,7 @@ struct HAS_MMIO_EXT_REQ {
};
};
struct HAS_MMIO_RES {
struct HasMmioRes {
uint32_t data;
enum {
@@ -95,7 +95,7 @@ struct HAS_MMIO_RES {
};
};
struct HAS_GTT32_REQ {
struct HasGtt32Req {
uint32_t write : 1;
uint32_t reserved : 31;
@@ -107,7 +107,7 @@ struct HAS_GTT32_REQ {
};
};
struct HAS_GTT32_RES {
struct HasGtt32Res {
uint32_t data;
enum {
@@ -115,7 +115,7 @@ struct HAS_GTT32_RES {
};
};
struct HAS_GTT64_REQ {
struct HasGtt64Req {
uint32_t write : 1;
uint32_t reserved : 31;
@@ -128,7 +128,7 @@ struct HAS_GTT64_REQ {
};
};
struct HAS_GTT64_RES {
struct HasGtt64Res {
uint32_t data;
uint32_t data_h;
@@ -137,7 +137,7 @@ struct HAS_GTT64_RES {
};
};
struct HAS_WRITE_DATA_REQ {
struct HasWriteDataReq {
uint32_t addr_type : 1;
uint32_t mask_exist : 1;
uint32_t frontdoor : 1;
@@ -155,7 +155,7 @@ struct HAS_WRITE_DATA_REQ {
};
};
struct HAS_READ_DATA_REQ {
struct HasReadDataReq {
uint32_t addr_type : 1;
uint32_t frontdoor : 1;
uint32_t ownership_req : 1;
@@ -171,7 +171,7 @@ struct HAS_READ_DATA_REQ {
};
};
struct HAS_READ_DATA_RES {
struct HasReadDataRes {
uint32_t addr_type : 1;
uint32_t mask_exist : 1;
uint32_t last_page : 1;
@@ -186,7 +186,7 @@ struct HAS_READ_DATA_RES {
};
};
struct HAS_CONTROL_REQ {
struct HasControlReq {
uint32_t reset : 1; // [0:0]
uint32_t has : 1; // [1:1]
uint32_t rd_on_demand : 1; // [2:2]
@@ -222,7 +222,7 @@ struct HAS_CONTROL_REQ {
};
};
struct HAS_REPORT_REND_END_REQ {
struct HasReportRendEndReq {
uint32_t timeout;
enum {
@@ -230,7 +230,7 @@ struct HAS_REPORT_REND_END_REQ {
};
};
struct HAS_REPORT_REND_END_RES {
struct HasReportRendEndRes {
uint32_t timeout : 1;
uint32_t reserved : 31;
@@ -239,7 +239,7 @@ struct HAS_REPORT_REND_END_RES {
};
};
struct HAS_PCICFG_REQ {
struct HasPcicfgReq {
uint32_t write : 1;
uint32_t size : 3;
uint32_t bus : 8;
@@ -254,11 +254,11 @@ struct HAS_PCICFG_REQ {
};
};
struct HAS_PCICFG_RES {
struct HasPcicfgRes {
uint32_t data;
};
struct HAS_GTT_PARAMS_REQ {
struct HasGttParamsReq {
uint32_t base;
uint32_t base_h : 8;
uint32_t size : 24;
@@ -268,7 +268,7 @@ struct HAS_GTT_PARAMS_REQ {
};
};
struct HAS_EVENT_OBSOLETE_REQ {
struct HasEventObsoleteReq {
uint32_t offset;
uint32_t data;
@@ -277,7 +277,7 @@ struct HAS_EVENT_OBSOLETE_REQ {
};
};
struct HAS_EVENT_REQ {
struct HasEventReq {
uint32_t offset;
uint32_t data;
uint32_t dev_idx : 2;
@@ -288,7 +288,7 @@ struct HAS_EVENT_REQ {
};
};
struct HAS_INNER_VAR_REQ {
struct HasInnerVarReq {
uint32_t write : 1;
uint32_t non_dword : 16;
uint32_t reserved : 15;
@@ -300,7 +300,7 @@ struct HAS_INNER_VAR_REQ {
};
};
struct HAS_INNER_VAR_RES {
struct HasInnerVarRes {
uint32_t data;
enum {
@@ -308,7 +308,7 @@ struct HAS_INNER_VAR_RES {
};
};
struct HAS_INNER_VAR_LIST_RES {
struct HasInnerVarListRes {
uint32_t size;
enum {
@@ -316,14 +316,14 @@ struct HAS_INNER_VAR_LIST_RES {
};
};
struct HAS_INTERNAL_VAR_LIST_ENTRY_RES {
struct HasInternalVarListEntryRes {
uint32_t id;
uint32_t min;
uint32_t max;
uint32_t desc_size;
};
struct HAS_FUNNY_IO_REQ {
struct HasFunnyIoReq {
uint32_t write : 1;
uint32_t reserved : 28;
uint32_t size : 3;
@@ -335,7 +335,7 @@ struct HAS_FUNNY_IO_REQ {
};
};
struct HAS_FUNNY_IO_RES {
struct HasFunnyIoRes {
uint32_t data;
enum {
@@ -343,7 +343,7 @@ struct HAS_FUNNY_IO_RES {
};
};
struct HAS_IO_REQ {
struct HasIoReq {
uint32_t write : 1;
uint32_t dev_idx : 2;
uint32_t reserved : 26;
@@ -356,7 +356,7 @@ struct HAS_IO_REQ {
};
};
struct HAS_IO_RES {
struct HasIoRes {
uint32_t data;
enum {
@@ -364,7 +364,7 @@ struct HAS_IO_RES {
};
};
struct HAS_RPC_REQ {
struct HasRpcReq {
uint32_t size;
enum {
@@ -372,7 +372,7 @@ struct HAS_RPC_REQ {
};
};
struct HAS_RPC_RES {
struct HasRpcRes {
uint32_t status;
uint32_t size;
@@ -381,7 +381,7 @@ struct HAS_RPC_RES {
};
};
struct HAS_CL_FLUSH_REQ {
struct HasClFlushReq {
uint32_t reserved : 23;
uint32_t ignore : 1;
uint32_t address_h : 8;
@@ -394,7 +394,7 @@ struct HAS_CL_FLUSH_REQ {
};
};
struct HAS_CL_FLUSH_RES {
struct HasClFlushRes {
uint32_t data;
enum {
@@ -402,7 +402,7 @@ struct HAS_CL_FLUSH_RES {
};
};
struct HAS_SIMTIME_RES {
struct HasSimtimeRes {
uint32_t data_l;
uint32_t data_h;
@@ -411,7 +411,7 @@ struct HAS_SIMTIME_RES {
};
};
struct HAS_GD2_MESSAGE {
struct HasGd2Message {
uint32_t subOpcode;
uint32_t data[1];
@@ -420,41 +420,41 @@ struct HAS_GD2_MESSAGE {
};
};
union HAS_MSG_BODY {
struct HAS_MMIO_REQ mmio_req;
struct HAS_MMIO_EXT_REQ mmio_req_ext;
struct HAS_MMIO_RES mmio_res;
struct HAS_GTT32_REQ gtt32_req;
struct HAS_GTT32_RES gtt32_res;
struct HAS_GTT64_REQ gtt64_req;
struct HAS_GTT64_RES gtt64_res;
struct HAS_WRITE_DATA_REQ write_req;
struct HAS_READ_DATA_REQ read_req;
struct HAS_READ_DATA_RES read_res;
struct HAS_CONTROL_REQ control_req;
struct HAS_REPORT_REND_END_REQ render_req;
struct HAS_REPORT_REND_END_RES render_res;
struct HAS_PCICFG_REQ pcicfg_req;
struct HAS_PCICFG_RES pcicfg_res;
struct HAS_GTT_PARAMS_REQ gtt_params_req;
struct HAS_EVENT_REQ event_req;
struct HAS_EVENT_OBSOLETE_REQ event_obsolete_req;
struct HAS_INNER_VAR_REQ inner_var_req;
struct HAS_INNER_VAR_RES inner_var_res;
struct HAS_INNER_VAR_LIST_RES inner_var_list_res;
struct HAS_IO_REQ io_req;
struct HAS_IO_RES io_res;
struct HAS_RPC_REQ rpc_req;
struct HAS_RPC_RES rpc_res;
struct HAS_CL_FLUSH_REQ flush_req;
struct HAS_CL_FLUSH_RES flush_res;
struct HAS_SIMTIME_RES stime_res;
struct HAS_GD2_MESSAGE gd2_message_req;
union HasMsgBody {
struct HasMmioReq mmio_req;
struct HasMmioExtReq mmio_req_ext;
struct HasMmioRes mmio_res;
struct HasGtt32Req gtt32_req;
struct HasGtt32Res gtt32_res;
struct HasGtt64Req gtt64_req;
struct HasGtt64Res gtt64_res;
struct HasWriteDataReq write_req;
struct HasReadDataReq read_req;
struct HasReadDataRes read_res;
struct HasControlReq control_req;
struct HasReportRendEndReq render_req;
struct HasReportRendEndRes render_res;
struct HasPcicfgReq pcicfg_req;
struct HasPcicfgRes pcicfg_res;
struct HasGttParamsReq gtt_params_req;
struct HasEventReq event_req;
struct HasEventObsoleteReq event_obsolete_req;
struct HasInnerVarReq inner_var_req;
struct HasInnerVarRes inner_var_res;
struct HasInnerVarListRes inner_var_list_res;
struct HasIoReq io_req;
struct HasIoRes io_res;
struct HasRpcReq rpc_req;
struct HasRpcRes rpc_res;
struct HasClFlushReq flush_req;
struct HasClFlushRes flush_res;
struct HasSimtimeRes stime_res;
struct HasGd2Message gd2_message_req;
};
struct HAS_MSG {
struct HAS_HDR hdr;
union HAS_MSG_BODY u;
struct HasMsg {
struct HasHdr hdr;
union HasMsgBody u;
};
enum mem_types : uint32_t {

46
shared/source/tbx/tbx_sockets_imp.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2020 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -81,10 +81,10 @@ bool TbxSocketsImp::init(const std::string &hostNameOrIp, uint16_t port) {
break;
}
HAS_MSG cmd;
HasMsg cmd;
memset(&cmd, 0, sizeof(cmd));
cmd.hdr.msg_type = HAS_CONTROL_REQ_TYPE;
cmd.hdr.size = sizeof(HAS_CONTROL_REQ);
cmd.hdr.size = sizeof(HasControlReq);
cmd.hdr.trans_id = transID++;
cmd.u.control_req.time_adv_mask = 1;
@@ -96,7 +96,7 @@ bool TbxSocketsImp::init(const std::string &hostNameOrIp, uint16_t port) {
cmd.u.control_req.has_mask = 1;
cmd.u.control_req.has = 1;
sendWriteData(&cmd, sizeof(HAS_HDR) + cmd.hdr.size);
sendWriteData(&cmd, sizeof(HasHdr) + cmd.hdr.size);
} while (false);
return m_socket != INVALID_SOCKET;
@@ -134,10 +134,10 @@ bool TbxSocketsImp::connectToServer(const std::string &hostNameOrIp, uint16_t po
bool TbxSocketsImp::readMMIO(uint32_t offset, uint32_t *data) {
bool success;
do {
HAS_MSG cmd;
HasMsg cmd;
memset(&cmd, 0, sizeof(cmd));
cmd.hdr.msg_type = HAS_MMIO_REQ_TYPE;
cmd.hdr.size = sizeof(HAS_MMIO_REQ);
cmd.hdr.size = sizeof(HasMmioReq);
cmd.hdr.trans_id = transID++;
cmd.u.mmio_req.offset = offset;
cmd.u.mmio_req.data = 0;
@@ -146,13 +146,13 @@ bool TbxSocketsImp::readMMIO(uint32_t offset, uint32_t *data) {
cmd.u.mmio_req.msg_type = MSG_TYPE_MMIO;
cmd.u.mmio_req.size = sizeof(uint32_t);
success = sendWriteData(&cmd, sizeof(HAS_HDR) + cmd.hdr.size);
success = sendWriteData(&cmd, sizeof(HasHdr) + cmd.hdr.size);
if (!success) {
break;
}
HAS_MSG resp;
success = getResponseData((char *)(&resp), sizeof(HAS_HDR) + sizeof(HAS_MMIO_RES));
HasMsg resp;
success = getResponseData((char *)(&resp), sizeof(HasHdr) + sizeof(HasMmioRes));
if (!success) {
break;
}
@@ -172,10 +172,10 @@ bool TbxSocketsImp::readMMIO(uint32_t offset, uint32_t *data) {
}
bool TbxSocketsImp::writeMMIO(uint32_t offset, uint32_t value) {
HAS_MSG cmd;
HasMsg cmd;
memset(&cmd, 0, sizeof(cmd));
cmd.hdr.msg_type = HAS_MMIO_REQ_TYPE;
cmd.hdr.size = sizeof(HAS_MMIO_REQ);
cmd.hdr.size = sizeof(HasMmioReq);
cmd.hdr.trans_id = transID++;
cmd.u.mmio_req.msg_type = MSG_TYPE_MMIO;
cmd.u.mmio_req.offset = offset;
@@ -183,15 +183,15 @@ bool TbxSocketsImp::writeMMIO(uint32_t offset, uint32_t value) {
cmd.u.mmio_req.write = 1;
cmd.u.mmio_req.size = sizeof(uint32_t);
return sendWriteData(&cmd, sizeof(HAS_HDR) + cmd.hdr.size);
return sendWriteData(&cmd, sizeof(HasHdr) + cmd.hdr.size);
}
bool TbxSocketsImp::readMemory(uint64_t addrOffset, void *data, size_t size) {
HAS_MSG cmd;
HasMsg cmd;
memset(&cmd, 0, sizeof(cmd));
cmd.hdr.msg_type = HAS_READ_DATA_REQ_TYPE;
cmd.hdr.trans_id = transID++;
cmd.hdr.size = sizeof(HAS_READ_DATA_REQ);
cmd.hdr.size = sizeof(HasReadDataReq);
cmd.u.read_req.address = static_cast<uint32_t>(addrOffset);
cmd.u.read_req.address_h = static_cast<uint32_t>(addrOffset >> 32);
cmd.u.read_req.addr_type = 0;
@@ -202,13 +202,13 @@ bool TbxSocketsImp::readMemory(uint64_t addrOffset, void *data, size_t size) {
bool success;
do {
success = sendWriteData(&cmd, sizeof(HAS_HDR) + sizeof(HAS_READ_DATA_REQ));
success = sendWriteData(&cmd, sizeof(HasHdr) + sizeof(HasReadDataReq));
if (!success) {
break;
}
HAS_MSG resp;
success = getResponseData(&resp, sizeof(HAS_HDR) + sizeof(HAS_READ_DATA_RES));
HasMsg resp;
success = getResponseData(&resp, sizeof(HasHdr) + sizeof(HasReadDataRes));
if (!success) {
break;
}
@@ -227,11 +227,11 @@ bool TbxSocketsImp::readMemory(uint64_t addrOffset, void *data, size_t size) {
}
bool TbxSocketsImp::writeMemory(uint64_t physAddr, const void *data, size_t size, uint32_t type) {
HAS_MSG cmd;
HasMsg cmd;
memset(&cmd, 0, sizeof(cmd));
cmd.hdr.msg_type = HAS_WRITE_DATA_REQ_TYPE;
cmd.hdr.trans_id = transID++;
cmd.hdr.size = sizeof(HAS_WRITE_DATA_REQ);
cmd.hdr.size = sizeof(HasWriteDataReq);
cmd.u.write_req.address = static_cast<uint32_t>(physAddr);
cmd.u.write_req.address_h = static_cast<uint32_t>(physAddr >> 32);
@@ -244,7 +244,7 @@ bool TbxSocketsImp::writeMemory(uint64_t physAddr, const void *data, size_t size
bool success;
do {
success = sendWriteData(&cmd, sizeof(HAS_HDR) + sizeof(HAS_WRITE_DATA_REQ));
success = sendWriteData(&cmd, sizeof(HasHdr) + sizeof(HasWriteDataReq));
if (!success) {
break;
}
@@ -261,17 +261,17 @@ bool TbxSocketsImp::writeMemory(uint64_t physAddr, const void *data, size_t size
}
bool TbxSocketsImp::writeGTT(uint32_t offset, uint64_t entry) {
HAS_MSG cmd;
HasMsg cmd;
memset(&cmd, 0, sizeof(cmd));
cmd.hdr.msg_type = HAS_GTT_REQ_TYPE;
cmd.hdr.size = sizeof(HAS_GTT64_REQ);
cmd.hdr.size = sizeof(HasGtt64Req);
cmd.hdr.trans_id = transID++;
cmd.u.gtt64_req.write = 1;
cmd.u.gtt64_req.offset = offset / sizeof(uint64_t); // the TBX server expects GTT index here, not offset
cmd.u.gtt64_req.data = static_cast<uint32_t>(entry & 0xffffffff);
cmd.u.gtt64_req.data_h = static_cast<uint32_t>(entry >> 32);
return sendWriteData(&cmd, sizeof(HAS_HDR) + cmd.hdr.size);
return sendWriteData(&cmd, sizeof(HasHdr) + cmd.hdr.size);
}
bool TbxSocketsImp::sendWriteData(const void *buffer, size_t sizeInBytes) {