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fix: add missing cache flushes on MTL and later integrated GPUs

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hdc pipeline / untyped dataport cache flushes were applied only on discrete GPUs

Related-To: GSD-5085
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski
2023-07-28 10:57:38 +00:00
committed by Compute-Runtime-Automation
parent e1e9907973
commit 27e459dfd0
7 changed files with 32 additions and 32 deletions
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4
level_zero/core/source/cmdlist/cmdlist_hw.inl
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@@ -2374,12 +2374,10 @@ void CommandListCoreFamily<gfxCoreFamily>::appendEventForProfiling(Event *event,
} else {
dispatchEventPostSyncOperation(event, Event::STATE_SIGNALED, true, false, false);
const auto &hwInfo = this->device->getHwInfo();
const auto &rootDeviceEnvironment = this->device->getNEODevice()->getRootDeviceEnvironment();
NEO::PipeControlArgs args;
args.dcFlushEnable = getDcFlushRequired(event->isSignalScope());
NEO::MemorySynchronizationCommands<GfxFamily>::setPostSyncExtraProperties(args,
hwInfo);
NEO::MemorySynchronizationCommands<GfxFamily>::setPostSyncExtraProperties(args);
NEO::MemorySynchronizationCommands<GfxFamily>::addSingleBarrier(*commandContainer.getCommandStream(), args);