diff --git a/level_zero/core/source/gen12lp/dg1/CMakeLists.txt b/level_zero/core/source/gen12lp/dg1/CMakeLists.txt new file mode 100644 index 0000000000..0d9bd7a3d6 --- /dev/null +++ b/level_zero/core/source/gen12lp/dg1/CMakeLists.txt @@ -0,0 +1,18 @@ +# +# Copyright (C) 2019-2020 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +if(SUPPORT_DG1) + set(HW_SOURCES_GEN12LP + ${HW_SOURCES_GEN12LP} + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_dg1.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/cmdqueue_dg1.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel_dg1.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/image_dg1.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/sampler_dg1.cpp + PARENT_SCOPE + ) +endif() diff --git a/level_zero/core/source/gen12lp/dg1/cmdlist_dg1.cpp b/level_zero/core/source/gen12lp/dg1/cmdlist_dg1.cpp new file mode 100644 index 0000000000..4452880163 --- /dev/null +++ b/level_zero/core/source/gen12lp/dg1/cmdlist_dg1.cpp @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2019-2020 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/gen12lp/hw_cmds.h" +#include "shared/source/gen12lp/hw_info.h" + +#include "level_zero/core/source/cmdlist/cmdlist_hw.inl" +#include "level_zero/core/source/cmdlist/cmdlist_hw_base.inl" +#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl" +#include "level_zero/core/source/gen12lp/cmdlist_gen12lp.h" + +#include "cache_flush_gen12lp.inl" +#include "cmdlist_extended.inl" +#include "igfxfmid.h" + +namespace L0 { +template struct CommandListCoreFamily; + +static CommandListPopulateFactory> + populateDG1; + +static CommandListImmediatePopulateFactory> + populateDG1Immediate; + +} // namespace L0 \ No newline at end of file diff --git a/level_zero/core/source/gen12lp/dg1/cmdqueue_dg1.cpp b/level_zero/core/source/gen12lp/dg1/cmdqueue_dg1.cpp new file mode 100644 index 0000000000..1b382e2ff2 --- /dev/null +++ b/level_zero/core/source/gen12lp/dg1/cmdqueue_dg1.cpp @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2019-2020 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/gen12lp/hw_cmds.h" +#include "shared/source/gen12lp/hw_info.h" + +#include "level_zero/core/source/cmdqueue/cmdqueue_hw.inl" +#include "level_zero/core/source/cmdqueue/cmdqueue_hw_base.inl" + +#include "cmdqueue_extended.inl" +#include "igfxfmid.h" + +namespace L0 { +template struct CommandQueueHw; +static CommandQueuePopulateFactory> + populateDG1; + +} // namespace L0 \ No newline at end of file diff --git a/level_zero/core/source/gen12lp/dg1/image_dg1.cpp b/level_zero/core/source/gen12lp/dg1/image_dg1.cpp new file mode 100644 index 0000000000..49a2409094 --- /dev/null +++ b/level_zero/core/source/gen12lp/dg1/image_dg1.cpp @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2019-2020 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/gen12lp/hw_cmds.h" +#include "shared/source/gen12lp/hw_info.h" + +#include "level_zero/core/source/image/image_hw.inl" + +namespace L0 { + +template <> +struct ImageProductFamily : public ImageCoreFamily { + using ImageCoreFamily::ImageCoreFamily; + + bool initialize(Device *device, const ze_image_desc_t *desc) override { + return ImageCoreFamily::initialize(device, desc); + }; +}; + +static ImagePopulateFactory> populateDG1; + +} // namespace L0 diff --git a/level_zero/core/source/gen12lp/dg1/kernel_dg1.cpp b/level_zero/core/source/gen12lp/dg1/kernel_dg1.cpp new file mode 100644 index 0000000000..42026bc4e1 --- /dev/null +++ b/level_zero/core/source/gen12lp/dg1/kernel_dg1.cpp @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2019-2020 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "level_zero/core/source/kernel/kernel_hw.h" + +namespace L0 { + +static KernelPopulateFactory> populateDG1; + +} // namespace L0 \ No newline at end of file diff --git a/level_zero/core/source/gen12lp/dg1/sampler_dg1.cpp b/level_zero/core/source/gen12lp/dg1/sampler_dg1.cpp new file mode 100644 index 0000000000..a7712704e9 --- /dev/null +++ b/level_zero/core/source/gen12lp/dg1/sampler_dg1.cpp @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2019-2020 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/gen12lp/hw_cmds.h" +#include "shared/source/gen12lp/hw_info.h" + +#include "level_zero/core/source/sampler/sampler_hw.inl" + +namespace L0 { + +template <> +struct SamplerProductFamily : public SamplerCoreFamily { + using SamplerCoreFamily::SamplerCoreFamily; +}; + +static SamplerPopulateFactory> populateDG1; + +} // namespace L0 diff --git a/opencl/source/aub_mem_dump/aub_services.h b/opencl/source/aub_mem_dump/aub_services.h index a7cc051a74..832703c866 100644 --- a/opencl/source/aub_mem_dump/aub_services.h +++ b/opencl/source/aub_mem_dump/aub_services.h @@ -100,6 +100,7 @@ struct CmdServicesMemTraceVersion { Cfl = 24, Lkf = 25, Ehl = 28, + Dg1 = 30, Tgllp = 22 }; }; diff --git a/opencl/source/aub_mem_dump/page_table_entry_bits.h b/opencl/source/aub_mem_dump/page_table_entry_bits.h index 0fbfeb1fc4..97d011e58f 100644 --- a/opencl/source/aub_mem_dump/page_table_entry_bits.h +++ b/opencl/source/aub_mem_dump/page_table_entry_bits.h @@ -14,5 +14,6 @@ namespace PageTableEntry { const uint32_t presentBit = 0; const uint32_t writableBit = 1; const uint32_t userSupervisorBit = 2; +const uint32_t localMemoryBit = 11; const uint64_t nonValidBits = std::numeric_limits::max(); } // namespace PageTableEntry diff --git a/opencl/source/dll/linux/devices/devices_base.inl b/opencl/source/dll/linux/devices/devices_base.inl index 5026efef16..30df96a1ac 100644 --- a/opencl/source/dll/linux/devices/devices_base.inl +++ b/opencl/source/dll/linux/devices/devices_base.inl @@ -17,6 +17,9 @@ DEVICE( ITGL_LP_1x2x16_DESK_65W_DEVICE_F0_ID, TGLLP_1x2x16, GTTYPE_GT2 ) DEVICE( ITGL_LP_1x2x16_HALO_WS_45W_DEVICE_F0_ID, TGLLP_1x2x16, GTTYPE_GT2 ) DEVICE( ITGL_LP_1x2x16_DESK_WS_65W_DEVICE_F0_ID, TGLLP_1x2x16, GTTYPE_GT2 ) #endif +#ifdef SUPPORT_DG1 +DEVICE( DEV_ID_4905, DG1_CONFIG, GTTYPE_GT2 ) +#endif #endif #ifdef SUPPORT_GEN11 diff --git a/opencl/source/gen12lp/hw_info_dg1.inl b/opencl/source/gen12lp/hw_info_dg1.inl new file mode 100644 index 0000000000..fbaec853e1 --- /dev/null +++ b/opencl/source/gen12lp/hw_info_dg1.inl @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2020 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/debug_settings/debug_settings_manager.h" +#include "shared/source/gen12lp/hw_cmds_dg1.h" +#include "shared/source/helpers/constants.h" + +#include "opencl/source/aub_mem_dump/aub_services.h" + +#include "engine_node.h" + +namespace NEO { + +const char *HwMapper::abbreviation = "dg1"; + +bool isSimulationDG1(unsigned short deviceId) { + switch (deviceId) { + case DEV_ID_4905: + return true; + } + + return false; +}; + +const PLATFORM DG1::platform = { + IGFX_DG1, + PCH_UNKNOWN, + IGFX_GEN12LP_CORE, + IGFX_GEN12LP_CORE, + PLATFORM_NONE, // default init + 0, // usDeviceID + 0, // usRevId. 0 sets the stepping to A0 + 0, // usDeviceID_PCH + 0, // usRevId_PCH + GTTYPE_UNDEFINED}; + +const RuntimeCapabilityTable DG1::capabilityTable{ + EngineDirectSubmissionInitVec{ + {aub_stream::ENGINE_RCS, {true, true}}, + {aub_stream::ENGINE_CCS, {true, true}}}, // directSubmissionEngines + {0, 0, 0, false, false, false}, // kmdNotifyProperties + MemoryConstants::max64BitAppAddress, // gpuAddressSpace + 83.333, // defaultProfilingTimerResolution + MemoryConstants::pageSize, // requiredPreemptionSurfaceSize + &isSimulationDG1, // isSimulation + PreemptionMode::ThreadGroup, // defaultPreemptionMode + aub_stream::ENGINE_CCS, // defaultEngineType + 0, // maxRenderFrequency + 30, // clVersionSupport + CmdServicesMemTraceVersion::DeviceValues::Dg1, // aubDeviceId + 1, // extraQuantityThreadsPerEU + 64, // slmSize + sizeof(DG1::GRF), // slmSize + false, // blitterOperationsSupported + true, // ftrSupportsInteger64BitAtomics + false, // ftrSupportsFP64 + false, // ftrSupports64BitMath + true, // ftrSvm + false, // ftrSupportsCoherency + false, // ftrSupportsVmeAvcTextureSampler + false, // ftrSupportsVmeAvcPreemption + false, // ftrRenderCompressedBuffers + false, // ftrRenderCompressedImages + true, // ftr64KBpages + true, // instrumentationEnabled + true, // forceStatelessCompilationFor32Bit + "lp", // platformType + true, // sourceLevelDebuggerSupported + false, // supportsVme + true, // supportCacheFlushAfterWalker + true, // supportsImages, + false, // supportsDeviceEnqueue + false, // supportsPipes + true, // supportsOcl21Features + false, // supportsOnDemandPageFaults + false, // hostPtrTrackingEnabled + true // levelZeroSupported +}; + +WorkaroundTable DG1::workaroundTable = {}; +FeatureTable DG1::featureTable = {}; + +void DG1::setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo) { + FeatureTable *featureTable = &hwInfo->featureTable; + WorkaroundTable *workaroundTable = &hwInfo->workaroundTable; + + featureTable->ftrL3IACoherency = true; + featureTable->ftrPPGTT = true; + featureTable->ftrSVM = true; + featureTable->ftrIA32eGfxPTEs = true; + featureTable->ftrStandardMipTailFormat = true; + featureTable->ftrLocalMemory = true; + + featureTable->ftrTranslationTable = true; + featureTable->ftrUserModeTranslationTable = true; + featureTable->ftrTileMappedResource = true; + featureTable->ftrEnableGuC = true; + + featureTable->ftrFbc = true; + featureTable->ftrFbc2AddressTranslation = true; + featureTable->ftrFbcBlitterTracking = true; + featureTable->ftrFbcCpuTracking = true; + featureTable->ftrTileY = true; + + featureTable->ftrAstcHdr2D = true; + featureTable->ftrAstcLdr2D = true; + + featureTable->ftr3dMidBatchPreempt = true; + featureTable->ftrGpGpuMidBatchPreempt = true; + featureTable->ftrGpGpuThreadGroupLevelPreempt = true; + featureTable->ftrPerCtxtPreemptionGranularityControl = true; + featureTable->ftrBcsInfo = maxNBitValue(1); + + workaroundTable->wa4kAlignUVOffsetNV12LinearSurface = true; + workaroundTable->waEnablePreemptionGranularityControlByUMD = true; +}; + +const HardwareInfo DG1_CONFIG::hwInfo = { + &DG1::platform, + &DG1::featureTable, + &DG1::workaroundTable, + &DG1_CONFIG::gtSystemInfo, + DG1::capabilityTable, +}; +GT_SYSTEM_INFO DG1_CONFIG::gtSystemInfo = {0}; +void DG1_CONFIG::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) { + GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo; + gtSysInfo->ThreadCount = gtSysInfo->EUCount * DG1::threadsPerEu; + gtSysInfo->SliceCount = 1; + gtSysInfo->DualSubSliceCount = 6; + gtSysInfo->L3CacheSizeInKb = 16384; + gtSysInfo->L3BankCount = 8; + gtSysInfo->MaxFillRate = 16; + gtSysInfo->TotalVsThreads = 672; + gtSysInfo->TotalHsThreads = 672; + gtSysInfo->TotalDsThreads = 672; + gtSysInfo->TotalGsThreads = 672; + gtSysInfo->TotalPsThreadsWindowerRange = 64; + gtSysInfo->CsrSizeInMb = 8; + gtSysInfo->MaxEuPerSubSlice = DG1::maxEuPerSubslice; + gtSysInfo->MaxSlicesSupported = DG1::maxSlicesSupported; + gtSysInfo->MaxSubSlicesSupported = DG1::maxSubslicesSupported; + gtSysInfo->MaxDualSubSlicesSupported = DG1::maxDualSubslicesSupported; + gtSysInfo->IsL3HashModeEnabled = false; + gtSysInfo->IsDynamicallyPopulated = false; + + gtSysInfo->CCSInfo.IsValid = true; + gtSysInfo->CCSInfo.NumberOfCCSEnabled = 1; + gtSysInfo->CCSInfo.Instances.CCSEnableMask = 0b1; + + if (setupFeatureTableAndWorkaroundTable) { + DG1::setupFeatureAndWorkaroundTable(hwInfo); + } +}; + +const HardwareInfo DG1::hwInfo = DG1_CONFIG::hwInfo; +const uint64_t DG1::defaultHardwareInfoConfig = 0x100060016; + +void setupDG1HardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig) { + if (hwInfoConfig == 0x100060016) { + DG1_CONFIG::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable); + } else if (hwInfoConfig == 0x0) { + // Default config + DG1_CONFIG::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable); + } else { + UNRECOVERABLE_IF(true); + } +} + +void (*DG1::setupHardwareInfo)(HardwareInfo *, bool, const uint64_t) = setupDG1HardwareInfoImpl; +} // namespace NEO diff --git a/opencl/source/gen12lp/hw_info_gen12lp.cpp b/opencl/source/gen12lp/hw_info_gen12lp.cpp index 5f0a73f5b0..622e6c9af8 100644 --- a/opencl/source/gen12lp/hw_info_gen12lp.cpp +++ b/opencl/source/gen12lp/hw_info_gen12lp.cpp @@ -8,6 +8,9 @@ #ifdef SUPPORT_TGLLP #include "hw_info_tgllp.inl" #endif +#ifdef SUPPORT_DG1 +#include "hw_info_dg1.inl" +#endif namespace NEO { const char *GfxFamilyMapper::name = "Gen12LP"; diff --git a/opencl/source/gen12lp/linux/hw_info_config_dg1.inl b/opencl/source/gen12lp/linux/hw_info_config_dg1.inl new file mode 100644 index 0000000000..9974de1211 --- /dev/null +++ b/opencl/source/gen12lp/linux/hw_info_config_dg1.inl @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2020 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/hw_info.h" +#include "shared/source/helpers/hw_info_config_common_helper.h" +#include "shared/source/os_interface/hw_info_config.h" + +namespace NEO { + +template <> +int HwInfoConfigHw::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) { + if (nullptr == osIface) { + return 0; + } + + GT_SYSTEM_INFO *gtSystemInfo = &hwInfo->gtSystemInfo; + gtSystemInfo->SliceCount = 1; + + HwInfoConfigCommonHelper::enableBlitterOperationsSupport(*hwInfo); + return 0; +} + +template <> +uint64_t HwInfoConfigHw::getSharedSystemMemCapabilities() { + return 0; +} + +template class HwInfoConfigHw; +} // namespace NEO diff --git a/opencl/source/gen12lp/linux/hw_info_config_gen12lp.cpp b/opencl/source/gen12lp/linux/hw_info_config_gen12lp.cpp index e7af3d10fa..05860ac289 100644 --- a/opencl/source/gen12lp/linux/hw_info_config_gen12lp.cpp +++ b/opencl/source/gen12lp/linux/hw_info_config_gen12lp.cpp @@ -11,3 +11,6 @@ #ifdef SUPPORT_TGLLP #include "hw_info_config_tgllp.inl" #endif +#ifdef SUPPORT_DG1 +#include "hw_info_config_dg1.inl" +#endif diff --git a/opencl/source/gen12lp/windows/hw_info_config_gen12lp.cpp b/opencl/source/gen12lp/windows/hw_info_config_gen12lp.cpp index 0a4386941b..57063fe7c2 100644 --- a/opencl/source/gen12lp/windows/hw_info_config_gen12lp.cpp +++ b/opencl/source/gen12lp/windows/hw_info_config_gen12lp.cpp @@ -32,5 +32,27 @@ void HwInfoConfigHw::adjustPlatformForProductFamily(HardwareI template class HwInfoConfigHw; #endif +#ifdef SUPPORT_DG1 +template <> +int HwInfoConfigHw::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) { + hwInfo->capabilityTable.ftrRenderCompressedImages = hwInfo->featureTable.ftrE2ECompression; + hwInfo->capabilityTable.ftrRenderCompressedBuffers = hwInfo->featureTable.ftrE2ECompression; + HwInfoConfigCommonHelper::enableBlitterOperationsSupport(*hwInfo); + return 0; +} +template <> +void HwInfoConfigHw::adjustPlatformForProductFamily(HardwareInfo *hwInfo) { + PLATFORM *platform = &hwInfo->platform; + platform->eRenderCoreFamily = IGFX_GEN12LP_CORE; + platform->eDisplayCoreFamily = IGFX_GEN12LP_CORE; +} + +template <> +uint64_t HwInfoConfigHw::getSharedSystemMemCapabilities() { + return 0; +} + +template class HwInfoConfigHw; +#endif } // namespace NEO diff --git a/shared/source/gen12lp/CMakeLists.txt b/shared/source/gen12lp/CMakeLists.txt index 8a2352bc80..0ed77488d0 100644 --- a/shared/source/gen12lp/CMakeLists.txt +++ b/shared/source/gen12lp/CMakeLists.txt @@ -4,9 +4,16 @@ # SPDX-License-Identifier: MIT # +if(SUPPORT_DG1) +set(SHARED_SRCS_ADDITIONAL_FILES_GEN12LP + ${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}/helpers_gen12lp_dg1.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/helpers_gen12lp.h +) +else() set(SHARED_SRCS_ADDITIONAL_FILES_GEN12LP ${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}/helpers_gen12lp.cpp ${CMAKE_CURRENT_SOURCE_DIR}/helpers_gen12lp.h ) +endif() set_property(GLOBAL PROPERTY SHARED_SRCS_ADDITIONAL_FILES_GEN12LP ${SHARED_SRCS_ADDITIONAL_FILES_GEN12LP}) \ No newline at end of file diff --git a/shared/source/gen12lp/enable_gen12lp.cpp b/shared/source/gen12lp/enable_gen12lp.cpp index 10f257c948..f312f8b2b7 100644 --- a/shared/source/gen12lp/enable_gen12lp.cpp +++ b/shared/source/gen12lp/enable_gen12lp.cpp @@ -15,5 +15,8 @@ namespace NEO { #ifdef SUPPORT_TGLLP static EnableGfxProductHw enableGfxProductHwTGLLP; #endif +#ifdef SUPPORT_DG1 +static EnableGfxProductHw enableGfxProductHwDG1; +#endif } // namespace NEO diff --git a/shared/source/gen12lp/enable_hw_info_config_gen12lp.cpp b/shared/source/gen12lp/enable_hw_info_config_gen12lp.cpp index bd7e9360e7..b9bb8805cd 100644 --- a/shared/source/gen12lp/enable_hw_info_config_gen12lp.cpp +++ b/shared/source/gen12lp/enable_hw_info_config_gen12lp.cpp @@ -13,5 +13,7 @@ namespace NEO { #ifdef SUPPORT_TGLLP static EnableProductHwInfoConfig enableTGLLP; #endif - +#ifdef SUPPORT_DG1 +static EnableProductHwInfoConfig enableDG1; +#endif } // namespace NEO diff --git a/shared/source/gen12lp/helpers_gen12lp_dg1.cpp b/shared/source/gen12lp/helpers_gen12lp_dg1.cpp new file mode 100644 index 0000000000..e66ac4ba39 --- /dev/null +++ b/shared/source/gen12lp/helpers_gen12lp_dg1.cpp @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2020 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_stream/command_stream_receiver.h" +#include "shared/source/gen12lp/helpers_gen12lp.h" + +#include "opencl/source/aub_mem_dump/page_table_entry_bits.h" +#include "opencl/source/command_stream/command_stream_receiver_simulated_common_hw.h" + +namespace NEO { +namespace Gen12LPHelpers { + +bool pipeControlWaRequired(PRODUCT_FAMILY productFamily) { + return (productFamily == IGFX_TIGERLAKE_LP) || (productFamily == IGFX_DG1); +} + +bool imagePitchAlignmentWaRequired(PRODUCT_FAMILY productFamily) { + return (productFamily == IGFX_TIGERLAKE_LP) || (productFamily == IGFX_DG1); +} + +void adjustCoherencyFlag(PRODUCT_FAMILY productFamily, bool &coherencyFlag) { + if (productFamily == IGFX_DG1) { + coherencyFlag = false; + } +} + +bool isLocalMemoryEnabled(const HardwareInfo &hwInfo) { + return hwInfo.featureTable.ftrLocalMemory; +} + +void initAdditionalGlobalMMIO(const CommandStreamReceiver &commandStreamReceiver, AubMemDump::AubStream &stream) {} + +uint64_t getPPGTTAdditionalBits(GraphicsAllocation *graphicsAllocation) { + if (graphicsAllocation && graphicsAllocation->getMemoryPool() == MemoryPool::LocalMemory) { + return BIT(PageTableEntry::localMemoryBit); + } + return 0; +} + +void adjustAubGTTData(const CommandStreamReceiver &commandStreamReceiver, AubGTTData &data) { + data.localMemory = commandStreamReceiver.isLocalMemoryEnabled(); +} + +void setAdditionalPipelineSelectFields(void *pipelineSelectCmd, + const PipelineSelectArgs &pipelineSelectArgs, + const HardwareInfo &hwInfo) {} + +bool isOffsetToSkipSetFFIDGPWARequired(const HardwareInfo &hwInfo) { + return (hwInfo.platform.usRevId == REVISION_A0); +} + +bool isForceDefaultRCSEngineWARequired(const HardwareInfo &hwInfo) { + return ((hwInfo.platform.eProductFamily == IGFX_TIGERLAKE_LP) || (hwInfo.platform.eProductFamily == IGFX_DG1) & (hwInfo.platform.usRevId == REVISION_A0)); +} + +bool isForceEmuInt32DivRemSPWARequired(const HardwareInfo &hwInfo) { + return ((hwInfo.platform.eProductFamily == IGFX_TIGERLAKE_LP) & (hwInfo.platform.usRevId == REVISION_A0)); +} + +bool is3DPipelineSelectWARequired(const HardwareInfo &hwInfo) { + return (hwInfo.platform.eProductFamily == IGFX_TIGERLAKE_LP || hwInfo.platform.eProductFamily == IGFX_DG1); +} + +} // namespace Gen12LPHelpers +} // namespace NEO diff --git a/shared/source/gen12lp/hw_cmds.h b/shared/source/gen12lp/hw_cmds.h index fa2fe256c0..b8c4cc81ab 100644 --- a/shared/source/gen12lp/hw_cmds.h +++ b/shared/source/gen12lp/hw_cmds.h @@ -9,3 +9,6 @@ #ifdef SUPPORT_TGLLP #include "hw_cmds_tgllp.h" #endif +#ifdef SUPPORT_DG1 +#include "hw_cmds_dg1.h" +#endif diff --git a/shared/source/gen12lp/hw_cmds_dg1.h b/shared/source/gen12lp/hw_cmds_dg1.h new file mode 100644 index 0000000000..98e0883a66 --- /dev/null +++ b/shared/source/gen12lp/hw_cmds_dg1.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2020 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "shared/source/gen12lp/hw_cmds_base.h" +namespace NEO { +struct DG1 : public TGLLPFamily { + static const PLATFORM platform; + static const HardwareInfo hwInfo; + static const uint64_t defaultHardwareInfoConfig; + static FeatureTable featureTable; + static WorkaroundTable workaroundTable; + static const uint32_t threadsPerEu = 7; + static const uint32_t maxEuPerSubslice = 16; + static const uint32_t maxSlicesSupported = 1; + static const uint32_t maxSubslicesSupported = 6; + static const uint32_t maxDualSubslicesSupported = 6; + static const RuntimeCapabilityTable capabilityTable; + static void (*setupHardwareInfo)(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig); + static void setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo); +}; +class DG1_CONFIG : public DG1 { + public: + static void setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable); + static const HardwareInfo hwInfo; + + private: + static GT_SYSTEM_INFO gtSystemInfo; +}; +} // namespace NEO diff --git a/shared/source/gen12lp/hw_cmds_tgllp.h b/shared/source/gen12lp/hw_cmds_tgllp.h index 9bde64e1b8..6b4cfb6fc0 100644 --- a/shared/source/gen12lp/hw_cmds_tgllp.h +++ b/shared/source/gen12lp/hw_cmds_tgllp.h @@ -19,7 +19,7 @@ struct TGLLP : public TGLLPFamily { static const uint32_t maxEuPerSubslice = 16; static const uint32_t maxSlicesSupported = 1; static const uint32_t maxSubslicesSupported = 6; - static const uint32_t maxDualSubslicesSupported = 12; + static const uint32_t maxDualSubslicesSupported = 6; static const RuntimeCapabilityTable capabilityTable; static void (*setupHardwareInfo)(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig); static void setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo); diff --git a/shared/source/gen12lp/hw_info.h b/shared/source/gen12lp/hw_info.h index f5e860e82b..7fc48e1449 100644 --- a/shared/source/gen12lp/hw_info.h +++ b/shared/source/gen12lp/hw_info.h @@ -9,3 +9,6 @@ #ifdef SUPPORT_TGLLP #include "hw_info_tgllp.h" #endif +#ifdef SUPPORT_DG1 +#include "hw_info_dg1.h" +#endif diff --git a/shared/source/gen12lp/hw_info_dg1.h b/shared/source/gen12lp/hw_info_dg1.h new file mode 100644 index 0000000000..3abb2505cb --- /dev/null +++ b/shared/source/gen12lp/hw_info_dg1.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2020 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "hw_info_gen12lp.h" + +namespace NEO { + +struct DG1; + +template <> +struct HwMapper { + enum { gfxFamily = IGFX_GEN12LP_CORE }; + + static const char *abbreviation; + using GfxFamily = GfxFamilyMapper(gfxFamily)>::GfxFamily; + using GfxProduct = DG1; +}; +} // namespace NEO