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https://github.com/intel/compute-runtime.git
synced 2026-01-08 14:02:58 +08:00
Refactor HardwareParse::getSurfaceState() to return CPU memory
- if SSH indirectHeap is passed, use CPU address instead of GPU address programed in SBA command Change-Id: Id2c8973db0dfe2d9562ee835a27c4d3c28ea3351
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sys_ocldev
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eb65521057
commit
3c47c418a9
@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -152,7 +152,7 @@ HWTEST_F(EnqueueCopyBufferToImageTest, surfaceState) {
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enqueueCopyBufferToImage<FamilyType>();
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const auto &surfaceState = getSurfaceState<FamilyType>(1);
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const auto &surfaceState = getSurfaceState<FamilyType>(&pCmdQ->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0), 1);
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const auto &imageDesc = dstImage->getImageDesc();
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// EnqueueReadImage uses multi-byte copies depending on per-pixel-size-in-bytes
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EXPECT_EQ(imageDesc.image_width, surfaceState.getWidth());
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -156,7 +156,7 @@ HWTEST_F(EnqueueCopyImageTest, surfaceState) {
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enqueueCopyImage<FamilyType>();
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for (uint32_t i = 0; i < 2; ++i) {
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const auto &surfaceState = getSurfaceState<FamilyType>(i);
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const auto &surfaceState = getSurfaceState<FamilyType>(&pCmdQ->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0), i);
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const auto &imageDesc = dstImage->getImageDesc();
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EXPECT_EQ(imageDesc.image_width, surfaceState.getWidth());
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EXPECT_EQ(imageDesc.image_height, surfaceState.getHeight());
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@@ -174,10 +174,10 @@ HWTEST_F(EnqueueCopyImageTest, surfaceState) {
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EXPECT_EQ(RENDER_SURFACE_STATE::SURFACE_VERTICAL_ALIGNMENT_VALIGN_4, surfaceState.getSurfaceVerticalAlignment());
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}
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const auto &srcSurfaceState = getSurfaceState<FamilyType>(0);
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const auto &srcSurfaceState = getSurfaceState<FamilyType>(&pCmdQ->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0), 0);
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EXPECT_EQ(reinterpret_cast<uint64_t>(srcImage->getCpuAddress()), srcSurfaceState.getSurfaceBaseAddress());
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const auto &dstSurfaceState = getSurfaceState<FamilyType>(1);
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const auto &dstSurfaceState = getSurfaceState<FamilyType>(&pCmdQ->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0), 1);
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EXPECT_EQ(reinterpret_cast<uint64_t>(dstImage->getCpuAddress()), dstSurfaceState.getSurfaceBaseAddress());
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}
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -153,7 +153,7 @@ HWTEST_F(EnqueueCopyImageToBufferTest, surfaceState) {
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enqueueCopyImageToBuffer<FamilyType>();
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const auto &surfaceState = getSurfaceState<FamilyType>(0);
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const auto &surfaceState = getSurfaceState<FamilyType>(&pCmdQ->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0), 0);
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const auto &imageDesc = srcImage->getImageDesc();
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// EnqueueReadImage uses multi-byte copies depending on per-pixel-size-in-bytes
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EXPECT_EQ(imageDesc.image_width, surfaceState.getWidth());
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@@ -163,7 +163,7 @@ HWTEST_F(EnqueueFillImageTest, surfaceState) {
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enqueueFillImage<FamilyType>();
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const auto &surfaceState = getSurfaceState<FamilyType>(0);
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const auto &surfaceState = getSurfaceState<FamilyType>(&pCmdQ->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0), 0);
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const auto &imageDesc = image->getImageDesc();
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EXPECT_EQ(imageDesc.image_width, surfaceState.getWidth());
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EXPECT_EQ(imageDesc.image_height, surfaceState.getHeight());
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@@ -172,7 +172,7 @@ HWTEST_F(EnqueueFillImageTest, surfaceState) {
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EXPECT_EQ(RENDER_SURFACE_STATE::SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_4, surfaceState.getSurfaceHorizontalAlignment());
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EXPECT_EQ(RENDER_SURFACE_STATE::SURFACE_VERTICAL_ALIGNMENT_VALIGN_4, surfaceState.getSurfaceVerticalAlignment());
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const auto &srcSurfaceState = getSurfaceState<FamilyType>(0);
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const auto &srcSurfaceState = getSurfaceState<FamilyType>(&pCmdQ->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0), 0);
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EXPECT_EQ(reinterpret_cast<uint64_t>(image->getCpuAddress()), srcSurfaceState.getSurfaceBaseAddress());
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}
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@@ -166,7 +166,7 @@ HWTEST_F(EnqueueReadImageTest, surfaceState) {
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// BufferToImage kernel uses BTI=1 for destSurface
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uint32_t bindingTableIndex = 0;
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const auto &surfaceState = getSurfaceState<FamilyType>(bindingTableIndex);
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const auto &surfaceState = getSurfaceState<FamilyType>(&pCmdQ->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0), bindingTableIndex);
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// EnqueueReadImage uses multi-byte copies depending on per-pixel-size-in-bytes
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const auto &imageDesc = srcImage->getImageDesc();
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -166,7 +166,7 @@ HWTEST_F(EnqueueWriteImageTest, surfaceState) {
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// BufferToImage kernel uses BTI=1 for destSurface
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uint32_t bindingTableIndex = 1;
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const auto &surfaceState = getSurfaceState<FamilyType>(bindingTableIndex);
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const auto &surfaceState = getSurfaceState<FamilyType>(&pCmdQ->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0), bindingTableIndex);
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// EnqueueWriteImage uses multi-byte copies depending on per-pixel-size-in-bytes
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const auto &imageDesc = dstImage->getImageDesc();
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@@ -98,7 +98,7 @@ struct HardwareParse {
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}
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template <typename FamilyType>
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const typename FamilyType::RENDER_SURFACE_STATE &getSurfaceState(uint32_t index) {
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const typename FamilyType::RENDER_SURFACE_STATE &getSurfaceState(IndirectHeap *ssh, uint32_t index) {
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typedef typename FamilyType::BINDING_TABLE_STATE BINDING_TABLE_STATE;
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typedef typename FamilyType::INTERFACE_DESCRIPTOR_DATA INTERFACE_DESCRIPTOR_DATA;
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typedef typename FamilyType::RENDER_SURFACE_STATE RENDER_SURFACE_STATE;
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@@ -108,6 +108,9 @@ struct HardwareParse {
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auto cmdSBA = (STATE_BASE_ADDRESS *)cmdStateBaseAddress;
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auto surfaceStateHeap = cmdSBA->getSurfaceStateBaseAddress();
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if (ssh && (ssh->getHeapGpuBase() == surfaceStateHeap)) {
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surfaceStateHeap = reinterpret_cast<uint64_t>(ssh->getCpuBase());
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}
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EXPECT_NE(0u, surfaceStateHeap);
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auto bindingTablePointer = interfaceDescriptorData.getBindingTablePointer();
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@@ -103,7 +103,7 @@ HWTEST_F(EnqueueBufferWindowsTest, givenMisalignedHostPtrWhenEnqueueReadBufferCa
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parseCommands<FamilyType>(*cmdQ);
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if (hwInfo->capabilityTable.gpuAddressSpace == MemoryConstants::max48BitAddress) {
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const auto &surfaceStateDst = getSurfaceState<FamilyType>(1);
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const auto &surfaceStateDst = getSurfaceState<FamilyType>(&cmdQ->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0), 1);
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if (kernel->getKernelInfo().kernelArgInfo[1].kernelArgPatchInfoVector[0].size == sizeof(uint64_t)) {
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auto pKernelArg = (uint64_t *)(kernel->getCrossThreadData() +
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