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Move os_interface files to core

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Change-Id: Ie708a944130884248499091854ebc483953fa828
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
This commit is contained in:
Mateusz Hoppe
2020-01-21 15:24:52 +01:00
committed by sys_ocldev
parent 0b141ed4ea
commit 3c89cfc753
109 changed files with 184 additions and 187 deletions
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11
runtime/os_interface/linux/CMakeLists.txt
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@@ -19,18 +19,11 @@ set(RUNTIME_SRCS_OS_INTERFACE_LINUX
${CMAKE_CURRENT_SOURCE_DIR}/drm_command_stream.h
${CMAKE_CURRENT_SOURCE_DIR}/drm_command_stream.inl
${CMAKE_CURRENT_SOURCE_DIR}/drm_command_stream_bdw_plus.inl
${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}/drm_engine_mapper.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_engine_mapper.h
${CMAKE_CURRENT_SOURCE_DIR}/drm_gem_close_worker.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_gem_close_worker.h
${CMAKE_CURRENT_SOURCE_DIR}/drm_memory_manager.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_memory_manager.h
${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}/drm_memory_manager_allocate_in_device_pool.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_neo.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_neo.h
${CMAKE_CURRENT_SOURCE_DIR}/drm_neo_create.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_null_device.h
${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}/drm_query.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_memory_operations_handler.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_memory_operations_handler.h
${CMAKE_CURRENT_SOURCE_DIR}/hw_info_config.cpp
@@ -38,11 +31,7 @@ set(RUNTIME_SRCS_OS_INTERFACE_LINUX
${CMAKE_CURRENT_SOURCE_DIR}/ocl_reg_path.cpp
${CMAKE_CURRENT_SOURCE_DIR}/os_context_linux.cpp
${CMAKE_CURRENT_SOURCE_DIR}/os_context_linux.h
${CMAKE_CURRENT_SOURCE_DIR}/os_interface.cpp
${CMAKE_CURRENT_SOURCE_DIR}/os_interface.h
${CMAKE_CURRENT_SOURCE_DIR}/os_metrics_library.cpp
${CMAKE_CURRENT_SOURCE_DIR}/os_time_linux.cpp
${CMAKE_CURRENT_SOURCE_DIR}/os_time_linux.h
${CMAKE_CURRENT_SOURCE_DIR}/performance_counters_linux.cpp
${CMAKE_CURRENT_SOURCE_DIR}/performance_counters_linux.h
)

4
runtime/os_interface/linux/device_factory_linux.cpp
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@@ -8,12 +8,12 @@
#include "core/debug_settings/debug_settings_manager.h"
#include "core/execution_environment/root_device_environment.h"
#include "core/helpers/hw_info.h"
#include "core/os_interface/linux/drm_neo.h"
#include "core/os_interface/linux/os_interface.h"
#include "runtime/device/device.h"
#include "runtime/os_interface/device_factory.h"
#include "runtime/os_interface/hw_info_config.h"
#include "runtime/os_interface/linux/drm_memory_operations_handler.h"
#include "runtime/os_interface/linux/drm_neo.h"
#include "runtime/os_interface/linux/os_interface.h"
#include "drm/i915_drm.h"

6
runtime/os_interface/linux/drm_buffer_object.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2019 Intel Corporation
* Copyright (C) 2017-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -9,10 +9,10 @@
#include "core/helpers/aligned_memory.h"
#include "core/helpers/debug_helpers.h"
#include "core/os_interface/linux/drm_neo.h"
#include "core/os_interface/linux/os_time_linux.h"
#include "core/utilities/stackvec.h"
#include "runtime/os_interface/linux/drm_memory_manager.h"
#include "runtime/os_interface/linux/drm_neo.h"
#include "runtime/os_interface/linux/os_time_linux.h"
#include "drm/i915_drm.h"

6
runtime/os_interface/linux/drm_command_stream.inl
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@@ -11,17 +11,17 @@
#include "core/helpers/aligned_memory.h"
#include "core/helpers/preamble.h"
#include "core/memory_manager/residency.h"
#include "core/os_interface/linux/drm_engine_mapper.h"
#include "core/os_interface/linux/drm_neo.h"
#include "core/os_interface/linux/os_interface.h"
#include "runtime/execution_environment/execution_environment.h"
#include "runtime/helpers/flush_stamp.h"
#include "runtime/mem_obj/buffer.h"
#include "runtime/os_interface/linux/drm_allocation.h"
#include "runtime/os_interface/linux/drm_buffer_object.h"
#include "runtime/os_interface/linux/drm_command_stream.h"
#include "runtime/os_interface/linux/drm_engine_mapper.h"
#include "runtime/os_interface/linux/drm_memory_manager.h"
#include "runtime/os_interface/linux/drm_neo.h"
#include "runtime/os_interface/linux/os_context_linux.h"
#include "runtime/os_interface/linux/os_interface.h"
#include "runtime/platform/platform.h"
#include <cstdlib>

26
runtime/os_interface/linux/drm_engine_mapper.cpp
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@@ -1,26 +0,0 @@
/*
* Copyright (C) 2018-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/os_interface/linux/drm_engine_mapper.h"
#include "core/helpers/debug_helpers.h"
#include "drm/i915_drm.h"
namespace NEO {
unsigned int DrmEngineMapper::engineNodeMap(aub_stream::EngineType engineType) {
if (aub_stream::ENGINE_RCS == engineType) {
return I915_EXEC_RENDER;
} else if (aub_stream::ENGINE_BCS == engineType) {
return I915_EXEC_BLT;
} else if (aub_stream::ENGINE_CCS == engineType) {
return I915_EXEC_COMPUTE;
}
UNRECOVERABLE_IF(true);
}
} // namespace NEO

19
runtime/os_interface/linux/drm_engine_mapper.h
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@@ -1,19 +0,0 @@
/*
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "engine_node.h"
namespace NEO {
class DrmEngineMapper {
public:
static unsigned int engineNodeMap(aub_stream::EngineType engineType);
};
} // namespace NEO

2
runtime/os_interface/linux/drm_memory_manager.cpp
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@@ -16,13 +16,13 @@
#include "core/helpers/ptr_math.h"
#include "core/memory_manager/host_ptr_manager.h"
#include "core/memory_manager/residency.h"
#include "core/os_interface/linux/os_interface.h"
#include "runtime/command_stream/command_stream_receiver.h"
#include "runtime/device/device.h"
#include "runtime/execution_environment/execution_environment.h"
#include "runtime/helpers/surface_formats.h"
#include "runtime/os_interface/linux/allocator_helper.h"
#include "runtime/os_interface/linux/os_context_linux.h"
#include "runtime/os_interface/linux/os_interface.h"
#include "drm/i915_drm.h"

2
runtime/os_interface/linux/drm_memory_manager.h
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@@ -6,10 +6,10 @@
*/
#pragma once
#include "core/os_interface/linux/drm_neo.h"
#include "runtime/memory_manager/memory_manager.h"
#include "runtime/os_interface/linux/drm_allocation.h"
#include "runtime/os_interface/linux/drm_buffer_object.h"
#include "runtime/os_interface/linux/drm_neo.h"
#include "drm_gem_close_worker.h"

257
runtime/os_interface/linux/drm_neo.cpp
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@@ -1,257 +0,0 @@
/*
* Copyright (C) 2017-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "drm_neo.h"
#include "core/debug_settings/debug_settings_manager.h"
#include "core/helpers/debug_helpers.h"
#include "core/helpers/hw_info.h"
#include "core/memory_manager/memory_constants.h"
#include "core/os_interface/linux/os_inc.h"
#include "core/utilities/directory.h"
#include <cstdio>
#include <cstring>
#include <fstream>
namespace NEO {
const char *Drm::sysFsDefaultGpuPath = "/drm/card0";
const char *Drm::maxGpuFrequencyFile = "/gt_max_freq_mhz";
const char *Drm::configFileName = "/config";
int Drm::ioctl(unsigned long request, void *arg) {
int ret;
SYSTEM_ENTER();
do {
ret = ::ioctl(fd, request, arg);
} while (ret == -1 && (errno == EINTR || errno == EAGAIN));
SYSTEM_LEAVE(request);
return ret;
}
int Drm::getParamIoctl(int param, int *dstValue) {
drm_i915_getparam_t getParam = {};
getParam.param = param;
getParam.value = dstValue;
return ioctl(DRM_IOCTL_I915_GETPARAM, &getParam);
}
int Drm::getDeviceID(int &devId) {
return getParamIoctl(I915_PARAM_CHIPSET_ID, &devId);
}
int Drm::getDeviceRevID(int &revId) {
return getParamIoctl(I915_PARAM_REVISION, &revId);
}
int Drm::getExecSoftPin(int &execSoftPin) {
return getParamIoctl(I915_PARAM_HAS_EXEC_SOFTPIN, &execSoftPin);
}
int Drm::enableTurboBoost() {
drm_i915_gem_context_param contextParam = {};
contextParam.param = I915_CONTEXT_PRIVATE_PARAM_BOOST;
contextParam.value = 1;
return ioctl(DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &contextParam);
}
int Drm::getEnabledPooledEu(int &enabled) {
return getParamIoctl(I915_PARAM_HAS_POOLED_EU, &enabled);
}
int Drm::getMaxGpuFrequency(int &maxGpuFrequency) {
maxGpuFrequency = 0;
int deviceID = 0;
int ret = getDeviceID(deviceID);
if (ret != 0) {
return ret;
}
std::string clockSysFsPath = getSysFsPciPath(deviceID);
if (clockSysFsPath.size() == 0) {
return 0;
}
clockSysFsPath += sysFsDefaultGpuPath;
clockSysFsPath += maxGpuFrequencyFile;
std::ifstream ifs(clockSysFsPath.c_str(), std::ifstream::in);
if (ifs.fail()) {
return 0;
}
ifs >> maxGpuFrequency;
ifs.close();
return 0;
}
std::string Drm::getSysFsPciPath(int deviceID) {
std::string nullPath;
std::string sysFsPciDirectory = Os::sysFsPciPath;
std::vector<std::string> files = Directory::getFiles(sysFsPciDirectory);
for (std::vector<std::string>::iterator file = files.begin(); file != files.end(); ++file) {
PCIConfig config = {};
std::string configPath = *file + configFileName;
std::string sysfsPath = *file;
std::ifstream configFile(configPath, std::ifstream::binary);
if (configFile.is_open()) {
configFile.read(reinterpret_cast<char *>(&config), sizeof(config));
if (!configFile.good() || (config.DeviceID != deviceID)) {
configFile.close();
continue;
}
return sysfsPath;
}
}
return nullPath;
}
int Drm::queryGttSize(uint64_t &gttSizeOutput) {
drm_i915_gem_context_param contextParam = {0};
contextParam.param = I915_CONTEXT_PARAM_GTT_SIZE;
int ret = ioctl(DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &contextParam);
if (ret == 0) {
gttSizeOutput = contextParam.value;
}
return ret;
}
void Drm::checkPreemptionSupport() {
int value = 0;
auto ret = getParamIoctl(I915_PARAM_HAS_SCHEDULER, &value);
preemptionSupported = ((0 == ret) && (value & I915_SCHEDULER_CAP_PREEMPTION));
}
void Drm::checkQueueSliceSupport() {
sliceCountChangeSupported = getQueueSliceCount(&sseu) == 0 ? true : false;
}
void Drm::setLowPriorityContextParam(uint32_t drmContextId) {
drm_i915_gem_context_param gcp = {};
gcp.ctx_id = drmContextId;
gcp.param = I915_CONTEXT_PARAM_PRIORITY;
gcp.value = -1023;
auto retVal = ioctl(DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &gcp);
UNRECOVERABLE_IF(retVal != 0);
}
int Drm::getQueueSliceCount(drm_i915_gem_context_param_sseu *sseu) {
drm_i915_gem_context_param contextParam = {};
contextParam.param = I915_CONTEXT_PARAM_SSEU;
sseu->engine.engine_class = I915_ENGINE_CLASS_RENDER;
sseu->engine.engine_instance = I915_EXEC_DEFAULT;
contextParam.value = reinterpret_cast<uint64_t>(sseu);
contextParam.size = sizeof(struct drm_i915_gem_context_param_sseu);
return ioctl(DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &contextParam);
}
uint64_t Drm::getSliceMask(uint64_t sliceCount) {
return maxNBitValue(sliceCount);
}
bool Drm::setQueueSliceCount(uint64_t sliceCount) {
if (sliceCountChangeSupported) {
drm_i915_gem_context_param contextParam = {};
sseu.slice_mask = getSliceMask(sliceCount);
contextParam.param = I915_CONTEXT_PARAM_SSEU;
contextParam.ctx_id = 0;
contextParam.value = reinterpret_cast<uint64_t>(&sseu);
contextParam.size = sizeof(struct drm_i915_gem_context_param_sseu);
int retVal = ioctl(DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &contextParam);
if (retVal == 0) {
return true;
}
}
return false;
}
void Drm::checkNonPersistentContextsSupport() {
drm_i915_gem_context_param contextParam = {};
contextParam.param = I915_CONTEXT_PARAM_PERSISTENCE;
auto retVal = ioctl(DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &contextParam);
if (retVal == 0 && contextParam.value == 1) {
nonPersistentContextsSupported = true;
} else {
nonPersistentContextsSupported = false;
}
}
void Drm::setNonPersistentContext(uint32_t drmContextId) {
drm_i915_gem_context_param contextParam = {};
contextParam.ctx_id = drmContextId;
contextParam.param = I915_CONTEXT_PARAM_PERSISTENCE;
auto retVal = ioctl(DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &contextParam);
UNRECOVERABLE_IF(retVal != 0);
}
uint32_t Drm::createDrmContext() {
drm_i915_gem_context_create gcc = {};
auto retVal = ioctl(DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &gcc);
UNRECOVERABLE_IF(retVal != 0);
return gcc.ctx_id;
}
void Drm::destroyDrmContext(uint32_t drmContextId) {
drm_i915_gem_context_destroy destroy = {};
destroy.ctx_id = drmContextId;
auto retVal = ioctl(DRM_IOCTL_I915_GEM_CONTEXT_DESTROY, &destroy);
UNRECOVERABLE_IF(retVal != 0);
}
int Drm::getEuTotal(int &euTotal) {
return getParamIoctl(I915_PARAM_EU_TOTAL, &euTotal);
}
int Drm::getSubsliceTotal(int &subsliceTotal) {
return getParamIoctl(I915_PARAM_SUBSLICE_TOTAL, &subsliceTotal);
}
int Drm::getMinEuInPool(int &minEUinPool) {
return getParamIoctl(I915_PARAM_MIN_EU_IN_POOL, &minEUinPool);
}
int Drm::getErrno() {
return errno;
}
int Drm::setupHardwareInfo(DeviceDescriptor *device, bool setupFeatureTableAndWorkaroundTable) {
HardwareInfo *hwInfo = const_cast<HardwareInfo *>(device->pHwInfo);
int ret;
int euTotal;
int subsliceTotal;
ret = getEuTotal(euTotal);
if (ret != 0) {
printDebugString(DebugManager.flags.PrintDebugMessages.get(), stderr, "%s", "FATAL: Cannot query EU total parameter!\n");
return ret;
}
ret = getSubsliceTotal(subsliceTotal);
if (ret != 0) {
printDebugString(DebugManager.flags.PrintDebugMessages.get(), stderr, "%s", "FATAL: Cannot query subslice total parameter!\n");
return ret;
}
hwInfo->gtSystemInfo.EUCount = static_cast<uint32_t>(euTotal);
hwInfo->gtSystemInfo.SubSliceCount = static_cast<uint32_t>(subsliceTotal);
device->setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
return 0;
}
} // namespace NEO

151
runtime/os_interface/linux/drm_neo.h
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@@ -1,151 +0,0 @@
/*
* Copyright (C) 2017-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "core/helpers/basic_math.h"
#include "core/os_interface/linux/engine_info.h"
#include "core/os_interface/linux/memory_info.h"
#include "core/utilities/api_intercept.h"
#include "drm/i915_drm.h"
#include "engine_node.h"
#include "igfxfmid.h"
#include <cerrno>
#include <fcntl.h>
#include <memory>
#include <string>
#include <sys/ioctl.h>
#include <unistd.h>
struct GT_SYSTEM_INFO;
namespace NEO {
#define I915_CONTEXT_PRIVATE_PARAM_BOOST 0x80000000
class DeviceFactory;
struct HardwareInfo;
struct DeviceDescriptor { // NOLINT(clang-analyzer-optin.performance.Padding)
unsigned short deviceId;
const HardwareInfo *pHwInfo;
void (*setupHardwareInfo)(HardwareInfo *, bool);
GTTYPE eGtType;
};
extern const DeviceDescriptor deviceDescriptorTable[];
class Drm {
friend DeviceFactory;
public:
static Drm *get(int32_t deviceOrdinal);
virtual ~Drm();
virtual int ioctl(unsigned long request, void *arg);
int getDeviceID(int &devId);
int getDeviceRevID(int &revId);
int getExecSoftPin(int &execSoftPin);
int enableTurboBoost();
int getEuTotal(int &euTotal);
int getSubsliceTotal(int &subsliceTotal);
int getMaxGpuFrequency(int &maxGpuFrequency);
int getEnabledPooledEu(int &enabled);
int getMinEuInPool(int &minEUinPool);
int queryGttSize(uint64_t &gttSizeOutput);
bool isPreemptionSupported() const { return preemptionSupported; }
MOCKABLE_VIRTUAL void checkPreemptionSupport();
int getFileDescriptor() const { return fd; }
uint32_t createDrmContext();
void destroyDrmContext(uint32_t drmContextId);
void setLowPriorityContextParam(uint32_t drmContextId);
unsigned int bindDrmContext(uint32_t drmContextId, uint32_t deviceIndex, aub_stream::EngineType engineType);
void setGtType(GTTYPE eGtType) { this->eGtType = eGtType; }
GTTYPE getGtType() const { return this->eGtType; }
MOCKABLE_VIRTUAL int getErrno();
bool setQueueSliceCount(uint64_t sliceCount);
void checkQueueSliceSupport();
uint64_t getSliceMask(uint64_t sliceCount);
bool queryEngineInfo();
bool queryMemoryInfo();
int setupHardwareInfo(DeviceDescriptor *, bool);
bool areNonPersistentContextsSupported() const { return nonPersistentContextsSupported; }
void checkNonPersistentContextsSupport();
void setNonPersistentContext(uint32_t drmContextId);
MemoryInfo *getMemoryInfo() const {
return memoryInfo.get();
}
static bool (*pIsi915Version)(int fd);
static bool isi915Version(int fd);
static int (*pClose)(int fd);
protected:
int getQueueSliceCount(drm_i915_gem_context_param_sseu *sseu);
bool sliceCountChangeSupported = false;
drm_i915_gem_context_param_sseu sseu{};
bool preemptionSupported = false;
bool nonPersistentContextsSupported = false;
int fd;
int deviceId = 0;
int revisionId = 0;
GTTYPE eGtType = GTTYPE_UNDEFINED;
Drm(int fd) : fd(fd) {}
std::unique_ptr<EngineInfo> engineInfo;
std::unique_ptr<MemoryInfo> memoryInfo;
static int getDeviceFd(const int devType);
static int openDevice();
static Drm *create(int32_t deviceOrdinal);
static void closeDevice(int32_t deviceOrdinal);
std::string getSysFsPciPath(int deviceID);
void *query(uint32_t queryId);
#pragma pack(1)
struct PCIConfig {
uint16_t VendorID;
uint16_t DeviceID;
uint16_t Command;
uint16_t Status;
uint8_t Revision;
uint8_t ProgIF;
uint8_t Subclass;
uint8_t ClassCode;
uint8_t cacheLineSize;
uint8_t LatencyTimer;
uint8_t HeaderType;
uint8_t BIST;
uint32_t BAR0[6];
uint32_t CardbusCISPointer;
uint16_t SubsystemVendorID;
uint16_t SubsystemDeviceID;
uint32_t ROM;
uint8_t Capabilities;
uint8_t Reserved[7];
uint8_t InterruptLine;
uint8_t InterruptPIN;
uint8_t MinGrant;
uint8_t MaxLatency;
};
#pragma pack()
static const char *sysFsDefaultGpuPath;
static const char *maxGpuFrequencyFile;
static const char *configFileName;
private:
int getParamIoctl(int param, int *dstValue);
};
} // namespace NEO

25
runtime/os_interface/linux/drm_neo_create.cpp
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@@ -1,25 +0,0 @@
/*
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/os_interface/linux/drm_neo.h"
namespace NEO {
Drm::~Drm() = default;
Drm *Drm::get(int32_t deviceOrdinal) {
return nullptr;
}
Drm *Drm::create(int32_t deviceOrdinal) {
return nullptr;
}
void Drm::closeDevice(int32_t deviceOrdinal) {
return;
}
} // namespace NEO

48
runtime/os_interface/linux/drm_null_device.h
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@@ -1,48 +0,0 @@
/*
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "runtime/os_interface/linux/drm_neo.h"
#include "runtime/os_interface/linux/os_time_linux.h"
#include "drm/i915_drm.h"
#include <cstdio>
namespace NEO {
class DrmNullDevice : public Drm {
friend Drm;
friend DeviceFactory;
public:
int ioctl(unsigned long request, void *arg) override {
if (request == DRM_IOCTL_I915_GETPARAM) {
return Drm::ioctl(request, arg);
} else if (request == DRM_IOCTL_I915_REG_READ) {
struct drm_i915_reg_read *regArg = static_cast<struct drm_i915_reg_read *>(arg);
// Handle only 36b timestamp
if (regArg->offset == (TIMESTAMP_LOW_REG | 1)) {
gpuTimestamp += 1000;
regArg->val = gpuTimestamp & 0x0000000FFFFFFFFF;
} else if (regArg->offset == TIMESTAMP_LOW_REG || regArg->offset == TIMESTAMP_HIGH_REG) {
return -1;
}
return 0;
} else {
return 0;
}
}
protected:
DrmNullDevice(int fd) : Drm(fd), gpuTimestamp(0){};
uint64_t gpuTimestamp;
};
} // namespace NEO

30
runtime/os_interface/linux/drm_query.cpp
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@@ -1,30 +0,0 @@
/*
* Copyright (C) 2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/os_interface/linux/drm_engine_mapper.h"
#include "drm_neo.h"
namespace NEO {
void *Drm::query(uint32_t queryId) {
return nullptr;
}
bool Drm::queryEngineInfo() {
return true;
}
bool Drm::queryMemoryInfo() {
return true;
}
unsigned int Drm::bindDrmContext(uint32_t drmContextId, uint32_t deviceIndex, aub_stream::EngineType engineType) {
return DrmEngineMapper::engineNodeMap(engineType);
}
} // namespace NEO

6
runtime/os_interface/linux/hw_info_config.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2019 Intel Corporation
* Copyright (C) 2017-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -13,9 +13,9 @@
#include "core/helpers/hw_helper.h"
#include "core/helpers/hw_info.h"
#include "core/memory_manager/memory_constants.h"
#include "core/os_interface/linux/drm_neo.h"
#include "core/os_interface/linux/os_interface.h"
#include "core/utilities/cpu_info.h"
#include "runtime/os_interface/linux/drm_neo.h"
#include "runtime/os_interface/linux/os_interface.h"
#include "instrumentation.h"

4
runtime/os_interface/linux/os_context_linux.cpp
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@@ -7,9 +7,9 @@
#include "runtime/os_interface/linux/os_context_linux.h"
#include "core/os_interface/linux/drm_neo.h"
#include "core/os_interface/linux/os_interface.h"
#include "core/os_interface/os_context.h"
#include "runtime/os_interface/linux/drm_neo.h"
#include "runtime/os_interface/linux/os_interface.h"
namespace NEO {

32
runtime/os_interface/linux/os_interface.cpp
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@@ -1,32 +0,0 @@
/*
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/os_interface/linux/os_interface.h"
namespace NEO {
bool OSInterface::osEnabled64kbPages = false;
OSInterface::OSInterface() {
osInterfaceImpl = new OSInterfaceImpl();
}
OSInterface::~OSInterface() {
delete osInterfaceImpl;
}
bool OSInterface::are64kbPagesEnabled() {
return osEnabled64kbPages;
}
uint32_t OSInterface::getDeviceHandle() const {
return 0;
}
void OSInterface::setGmmInputArgs(void *args) {}
} // namespace NEO

29
runtime/os_interface/linux/os_interface.h
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@@ -1,29 +0,0 @@
/*
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "runtime/os_interface/os_interface.h"
namespace NEO {
class Drm;
class OSInterface::OSInterfaceImpl {
public:
OSInterfaceImpl() {
drm = nullptr;
}
Drm *getDrm() const {
return drm;
}
void setDrm(Drm *drm) {
this->drm = drm;
}
protected:
Drm *drm;
};
} // namespace NEO

172
runtime/os_interface/linux/os_time_linux.cpp
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@@ -1,172 +0,0 @@
/*
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "runtime/os_interface/linux/os_time_linux.h"
#include "runtime/os_interface/linux/drm_neo.h"
#include "runtime/os_interface/linux/os_interface.h"
#include "drm/i915_drm.h"
#include <time.h>
namespace NEO {
OSTimeLinux::OSTimeLinux(OSInterface *osInterface) {
this->osInterface = osInterface;
resolutionFunc = &clock_getres;
getTimeFunc = &clock_gettime;
if (osInterface) {
pDrm = osInterface->get()->getDrm();
} else {
pDrm = Drm::get(0);
}
timestampTypeDetect();
}
OSTimeLinux::~OSTimeLinux(){};
void OSTimeLinux::timestampTypeDetect() {
struct drm_i915_reg_read reg = {};
int err;
if (pDrm == nullptr)
return;
reg.offset = (TIMESTAMP_LOW_REG | 1);
err = pDrm->ioctl(DRM_IOCTL_I915_REG_READ, &reg);
if (err) {
reg.offset = TIMESTAMP_HIGH_REG;
err = pDrm->ioctl(DRM_IOCTL_I915_REG_READ, &reg);
if (err) {
getGpuTime = &OSTimeLinux::getGpuTime32;
timestampSizeInBits = OCLRT_NUM_TIMESTAMP_BITS_FALLBACK;
} else {
getGpuTime = &OSTimeLinux::getGpuTimeSplitted;
timestampSizeInBits = OCLRT_NUM_TIMESTAMP_BITS;
}
} else {
getGpuTime = &OSTimeLinux::getGpuTime36;
timestampSizeInBits = OCLRT_NUM_TIMESTAMP_BITS;
}
}
bool OSTimeLinux::getCpuTime(uint64_t *timestamp) {
struct timespec ts;
if (getTimeFunc(CLOCK_MONOTONIC_RAW, &ts)) {
return false;
}
*timestamp = (uint64_t)ts.tv_sec * NSEC_PER_SEC + ts.tv_nsec;
return true;
}
bool OSTimeLinux::getGpuTime32(uint64_t *timestamp) {
struct drm_i915_reg_read reg = {};
reg.offset = TIMESTAMP_LOW_REG;
if (pDrm->ioctl(DRM_IOCTL_I915_REG_READ, &reg)) {
return false;
}
*timestamp = reg.val >> 32;
return true;
}
bool OSTimeLinux::getGpuTime36(uint64_t *timestamp) {
struct drm_i915_reg_read reg = {};
reg.offset = TIMESTAMP_LOW_REG | 1;
if (pDrm->ioctl(DRM_IOCTL_I915_REG_READ, &reg)) {
return false;
}
*timestamp = reg.val;
return true;
}
bool OSTimeLinux::getGpuTimeSplitted(uint64_t *timestamp) {
struct drm_i915_reg_read reg_hi = {};
struct drm_i915_reg_read reg_lo = {};
uint64_t tmp_hi;
int err = 0, loop = 3;
reg_hi.offset = TIMESTAMP_HIGH_REG;
reg_lo.offset = TIMESTAMP_LOW_REG;
err += pDrm->ioctl(DRM_IOCTL_I915_REG_READ, &reg_hi);
do {
tmp_hi = reg_hi.val;
err += pDrm->ioctl(DRM_IOCTL_I915_REG_READ, &reg_lo);
err += pDrm->ioctl(DRM_IOCTL_I915_REG_READ, &reg_hi);
} while (err == 0 && reg_hi.val != tmp_hi && --loop);
if (err) {
return false;
}
*timestamp = reg_lo.val | (reg_hi.val << 32);
return true;
}
bool OSTimeLinux::getCpuGpuTime(TimeStampData *pGpuCpuTime) {
if (nullptr == this->getGpuTime) {
return false;
}
if (!(this->*getGpuTime)(&pGpuCpuTime->GPUTimeStamp)) {
return false;
}
if (!getCpuTime(&pGpuCpuTime->CPUTimeinNS)) {
return false;
}
return true;
}
std::unique_ptr<OSTime> OSTime::create(OSInterface *osInterface) {
return std::unique_ptr<OSTime>(new OSTimeLinux(osInterface));
}
double OSTimeLinux::getHostTimerResolution() const {
struct timespec ts;
if (resolutionFunc(CLOCK_MONOTONIC_RAW, &ts)) {
return 0;
}
return ts.tv_nsec + ts.tv_sec * NSEC_PER_SEC;
}
double OSTimeLinux::getDynamicDeviceTimerResolution(HardwareInfo const &hwInfo) const {
if (pDrm) {
drm_i915_getparam_t getParam = {};
int frequency = 0;
getParam.param = I915_PARAM_CS_TIMESTAMP_FREQUENCY;
getParam.value = &frequency;
auto error = pDrm->ioctl(DRM_IOCTL_I915_GETPARAM, &getParam);
if (!error) {
return 1000000000.0 / frequency;
}
}
return OSTime::getDeviceTimerResolution(hwInfo);
}
uint64_t OSTimeLinux::getCpuRawTimestamp() {
uint64_t timesInNsec = 0;
uint64_t ticksInNsec = 0;
if (!getCpuTime(&timesInNsec)) {
return 0;
}
ticksInNsec = getHostTimerResolution();
if (ticksInNsec == 0) {
return 0;
}
return timesInNsec / ticksInNsec;
}
} // namespace NEO

44
runtime/os_interface/linux/os_time_linux.h
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@@ -1,44 +0,0 @@
/*
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "runtime/os_interface/linux/drm_neo.h"
#include "runtime/os_interface/os_time.h"
#define OCLRT_NUM_TIMESTAMP_BITS (36)
#define OCLRT_NUM_TIMESTAMP_BITS_FALLBACK (32)
#define TIMESTAMP_HIGH_REG 0x0235C
#define TIMESTAMP_LOW_REG 0x02358
namespace NEO {
class OSTimeLinux : public OSTime {
public:
OSTimeLinux(OSInterface *osInterface);
~OSTimeLinux() override;
bool getCpuTime(uint64_t *timeStamp) override;
bool getCpuGpuTime(TimeStampData *pGpuCpuTime) override;
typedef bool (OSTimeLinux::*TimestampFunction)(uint64_t *);
void timestampTypeDetect();
TimestampFunction getGpuTime = nullptr;
bool getGpuTime32(uint64_t *timestamp);
bool getGpuTime36(uint64_t *timestamp);
bool getGpuTimeSplitted(uint64_t *timestamp);
double getHostTimerResolution() const override;
double getDynamicDeviceTimerResolution(HardwareInfo const &hwInfo) const override;
uint64_t getCpuRawTimestamp() override;
protected:
typedef int (*resolutionFunc_t)(clockid_t, struct timespec *);
typedef int (*getTimeFunc_t)(clockid_t, struct timespec *);
Drm *pDrm;
unsigned timestampSizeInBits;
resolutionFunc_t resolutionFunc;
getTimeFunc_t getTimeFunc;
};
} // namespace NEO