Flush instruction cache.

Change-Id: I2ae0c40ae99cd8e0c126c8588e6df293e29d3db3
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
This commit is contained in:
Mrozek, Michal
2019-08-26 10:34:27 +02:00
committed by sys_ocldev
parent b0f662a148
commit 3d062620a7
2 changed files with 3 additions and 0 deletions

View File

@@ -157,6 +157,7 @@ typename Family::PIPE_CONTROL *PipeControlHelper<Family>::obtainPipeControlAndPr
pipeControl->setAddress(static_cast<uint32_t>(gpuAddress & 0x0000FFFFFFFFULL));
pipeControl->setAddressHigh(static_cast<uint32_t>(gpuAddress >> 32));
pipeControl->setDcFlushEnable(dcFlush);
pipeControl->setInstructionCacheInvalidateEnable(true);
if (operation == POST_SYNC_OPERATION::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA) {
pipeControl->setImmediateData(immediateData);
}