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style: configure readability-identifier-naming.FunctionCase

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Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
This commit is contained in:
Artur Harasimiuk
2022-05-16 14:06:56 +00:00
committed by Compute-Runtime-Automation
parent b3261a8e2b
commit 3f04769f07
178 changed files with 2560 additions and 2556 deletions
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4
shared/test/common/cmd_parse/gen_cmd_parse.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -76,7 +76,7 @@ static inline typename FamilyType::MI_LOAD_REGISTER_IMM *findMmioCmd(GenCmdList:
}
template <typename Type>
static inline GenCmdList::reverse_iterator reverse_find(GenCmdList::reverse_iterator itorStart, GenCmdList::const_reverse_iterator itorEnd) {
static inline GenCmdList::reverse_iterator reverseFind(GenCmdList::reverse_iterator itorStart, GenCmdList::const_reverse_iterator itorEnd) {
GenCmdList::reverse_iterator itor = itorStart;
while (itor != itorEnd) {
if (genCmdCast<Type>(*itor))

4
shared/test/common/fixtures/preemption_fixture.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -63,4 +63,4 @@ struct PreemptionTestHwDetails {
};
template <typename FamilyType>
PreemptionTestHwDetails GetPreemptionTestHwDetails();
PreemptionTestHwDetails getPreemptionTestHwDetails();

4
shared/test/common/gen11/test_preemption_gen11.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Intel Corporation
* Copyright (C) 2019-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -17,7 +17,7 @@
using namespace NEO;
template <>
PreemptionTestHwDetails GetPreemptionTestHwDetails<ICLFamily>() {
PreemptionTestHwDetails getPreemptionTestHwDetails<ICLFamily>() {
PreemptionTestHwDetails ret;
ret.modeToRegValueMap[PreemptionMode::ThreadGroup] = DwordBuilder::build(1, true) | DwordBuilder::build(2, true, false);
ret.modeToRegValueMap[PreemptionMode::MidBatch] = DwordBuilder::build(2, true) | DwordBuilder::build(1, true, false);

4
shared/test/common/gen12lp/test_preemption_gen12lp.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2021 Intel Corporation
* Copyright (C) 2020-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -14,7 +14,7 @@
using namespace NEO;
template <>
PreemptionTestHwDetails GetPreemptionTestHwDetails<TGLLPFamily>() {
PreemptionTestHwDetails getPreemptionTestHwDetails<TGLLPFamily>() {
PreemptionTestHwDetails ret;
ret.modeToRegValueMap[PreemptionMode::ThreadGroup] = DwordBuilder::build(1, true) | DwordBuilder::build(2, true, false);
ret.modeToRegValueMap[PreemptionMode::MidBatch] = DwordBuilder::build(2, true) | DwordBuilder::build(1, true, false);

4
shared/test/common/gen8/test_preemption_gen8.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -16,7 +16,7 @@
using namespace NEO;
template <>
PreemptionTestHwDetails GetPreemptionTestHwDetails<BDWFamily>() {
PreemptionTestHwDetails getPreemptionTestHwDetails<BDWFamily>() {
PreemptionTestHwDetails ret;
ret.modeToRegValueMap[PreemptionMode::ThreadGroup] = 0;
ret.modeToRegValueMap[PreemptionMode::MidBatch] = (1 << 2);

4
shared/test/common/gen9/preamble_tests_gen9.cpp
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@@ -81,7 +81,7 @@ GEN9TEST_F(ThreadArbitrationGen9, givenPreambleWhenItIsProgrammedThenThreadArbit
auto ppC = find<PIPE_CONTROL *>(cmdList.begin(), cmdList.end());
ASSERT_EQ(cmdList.end(), ppC);
auto itorLRI = reverse_find<MI_LOAD_REGISTER_IMM *>(cmdList.rbegin(), cmdList.rend());
auto itorLRI = reverseFind<MI_LOAD_REGISTER_IMM *>(cmdList.rbegin(), cmdList.rend());
ASSERT_NE(cmdList.rend(), itorLRI);
const auto &lri = *reinterpret_cast<MI_LOAD_REGISTER_IMM *>(*itorLRI);
@@ -108,7 +108,7 @@ GEN9TEST_F(ThreadArbitrationGen9, whenThreadArbitrationPolicyIsProgrammedThenCor
auto ppC = find<PIPE_CONTROL *>(cmdList.begin(), cmdList.end());
ASSERT_NE(ppC, cmdList.end());
auto itorLRI = reverse_find<MI_LOAD_REGISTER_IMM *>(cmdList.rbegin(), cmdList.rend());
auto itorLRI = reverseFind<MI_LOAD_REGISTER_IMM *>(cmdList.rbegin(), cmdList.rend());
ASSERT_NE(cmdList.rend(), itorLRI);
const auto &lri = *reinterpret_cast<MI_LOAD_REGISTER_IMM *>(*itorLRI);

4
shared/test/common/gen9/test_preemption_gen9.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -19,7 +19,7 @@
using namespace NEO;
template <>
PreemptionTestHwDetails GetPreemptionTestHwDetails<SKLFamily>() {
PreemptionTestHwDetails getPreemptionTestHwDetails<SKLFamily>() {
PreemptionTestHwDetails ret;
ret.modeToRegValueMap[PreemptionMode::ThreadGroup] = DwordBuilder::build(1, true) | DwordBuilder::build(2, true, false);
ret.modeToRegValueMap[PreemptionMode::MidBatch] = DwordBuilder::build(2, true) | DwordBuilder::build(1, true, false);

4
shared/test/common/test_configuration/aub_tests/aub_tests_configuration.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -12,4 +12,4 @@ struct AubTestsConfig {
};
template <typename GfxFamily>
AubTestsConfig GetAubTestsConfig();
AubTestsConfig getAubTestsConfig();

4
shared/test/common/test_configuration/aub_tests/aub_tests_configuration.inl
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -9,7 +9,7 @@
#include "shared/test/common/test_configuration/aub_tests/aub_tests_configuration.h"
template <typename GfxFamily>
AubTestsConfig GetAubTestsConfig() {
AubTestsConfig getAubTestsConfig() {
AubTestsConfig aubTestsConfig;
aubTestsConfig.testCanonicalAddress = true;
return aubTestsConfig;

4
shared/test/common/test_configuration/aub_tests/gen11/aub_tests_configuration_gen11.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Intel Corporation
* Copyright (C) 2019-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -11,4 +11,4 @@
using namespace NEO;
template AubTestsConfig GetAubTestsConfig<ICLFamily>();
template AubTestsConfig getAubTestsConfig<ICLFamily>();

4
shared/test/common/test_configuration/aub_tests/gen12lp/aub_tests_configuration_gen12lp.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Intel Corporation
* Copyright (C) 2019-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -12,7 +12,7 @@
using namespace NEO;
template <>
AubTestsConfig GetAubTestsConfig<TGLLPFamily>() {
AubTestsConfig getAubTestsConfig<TGLLPFamily>() {
AubTestsConfig aubTestsConfig;
aubTestsConfig.testCanonicalAddress = false;
return aubTestsConfig;

4
shared/test/common/test_configuration/aub_tests/gen8/aub_tests_configuration_gen8.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -11,4 +11,4 @@
using namespace NEO;
template AubTestsConfig GetAubTestsConfig<BDWFamily>();
template AubTestsConfig getAubTestsConfig<BDWFamily>();

4
shared/test/common/test_configuration/aub_tests/gen9/aub_tests_configuration_gen9.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -11,4 +11,4 @@
using namespace NEO;
template AubTestsConfig GetAubTestsConfig<SKLFamily>();
template AubTestsConfig getAubTestsConfig<SKLFamily>();

4
shared/test/common/test_configuration/aub_tests/xe_hp_core/aub_tests_configuration_xe_hp_core.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -12,7 +12,7 @@
using namespace NEO;
template <>
AubTestsConfig GetAubTestsConfig<XeHpFamily>() {
AubTestsConfig getAubTestsConfig<XeHpFamily>() {
AubTestsConfig aubTestsConfig;
aubTestsConfig.testCanonicalAddress = true;
return aubTestsConfig;

4
shared/test/common/test_configuration/aub_tests/xe_hpc_core/aub_tests_configuration_xe_hpc_core.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -12,7 +12,7 @@
using namespace NEO;
template <>
AubTestsConfig GetAubTestsConfig<XE_HPC_COREFamily>() {
AubTestsConfig getAubTestsConfig<XE_HPC_COREFamily>() {
AubTestsConfig aubTestsConfig;
aubTestsConfig.testCanonicalAddress = false;
return aubTestsConfig;

4
shared/test/common/test_configuration/aub_tests/xe_hpg_core/aub_tests_configuration_xe_hpg_core.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -12,7 +12,7 @@
using namespace NEO;
template <>
AubTestsConfig GetAubTestsConfig<XE_HPG_COREFamily>() {
AubTestsConfig getAubTestsConfig<XE_HPG_COREFamily>() {
AubTestsConfig aubTestsConfig;
aubTestsConfig.testCanonicalAddress = true;
return aubTestsConfig;

4
shared/test/common/xe_hp_core/test_preemption_xe_hp_core.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -13,7 +13,7 @@ using namespace NEO;
HWTEST_EXCLUDE_PRODUCT(XeHPAndLaterPreemptionTests, GivenDebuggerUsedWhenProgrammingStateSipThenStateSipIsAdded, IGFX_XE_HP_CORE);
template <>
PreemptionTestHwDetails GetPreemptionTestHwDetails<XeHpFamily>() {
PreemptionTestHwDetails getPreemptionTestHwDetails<XeHpFamily>() {
PreemptionTestHwDetails ret;
ret.modeToRegValueMap[PreemptionMode::ThreadGroup] = DwordBuilder::build(1, true) | DwordBuilder::build(2, true, false);
ret.modeToRegValueMap[PreemptionMode::MidBatch] = DwordBuilder::build(2, true) | DwordBuilder::build(1, true, false);

4
shared/test/common/xe_hpc_core/test_preemption_xe_hpc_core.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -11,7 +11,7 @@
using namespace NEO;
template <>
PreemptionTestHwDetails GetPreemptionTestHwDetails<XE_HPC_COREFamily>() {
PreemptionTestHwDetails getPreemptionTestHwDetails<XE_HPC_COREFamily>() {
PreemptionTestHwDetails ret;
ret.modeToRegValueMap[PreemptionMode::ThreadGroup] = DwordBuilder::build(1, true) | DwordBuilder::build(2, true, false);
ret.modeToRegValueMap[PreemptionMode::MidBatch] = DwordBuilder::build(2, true) | DwordBuilder::build(1, true, false);

4
shared/test/common/xe_hpg_core/test_preemption_xe_hpg_core.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -11,7 +11,7 @@
using namespace NEO;
template <>
PreemptionTestHwDetails GetPreemptionTestHwDetails<XE_HPG_COREFamily>() {
PreemptionTestHwDetails getPreemptionTestHwDetails<XE_HPG_COREFamily>() {
PreemptionTestHwDetails ret;
ret.modeToRegValueMap[PreemptionMode::ThreadGroup] = DwordBuilder::build(1, true) | DwordBuilder::build(2, true, false);
ret.modeToRegValueMap[PreemptionMode::MidBatch] = DwordBuilder::build(2, true) | DwordBuilder::build(1, true, false);

4
shared/test/unit_test/device_binary_format/elf/elf_encoder_tests.cpp
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@@ -400,10 +400,10 @@ TEST(ElfEncoder, WhenDefaultAlignmentIsRaisedThenSegmentDataAbideByIt) {
auto &header64 = *reinterpret_cast<ElfFileHeader<EI_CLASS_64> *>(elfData64.data());
auto sectionHeaders = reinterpret_cast<NEO::Elf::ElfSectionHeader<EI_CLASS_64> *>(elfData64.data() + static_cast<size_t>(header64.shOff));
auto programHeaders = reinterpret_cast<NEO::Elf::ElfProgramHeader<EI_CLASS_64> *>(elfData64.data() + static_cast<size_t>(header64.phOff));
for (const auto &section : NEO::CreateRange(sectionHeaders, header64.shNum)) {
for (const auto &section : NEO::createRange(sectionHeaders, header64.shNum)) {
EXPECT_EQ(0U, section.offset % 8U);
}
for (const auto &segment : NEO::CreateRange(programHeaders, header64.phNum)) {
for (const auto &segment : NEO::createRange(programHeaders, header64.phNum)) {
EXPECT_EQ(0U, segment.offset % alignment);
EXPECT_LE(alignment, segment.align);
}

6
shared/test/unit_test/direct_submission/dispatchers/render_dispatcher_tests.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2021 Intel Corporation
* Copyright (C) 2020-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -20,7 +20,7 @@ HWTEST_F(RenderDispatcherTest, givenRenderWhenAskingForPreemptionCmdSizeThenRetu
using MI_LOAD_REGISTER_IMM = typename FamilyType::MI_LOAD_REGISTER_IMM;
size_t expectedCmdSize = 0u;
if (GetPreemptionTestHwDetails<FamilyType>().supportsPreemptionProgramming()) {
if (getPreemptionTestHwDetails<FamilyType>().supportsPreemptionProgramming()) {
expectedCmdSize = sizeof(MI_LOAD_REGISTER_IMM);
}
EXPECT_EQ(expectedCmdSize, RenderDispatcher<FamilyType>::getSizePreemption());
@@ -29,7 +29,7 @@ HWTEST_F(RenderDispatcherTest, givenRenderWhenAskingForPreemptionCmdSizeThenRetu
HWTEST_F(RenderDispatcherTest, givenRenderWhenAddingPreemptionCmdThenExpectProperMmioAddress) {
using MI_LOAD_REGISTER_IMM = typename FamilyType::MI_LOAD_REGISTER_IMM;
auto preemptionDetails = GetPreemptionTestHwDetails<FamilyType>();
auto preemptionDetails = getPreemptionTestHwDetails<FamilyType>();
RenderDispatcher<FamilyType>::dispatchPreemption(cmdBuffer);

4
shared/test/unit_test/encoders/test_encode_dispatch_kernel.cpp
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@@ -630,13 +630,13 @@ HWCMDTEST_F(IGFX_GEN8_CORE, CommandEncodeStatesTest, givenDirtyHeapsWhenDispatch
GenCmdList cmdList;
CmdParse<FamilyType>::parseCommandBuffer(cmdList, ptrOffset(cmdContainer->getCommandStream()->getCpuBase(), 0), cmdContainer->getCommandStream()->getUsed());
auto itor = reverse_find<STATE_BASE_ADDRESS *>(cmdList.rbegin(), cmdList.rend());
auto itor = reverseFind<STATE_BASE_ADDRESS *>(cmdList.rbegin(), cmdList.rend());
ASSERT_NE(cmdList.rend(), itor);
auto cmdSba = genCmdCast<STATE_BASE_ADDRESS *>(*itor);
EXPECT_NE(nullptr, cmdSba);
auto itorPc = reverse_find<PIPE_CONTROL *>(itor, cmdList.rend());
auto itorPc = reverseFind<PIPE_CONTROL *>(itor, cmdList.rend());
ASSERT_NE(cmdList.rend(), itorPc);
bool foundPcWithDCFlush = false;

2
shared/test/unit_test/main.cpp
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@@ -112,7 +112,7 @@ void applyWorkarounds() {
//Create FileLogger to prevent false memory leaks
{
NEO::FileLoggerInstance();
NEO::fileLoggerInstance();
}
}

4
shared/test/unit_test/page_fault_manager/default_asan_options.cpp
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@@ -1,12 +1,12 @@
/*
* Copyright (C) 2019-2020 Intel Corporation
* Copyright (C) 2019-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
extern "C" {
const char *__asan_default_options() {
const char *__asan_default_options() { // NOLINT(readability-identifier-naming0
return "allow_user_segv_handler=1";
}
}

8
shared/test/unit_test/preemption/preemption_tests.cpp
View File

@@ -118,7 +118,7 @@ HWTEST_P(PreemptionHwTest, GivenPreemptionModeIsChangingWhenGettingRequiredCmdSt
PreemptionMode mode = GetParam();
PreemptionMode differentPreemptionMode = static_cast<PreemptionMode>(0);
if (false == GetPreemptionTestHwDetails<FamilyType>().supportsPreemptionProgramming()) {
if (false == getPreemptionTestHwDetails<FamilyType>().supportsPreemptionProgramming()) {
EXPECT_EQ(0U, PreemptionHelper::getRequiredCmdStreamSize<FamilyType>(mode, differentPreemptionMode));
return;
}
@@ -146,7 +146,7 @@ HWTEST_P(PreemptionHwTest, WhenProgrammingCmdStreamThenProperMiLoadRegisterImmCo
PreemptionMode differentPreemptionMode = static_cast<PreemptionMode>(0);
auto mockDevice = std::unique_ptr<MockDevice>(MockDevice::createWithNewExecutionEnvironment<MockDevice>(nullptr));
if (false == GetPreemptionTestHwDetails<FamilyType>().supportsPreemptionProgramming()) {
if (false == getPreemptionTestHwDetails<FamilyType>().supportsPreemptionProgramming()) {
LinearStream cmdStream(nullptr, 0U);
PreemptionHelper::programCmdStream<FamilyType>(cmdStream, mode, differentPreemptionMode, nullptr);
EXPECT_EQ(0U, cmdStream.getUsed());
@@ -154,7 +154,7 @@ HWTEST_P(PreemptionHwTest, WhenProgrammingCmdStreamThenProperMiLoadRegisterImmCo
}
using MI_LOAD_REGISTER_IMM = typename FamilyType::MI_LOAD_REGISTER_IMM;
auto hwDetails = GetPreemptionTestHwDetails<FamilyType>();
auto hwDetails = getPreemptionTestHwDetails<FamilyType>();
uint32_t defaultRegValue = hwDetails.defaultRegValue;
@@ -383,7 +383,7 @@ HWCMDTEST_F(IGFX_GEN8_CORE, MidThreadPreemptionTests, WhenProgrammingPreemptionT
dispatchFlags,
*mockDevice);
auto hwDetails = GetPreemptionTestHwDetails<FamilyType>();
auto hwDetails = getPreemptionTestHwDetails<FamilyType>();
HardwareParse hwParser;
hwParser.parseCommands<FamilyType>(csr.getCS(0));

4
shared/test/unit_test/utilities/base_object_utils.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -28,7 +28,7 @@ static ReleaseableObjectPtr<T> clUniquePtr(T *object) {
}
template <class _Ty, class... _Types>
inline ReleaseableObjectPtr<_Ty> make_releaseable(_Types &&...args) {
inline ReleaseableObjectPtr<_Ty> makeReleaseable(_Types &&...args) {
return (ReleaseableObjectPtr<_Ty>(new _Ty(std::forward<_Types>(args)...)));
}
} // namespace NEO