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Improve build time: command_queue tests
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com> Change-Id: Ia80a8bfed28789c6c7a53478cdd56f883d61adf3
This commit is contained in:
Dunajski, Bartosz
committed by
sys_ocldev
sys_ocldev
parent
54572163d8
commit
41811852db
@@ -1,571 +0,0 @@
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/*
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* Copyright (c) 2017 - 2018, Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "runtime/built_ins/built_ins.h"
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#include "runtime/built_ins/builtins_dispatch_builder.h"
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#include "reg_configs_common.h"
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#include "runtime/helpers/dispatch_info.h"
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#include "unit_tests/command_queue/enqueue_write_buffer_rect_fixture.h"
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#include "unit_tests/fixtures/buffer_fixture.h"
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#include "unit_tests/gen_common/gen_commands_common_validation.h"
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#include "test.h"
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using namespace OCLRT;
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HWTEST_F(EnqueueWriteBufferRectTest, nullBufferReturnsError) {
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auto retVal = CL_SUCCESS;
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size_t srcOrigin[] = {0, 0, 0};
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size_t dstOrigin[] = {0, 0, 0};
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size_t region[] = {1, 1, 1};
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retVal = clEnqueueWriteBufferRect(
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pCmdQ,
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nullptr,
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CL_FALSE,
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srcOrigin,
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dstOrigin,
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region,
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10,
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0,
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10,
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0,
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hostPtr,
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0,
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nullptr,
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nullptr);
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EXPECT_EQ(CL_INVALID_MEM_OBJECT, retVal);
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}
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HWTEST_F(EnqueueWriteBufferRectTest, returnSuccess) {
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auto retVal = CL_SUCCESS;
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size_t srcOrigin[] = {0, 0, 0};
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size_t dstOrigin[] = {0, 0, 0};
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size_t region[] = {1, 1, 1};
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retVal = clEnqueueWriteBufferRect(
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pCmdQ,
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buffer.get(),
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CL_TRUE,
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srcOrigin,
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dstOrigin,
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region,
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10,
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0,
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10,
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0,
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hostPtr,
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0,
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nullptr,
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nullptr);
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EXPECT_EQ(CL_SUCCESS, retVal);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, alignsToCSR_Blocking) {
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//this test case assumes IOQ
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auto &csr = pDevice->getUltCommandStreamReceiver<FamilyType>();
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csr.taskCount = pCmdQ->taskCount + 100;
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csr.taskLevel = pCmdQ->taskLevel + 50;
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auto oldCsrTaskLevel = csr.peekTaskLevel();
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enqueueWriteBufferRect2D<FamilyType>(CL_TRUE);
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EXPECT_EQ(csr.peekTaskCount(), pCmdQ->taskCount);
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EXPECT_EQ(oldCsrTaskLevel, pCmdQ->taskLevel);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, alignsToCSR_NonBlocking) {
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//this test case assumes IOQ
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auto &csr = pDevice->getUltCommandStreamReceiver<FamilyType>();
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csr.taskCount = pCmdQ->taskCount + 100;
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csr.taskLevel = pCmdQ->taskLevel + 50;
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enqueueWriteBufferRect2D<FamilyType>(CL_FALSE);
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EXPECT_EQ(csr.peekTaskCount(), pCmdQ->taskCount);
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EXPECT_EQ(csr.peekTaskLevel(), pCmdQ->taskLevel + 1);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, 2D_GPGPUWalker) {
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typedef typename FamilyType::GPGPU_WALKER GPGPU_WALKER;
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enqueueWriteBufferRect2D<FamilyType>();
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ASSERT_NE(cmdList.end(), itorWalker);
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auto *cmd = (GPGPU_WALKER *)*itorWalker;
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// Verify GPGPU_WALKER parameters
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EXPECT_NE(0u, cmd->getThreadGroupIdXDimension());
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EXPECT_NE(0u, cmd->getThreadGroupIdYDimension());
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EXPECT_EQ(1u, cmd->getThreadGroupIdZDimension());
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EXPECT_NE(0u, cmd->getRightExecutionMask());
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EXPECT_NE(0u, cmd->getBottomExecutionMask());
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EXPECT_EQ(GPGPU_WALKER::SIMD_SIZE_SIMD32, cmd->getSimdSize());
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EXPECT_NE(0u, cmd->getIndirectDataLength());
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EXPECT_FALSE(cmd->getIndirectParameterEnable());
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// Compute the SIMD lane mask
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size_t simd =
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cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16 : 8;
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uint64_t simdMask = (1ull << simd) - 1;
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// Mask off lanes based on the execution masks
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auto laneMaskRight = cmd->getRightExecutionMask() & simdMask;
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auto lanesPerThreadX = 0;
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while (laneMaskRight) {
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lanesPerThreadX += laneMaskRight & 1;
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laneMaskRight >>= 1;
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}
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, 2D_bumpsTaskLevel) {
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auto taskLevelBefore = pCmdQ->taskLevel;
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enqueueWriteBufferRect2D<FamilyType>();
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EXPECT_GT(pCmdQ->taskLevel, taskLevelBefore);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, 2D_addsCommands) {
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auto usedCmdBufferBefore = pCS->getUsed();
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enqueueWriteBufferRect2D<FamilyType>();
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EXPECT_NE(usedCmdBufferBefore, pCS->getUsed());
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, 2D_addsIndirectData) {
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auto dshBefore = pDSH->getUsed();
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auto iohBefore = pIOH->getUsed();
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auto sshBefore = pSSH->getUsed();
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enqueueWriteBufferRect2D<FamilyType>();
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MultiDispatchInfo multiDispatchInfo;
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auto &builder = pCmdQ->getDevice().getExecutionEnvironment()->getBuiltIns()->getBuiltinDispatchInfoBuilder(EBuiltInOps::CopyBufferRect,
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pCmdQ->getContext(), pCmdQ->getDevice());
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ASSERT_NE(nullptr, &builder);
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BuiltinDispatchInfoBuilder::BuiltinOpParams dc;
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dc.srcPtr = hostPtr;
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dc.dstMemObj = buffer.get();
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dc.srcOffset = {0, 0, 0};
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dc.dstOffset = {0, 0, 0};
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dc.size = {50, 50, 1};
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dc.srcRowPitch = rowPitch;
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dc.srcSlicePitch = slicePitch;
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dc.dstRowPitch = rowPitch;
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dc.dstSlicePitch = slicePitch;
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builder.buildDispatchInfos(multiDispatchInfo, dc);
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EXPECT_NE(0u, multiDispatchInfo.size());
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auto kernel = multiDispatchInfo.begin()->getKernel();
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ASSERT_NE(nullptr, kernel);
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EXPECT_NE(dshBefore, pDSH->getUsed());
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EXPECT_NE(iohBefore, pIOH->getUsed());
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if (kernel->requiresSshForBuffers()) {
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EXPECT_NE(sshBefore, pSSH->getUsed());
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}
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, 2D_LoadRegisterImmediateL3CNTLREG) {
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enqueueWriteBufferRect2D<FamilyType>();
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validateL3Programming<FamilyType>(cmdList, itorWalker);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, When2DEnqueueIsDoneThenStateBaseAddressIsProperlyProgrammed) {
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enqueueWriteBufferRect2D<FamilyType>();
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validateStateBaseAddress<FamilyType>(this->pDevice->getCommandStreamReceiver().getMemoryManager()->getInternalHeapBaseAddress(),
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pDSH, pIOH, pSSH, itorPipelineSelect, itorWalker, cmdList, 0llu);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, 2D_MediaInterfaceDescriptorLoad) {
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typedef typename FamilyType::MEDIA_INTERFACE_DESCRIPTOR_LOAD MEDIA_INTERFACE_DESCRIPTOR_LOAD;
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typedef typename FamilyType::INTERFACE_DESCRIPTOR_DATA INTERFACE_DESCRIPTOR_DATA;
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enqueueWriteBufferRect2D<FamilyType>();
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// All state should be programmed before walker
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auto itorCmd = find<MEDIA_INTERFACE_DESCRIPTOR_LOAD *>(itorPipelineSelect, itorWalker);
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ASSERT_NE(itorWalker, itorCmd);
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auto *cmd = (MEDIA_INTERFACE_DESCRIPTOR_LOAD *)*itorCmd;
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// Verify we have a valid length -- multiple of INTERFACE_DESCRIPTOR_DATAs
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EXPECT_EQ(0u, cmd->getInterfaceDescriptorTotalLength() % sizeof(INTERFACE_DESCRIPTOR_DATA));
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// Validate the start address
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size_t alignmentStartAddress = 64 * sizeof(uint8_t);
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EXPECT_EQ(0u, cmd->getInterfaceDescriptorDataStartAddress() % alignmentStartAddress);
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// Validate the length
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EXPECT_NE(0u, cmd->getInterfaceDescriptorTotalLength());
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size_t alignmentTotalLength = 32 * sizeof(uint8_t);
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EXPECT_EQ(0u, cmd->getInterfaceDescriptorTotalLength() % alignmentTotalLength);
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// Generically validate this command
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FamilyType::PARSE::template validateCommand<MEDIA_INTERFACE_DESCRIPTOR_LOAD *>(cmdList.begin(), itorCmd);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, 2D_InterfaceDescriptorData) {
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typedef typename FamilyType::MEDIA_INTERFACE_DESCRIPTOR_LOAD MEDIA_INTERFACE_DESCRIPTOR_LOAD;
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typedef typename FamilyType::STATE_BASE_ADDRESS STATE_BASE_ADDRESS;
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typedef typename FamilyType::INTERFACE_DESCRIPTOR_DATA INTERFACE_DESCRIPTOR_DATA;
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enqueueWriteBufferRect2D<FamilyType>();
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// Extract the MIDL command
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auto itorCmd = find<MEDIA_INTERFACE_DESCRIPTOR_LOAD *>(itorPipelineSelect, itorWalker);
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ASSERT_NE(itorWalker, itorCmd);
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auto *cmdMIDL = (MEDIA_INTERFACE_DESCRIPTOR_LOAD *)*itorCmd;
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// Extract the SBA command
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itorCmd = find<STATE_BASE_ADDRESS *>(cmdList.begin(), itorWalker);
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ASSERT_NE(itorWalker, itorCmd);
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auto *cmdSBA = (STATE_BASE_ADDRESS *)*itorCmd;
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// Extrach the DSH
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auto DSH = cmdSBA->getDynamicStateBaseAddress();
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ASSERT_NE(0u, DSH);
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// IDD should be located within DSH
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auto iddStart = cmdMIDL->getInterfaceDescriptorDataStartAddress();
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auto IDDEnd = iddStart + cmdMIDL->getInterfaceDescriptorTotalLength();
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ASSERT_LE(IDDEnd, cmdSBA->getDynamicStateBufferSize() * MemoryConstants::pageSize);
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// Extract the IDD
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auto &IDD = *(INTERFACE_DESCRIPTOR_DATA *)(DSH + iddStart);
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// Validate the kernel start pointer. Technically, a kernel can start at address 0 but let's force a value.
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auto kernelStartPointer = ((uint64_t)IDD.getKernelStartPointerHigh() << 32) + IDD.getKernelStartPointer();
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EXPECT_LE(kernelStartPointer, cmdSBA->getInstructionBufferSize() * MemoryConstants::pageSize);
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EXPECT_NE(0u, IDD.getNumberOfThreadsInGpgpuThreadGroup());
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EXPECT_NE(0u, IDD.getCrossThreadConstantDataReadLength());
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EXPECT_NE(0u, IDD.getConstantIndirectUrbEntryReadLength());
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, 2D_PipelineSelect) {
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enqueueWriteBufferRect2D<FamilyType>();
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int numCommands = getNumberOfPipelineSelectsThatEnablePipelineSelect<FamilyType>();
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EXPECT_EQ(1, numCommands);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueWriteBufferRectTest, 2D_MediaVFEState) {
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enqueueWriteBufferRect2D<FamilyType>();
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validateMediaVFEState<FamilyType>(&pDevice->getHardwareInfo(), cmdMediaVfeState, cmdList, itorMediaVfeState);
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}
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HWTEST_F(EnqueueWriteBufferRectTest, givenInOrderQueueAndDstPtrEqualSrcPtrWhenWriteBufferIsExecutedThenTaskLevelShouldNotBeIncreased) {
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cl_int retVal = CL_SUCCESS;
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void *ptr = buffer->getCpuAddressForMemoryTransfer();
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size_t bufferOrigin[] = {0, 0, 0};
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size_t hostOrigin[] = {0, 0, 0};
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size_t region[] = {50, 50, 1};
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retVal = pCmdQ->enqueueWriteBufferRect(
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buffer.get(),
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CL_FALSE,
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bufferOrigin,
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hostOrigin,
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region,
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rowPitch,
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slicePitch,
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rowPitch,
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slicePitch,
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ptr,
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0,
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nullptr,
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nullptr);
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EXPECT_EQ(CL_SUCCESS, retVal);
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EXPECT_EQ(CL_SUCCESS, retVal);
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EXPECT_EQ(pCmdQ->taskLevel, 0u);
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}
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HWTEST_F(EnqueueWriteBufferRectTest, givenOutOfOrderQueueAndDstPtrEqualSrcPtrWhenWriteBufferIsExecutedThenTaskLevelShouldNotBeIncreased) {
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cl_int retVal = CL_SUCCESS;
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std::unique_ptr<CommandQueue> pCmdOOQ(createCommandQueue(pDevice, CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE));
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void *ptr = buffer->getCpuAddressForMemoryTransfer();
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size_t bufferOrigin[] = {0, 0, 0};
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size_t hostOrigin[] = {0, 0, 0};
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size_t region[] = {50, 50, 1};
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retVal = pCmdOOQ->enqueueWriteBufferRect(
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buffer.get(),
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CL_FALSE,
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bufferOrigin,
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hostOrigin,
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region,
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rowPitch,
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slicePitch,
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rowPitch,
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slicePitch,
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ptr,
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0,
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nullptr,
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nullptr);
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EXPECT_EQ(CL_SUCCESS, retVal);
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EXPECT_EQ(CL_SUCCESS, retVal);
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EXPECT_EQ(pCmdOOQ->taskLevel, 0u);
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}
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HWTEST_F(EnqueueWriteBufferRectTest, givenInOrderQueueAndDstPtrEqualSrcPtrWithEventsWhenWriteBufferIsExecutedThenTaskLevelShouldNotBeIncreased) {
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cl_int retVal = CL_SUCCESS;
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uint32_t taskLevelCmdQ = 17;
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pCmdQ->taskLevel = taskLevelCmdQ;
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uint32_t taskLevelEvent1 = 8;
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uint32_t taskLevelEvent2 = 19;
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Event event1(pCmdQ, CL_COMMAND_NDRANGE_KERNEL, taskLevelEvent1, 4);
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Event event2(pCmdQ, CL_COMMAND_NDRANGE_KERNEL, taskLevelEvent2, 10);
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cl_event eventWaitList[] =
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{
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&event1,
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&event2};
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cl_uint numEventsInWaitList = sizeof(eventWaitList) / sizeof(eventWaitList[0]);
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cl_event event = nullptr;
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size_t bufferOrigin[] = {0, 0, 0};
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size_t hostOrigin[] = {0, 0, 0};
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size_t region[] = {50, 50, 1};
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void *ptr = buffer->getCpuAddressForMemoryTransfer();
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retVal = pCmdQ->enqueueWriteBufferRect(
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buffer.get(),
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CL_FALSE,
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bufferOrigin,
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hostOrigin,
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region,
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rowPitch,
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slicePitch,
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rowPitch,
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slicePitch,
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ptr,
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numEventsInWaitList,
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eventWaitList,
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&event);
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;
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EXPECT_EQ(CL_SUCCESS, retVal);
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ASSERT_NE(nullptr, event);
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auto pEvent = (Event *)event;
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EXPECT_EQ(19u, pEvent->taskLevel);
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EXPECT_EQ(19u, pCmdQ->taskLevel);
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EXPECT_EQ(CL_COMMAND_WRITE_BUFFER_RECT, (const int)pEvent->getCommandType());
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pEvent->release();
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}
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HWTEST_F(EnqueueWriteBufferRectTest, givenOutOfOrderQueueAndDstPtrEqualSrcPtrWithEventsWhenWriteBufferIsExecutedThenTaskLevelShouldNotBeIncreased) {
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cl_int retVal = CL_SUCCESS;
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std::unique_ptr<CommandQueue> pCmdOOQ(createCommandQueue(pDevice, CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE));
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uint32_t taskLevelCmdQ = 17;
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pCmdOOQ->taskLevel = taskLevelCmdQ;
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uint32_t taskLevelEvent1 = 8;
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uint32_t taskLevelEvent2 = 19;
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Event event1(pCmdOOQ.get(), CL_COMMAND_NDRANGE_KERNEL, taskLevelEvent1, 4);
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Event event2(pCmdOOQ.get(), CL_COMMAND_NDRANGE_KERNEL, taskLevelEvent2, 10);
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cl_event eventWaitList[] =
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{
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&event1,
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&event2};
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cl_uint numEventsInWaitList = sizeof(eventWaitList) / sizeof(eventWaitList[0]);
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cl_event event = nullptr;
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size_t bufferOrigin[] = {0, 0, 0};
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size_t hostOrigin[] = {0, 0, 0};
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size_t region[] = {50, 50, 1};
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void *ptr = buffer->getCpuAddressForMemoryTransfer();
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retVal = pCmdOOQ->enqueueWriteBufferRect(
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buffer.get(),
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CL_FALSE,
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bufferOrigin,
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hostOrigin,
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region,
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rowPitch,
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slicePitch,
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rowPitch,
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slicePitch,
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ptr,
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numEventsInWaitList,
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eventWaitList,
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&event);
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EXPECT_EQ(CL_SUCCESS, retVal);
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EXPECT_EQ(CL_SUCCESS, retVal);
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ASSERT_NE(nullptr, event);
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auto pEvent = (Event *)event;
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EXPECT_EQ(19u, pEvent->taskLevel);
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EXPECT_EQ(19u, pCmdOOQ->taskLevel);
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EXPECT_EQ(CL_COMMAND_WRITE_BUFFER_RECT, (const int)pEvent->getCommandType());
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pEvent->release();
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}
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HWTEST_F(EnqueueWriteBufferRectTest, givenInOrderQueueAndRowPitchEqualZeroAndDstPtrEqualSrcPtrWhenWriteBufferIsExecutedThenTaskLevelShouldNotBeIncreased) {
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cl_int retVal = CL_SUCCESS;
|
||||
void *ptr = buffer->getCpuAddressForMemoryTransfer();
|
||||
size_t bufferOrigin[] = {0, 0, 0};
|
||||
size_t hostOrigin[] = {0, 0, 0};
|
||||
size_t region[] = {50, 50, 1};
|
||||
retVal = pCmdQ->enqueueWriteBufferRect(
|
||||
buffer.get(),
|
||||
CL_FALSE,
|
||||
bufferOrigin,
|
||||
hostOrigin,
|
||||
region,
|
||||
0,
|
||||
slicePitch,
|
||||
0,
|
||||
slicePitch,
|
||||
ptr,
|
||||
0,
|
||||
nullptr,
|
||||
nullptr);
|
||||
EXPECT_EQ(CL_SUCCESS, retVal);
|
||||
|
||||
EXPECT_EQ(CL_SUCCESS, retVal);
|
||||
EXPECT_EQ(pCmdQ->taskLevel, 0u);
|
||||
}
|
||||
HWTEST_F(EnqueueWriteBufferRectTest, givenInOrderQueueAndSlicePitchEqualZeroAndDstPtrEqualSrcPtrWhenWriteBufferIsExecutedThenTaskLevelShouldNotBeIncreased) {
|
||||
cl_int retVal = CL_SUCCESS;
|
||||
void *ptr = buffer->getCpuAddressForMemoryTransfer();
|
||||
size_t bufferOrigin[] = {0, 0, 0};
|
||||
size_t hostOrigin[] = {0, 0, 0};
|
||||
size_t region[] = {50, 50, 1};
|
||||
retVal = pCmdQ->enqueueWriteBufferRect(
|
||||
buffer.get(),
|
||||
CL_FALSE,
|
||||
bufferOrigin,
|
||||
hostOrigin,
|
||||
region,
|
||||
rowPitch,
|
||||
0,
|
||||
rowPitch,
|
||||
0,
|
||||
ptr,
|
||||
0,
|
||||
nullptr,
|
||||
nullptr);
|
||||
EXPECT_EQ(CL_SUCCESS, retVal);
|
||||
|
||||
EXPECT_EQ(CL_SUCCESS, retVal);
|
||||
EXPECT_EQ(pCmdQ->taskLevel, 0u);
|
||||
}
|
||||
HWTEST_F(EnqueueWriteBufferRectTest, givenInOrderQueueAndMemObjWithOffsetPointTheSameStorageWithHostWhenWriteBufferIsExecutedThenTaskLevelShouldNotBeIncreased) {
|
||||
cl_int retVal = CL_SUCCESS;
|
||||
void *ptr = buffer->getCpuAddressForMemoryTransfer();
|
||||
size_t bufferOrigin[] = {50, 50, 0};
|
||||
size_t hostOrigin[] = {20, 20, 0};
|
||||
size_t region[] = {50, 50, 1};
|
||||
size_t hostOffset = (bufferOrigin[2] - hostOrigin[2]) * slicePitch + (bufferOrigin[1] - hostOrigin[1]) * rowPitch + (bufferOrigin[0] - hostOrigin[0]);
|
||||
auto hostStorage = ptrOffset(ptr, hostOffset);
|
||||
retVal = pCmdQ->enqueueWriteBufferRect(
|
||||
buffer.get(),
|
||||
CL_FALSE,
|
||||
bufferOrigin,
|
||||
hostOrigin,
|
||||
region,
|
||||
rowPitch,
|
||||
slicePitch,
|
||||
rowPitch,
|
||||
slicePitch,
|
||||
hostStorage,
|
||||
0,
|
||||
nullptr,
|
||||
nullptr);
|
||||
EXPECT_EQ(CL_SUCCESS, retVal);
|
||||
|
||||
EXPECT_EQ(CL_SUCCESS, retVal);
|
||||
EXPECT_EQ(pCmdQ->taskLevel, 0u);
|
||||
}
|
||||
HWTEST_F(EnqueueWriteBufferRectTest, givenInOrderQueueAndMemObjWithOffsetPointDiffrentStorageWithHostWhenWriteBufferIsExecutedThenTaskLevelShouldBeIncreased) {
|
||||
cl_int retVal = CL_SUCCESS;
|
||||
void *ptr = buffer->getCpuAddressForMemoryTransfer();
|
||||
size_t bufferOrigin[] = {0, 0, 0};
|
||||
size_t hostOrigin[] = {1, 1, 0};
|
||||
size_t region[] = {1, 1, 1};
|
||||
retVal = pCmdQ->enqueueWriteBufferRect(
|
||||
buffer.get(),
|
||||
CL_FALSE,
|
||||
bufferOrigin,
|
||||
hostOrigin,
|
||||
region,
|
||||
rowPitch,
|
||||
slicePitch,
|
||||
rowPitch,
|
||||
slicePitch,
|
||||
ptr,
|
||||
0,
|
||||
nullptr,
|
||||
nullptr);
|
||||
EXPECT_EQ(CL_SUCCESS, retVal);
|
||||
|
||||
EXPECT_EQ(CL_SUCCESS, retVal);
|
||||
EXPECT_EQ(pCmdQ->taskLevel, 1u);
|
||||
}
|
||||
HWTEST_F(EnqueueWriteBufferRectTest, givenInOrderQueueAndDstPtrEqualSrcPtrAndNonZeroCopyBufferWhenWriteBufferIsExecutedThenTaskLevelShouldBeIncreased) {
|
||||
cl_int retVal = CL_SUCCESS;
|
||||
void *ptr = nonZeroCopyBuffer->getCpuAddressForMemoryTransfer();
|
||||
size_t bufferOrigin[] = {0, 0, 0};
|
||||
size_t hostOrigin[] = {0, 0, 0};
|
||||
size_t region[] = {1, 1, 1};
|
||||
retVal = pCmdQ->enqueueWriteBufferRect(
|
||||
nonZeroCopyBuffer.get(),
|
||||
CL_FALSE,
|
||||
bufferOrigin,
|
||||
hostOrigin,
|
||||
region,
|
||||
rowPitch,
|
||||
slicePitch,
|
||||
rowPitch,
|
||||
slicePitch,
|
||||
ptr,
|
||||
0,
|
||||
nullptr,
|
||||
nullptr);
|
||||
EXPECT_EQ(CL_SUCCESS, retVal);
|
||||
|
||||
EXPECT_EQ(CL_SUCCESS, retVal);
|
||||
EXPECT_EQ(pCmdQ->taskLevel, 1u);
|
||||
}
|
||||
|
||||
using NegativeFailAllocationTest = Test<NegativeFailAllocationCommandEnqueueBaseFixture>;
|
||||
|
||||
HWTEST_F(NegativeFailAllocationTest, givenEnqueueWriteBufferRectWhenHostPtrAllocationCreationFailsThenReturnOutOfResource) {
|
||||
cl_int retVal = CL_SUCCESS;
|
||||
size_t bufferOrigin[] = {0, 0, 0};
|
||||
size_t hostOrigin[] = {0, 0, 0};
|
||||
size_t region[] = {50, 50, 1};
|
||||
constexpr size_t rowPitch = 100;
|
||||
constexpr size_t slicePitch = 100 * 100;
|
||||
|
||||
retVal = pCmdQ->enqueueWriteBufferRect(
|
||||
buffer.get(),
|
||||
CL_FALSE,
|
||||
bufferOrigin,
|
||||
hostOrigin,
|
||||
region,
|
||||
rowPitch,
|
||||
slicePitch,
|
||||
rowPitch,
|
||||
slicePitch,
|
||||
ptr,
|
||||
0,
|
||||
nullptr,
|
||||
nullptr);
|
||||
|
||||
EXPECT_EQ(CL_OUT_OF_RESOURCES, retVal);
|
||||
}
|
||||
Reference in New Issue
Block a user