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style: format code using clang-format 15.0.6

Browse Source 
Related-To: NEO-7500
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski
2023-01-04 15:00:09 +00:00
committed by Compute-Runtime-Automation
parent a4794e432d
commit 43b790957d
183 changed files with 1210 additions and 1211 deletions
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4
shared/offline_compiler/source/multi_command.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2022 Intel Corporation
* Copyright (C) 2019-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -112,7 +112,7 @@ int MultiCommand::initialize(const std::vector<std::string> &args) {
}
}
//save file with builds arguments to vector of strings, line by line
// save file with builds arguments to vector of strings, line by line
if (argHelper->fileExists(pathToCommandFile)) {
argHelper->readFileToVectorOfStrings(pathToCommandFile, lines);
if (lines.empty()) {

12
shared/offline_compiler/source/ocloc_api.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2022 Intel Corporation
* Copyright (C) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -60,12 +60,12 @@ int oclocInvoke(unsigned int numArgs, const char *argv[],
int oclocFreeOutput(uint32_t *numOutputs, uint8_t ***dataOutputs, uint64_t **lenOutputs, char ***nameOutputs) {
for (uint32_t i = 0; i < *numOutputs; i++) {
delete[](*dataOutputs)[i];
delete[](*nameOutputs)[i];
delete[] (*dataOutputs)[i];
delete[] (*nameOutputs)[i];
}
delete[](*dataOutputs);
delete[](*lenOutputs);
delete[](*nameOutputs);
delete[] (*dataOutputs);
delete[] (*lenOutputs);
delete[] (*nameOutputs);
return 0;
}

8
shared/source/aub/aub_subcapture.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2022 Intel Corporation
* Copyright (C) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -20,9 +20,9 @@ class SettingsReader;
class AubSubCaptureCommon {
public:
enum class SubCaptureMode {
Off = 0, //subcapture off
Filter, //subcapture kernel specified by filter (static regkey)
Toggle //toggle subcapture on/off (dynamic regkey)
Off = 0, // subcapture off
Filter, // subcapture kernel specified by filter (static regkey)
Toggle // toggle subcapture on/off (dynamic regkey)
} subCaptureMode = SubCaptureMode::Off;
struct SubCaptureFilter {

4
shared/source/aub_mem_dump/aub_alloc_dump.inl
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2022 Intel Corporation
* Copyright (C) 2019-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -168,7 +168,7 @@ void dumpImageInTreFormat(GraphicsAllocation &gfxAllocation, AubMemDump::AubFile
using RENDER_SURFACE_STATE = typename GfxFamily::RENDER_SURFACE_STATE;
auto gmm = gfxAllocation.getDefaultGmm();
if ((gmm->gmmResourceInfo->getNumSamples() > 1) || (gfxAllocation.isCompressionEnabled())) {
DEBUG_BREAK_IF(true); //unsupported
DEBUG_BREAK_IF(true); // unsupported
return;
}

6
shared/source/aub_mem_dump/aub_mem_dump.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2022 Intel Corporation
* Copyright (C) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -321,12 +321,12 @@ struct LrcaHelper {
uint32_t numNoops0 = 3;
uint32_t offsetLRI1 = offsetLRI0 + (1 + numRegsLRI0 * 2 + numNoops0) * sizeof(uint32_t); //offsetLRI == 0x21 * sizeof(uint32_t);
uint32_t offsetLRI1 = offsetLRI0 + (1 + numRegsLRI0 * 2 + numNoops0) * sizeof(uint32_t); // offsetLRI == 0x21 * sizeof(uint32_t);
uint32_t numRegsLRI1 = 9;
uint32_t numNoops1 = 13;
uint32_t offsetLRI2 = offsetLRI1 + (1 + numRegsLRI1 * 2 + numNoops1) * sizeof(uint32_t); //offsetLR2 == 0x41 * sizeof(uint32_t);
uint32_t offsetLRI2 = offsetLRI1 + (1 + numRegsLRI1 * 2 + numNoops1) * sizeof(uint32_t); // offsetLR2 == 0x41 * sizeof(uint32_t);
uint32_t numRegsLRI2 = 1;
uint32_t offsetRingRegisters = offsetLRI0 + (3 * sizeof(uint32_t));

82
shared/source/aub_mem_dump/aub_mem_dump_pvc_and_later.inl
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -170,7 +170,7 @@ const MMIOList AUBFamilyMapper<Family>::globalMMIO = {
MMIOPair(0x0000B098, 0x00300010),
MMIOPair(0x0000B09C, 0x00300010),
//PAT_INDEX
// PAT_INDEX
MMIOPair(0x00004100, 0x0000000),
MMIOPair(0x00004104, 0x0000000),
MMIOPair(0x00004108, 0x0000000),
@@ -180,42 +180,42 @@ const MMIOList AUBFamilyMapper<Family>::globalMMIO = {
MMIOPair(0x00004118, 0x0000000),
MMIOPair(0x0000411c, 0x0000000),
MMIOPair(0x00004b80, 0xffff1001), //GACB_PERF_CTRL_REG
MMIOPair(0x00007000, 0xffff0000), //CACHE_MODE_0
MMIOPair(0x00007004, 0xffff0000), //CACHE_MODE_1
MMIOPair(0x000043F8, 0x00000000), //Gen12 (A-step) chicken bit for AuxT granularity
MMIOPair(0x00009008, 0x00000200), //IDICR
MMIOPair(0x0000900c, 0x00001b40), //SNPCR
MMIOPair(0x0000b120, 0x14000002), //LTCDREG
MMIOPair(0x00042080, 0x00000000), //CHICKEN_MISC_1
MMIOPair(0x000020D4, 0xFFFF0000), //Chicken bit for CSFE
MMIOPair(0x0000B0A0, 0x00000000), //SCRATCH 2 for LNCF unit
MMIOPair(0x000094D4, 0x00000000), //Slice unit Level Clock Gating Control
MMIOPair(0x00004b80, 0xffff1001), // GACB_PERF_CTRL_REG
MMIOPair(0x00007000, 0xffff0000), // CACHE_MODE_0
MMIOPair(0x00007004, 0xffff0000), // CACHE_MODE_1
MMIOPair(0x000043F8, 0x00000000), // Gen12 (A-step) chicken bit for AuxT granularity
MMIOPair(0x00009008, 0x00000200), // IDICR
MMIOPair(0x0000900c, 0x00001b40), // SNPCR
MMIOPair(0x0000b120, 0x14000002), // LTCDREG
MMIOPair(0x00042080, 0x00000000), // CHICKEN_MISC_1
MMIOPair(0x000020D4, 0xFFFF0000), // Chicken bit for CSFE
MMIOPair(0x0000B0A0, 0x00000000), // SCRATCH 2 for LNCF unit
MMIOPair(0x000094D4, 0x00000000), // Slice unit Level Clock Gating Control
// Capture Perf MMIO register programming
MMIOPair(0x0000B004, 0x2FC0100B), //KM_ARBITER_CTRL_REG
MMIOPair(0x0000B404, 0x00000160), //KM_GLOBAL_INVALIDATION_REG
MMIOPair(0x00008708, 0x00000000), //KM_GEN12_IDI_CONTROL_REGISTER
MMIOPair(0x0000B004, 0x2FC0100B), // KM_ARBITER_CTRL_REG
MMIOPair(0x0000B404, 0x00000160), // KM_GLOBAL_INVALIDATION_REG
MMIOPair(0x00008708, 0x00000000), // KM_GEN12_IDI_CONTROL_REGISTER
// Tiled Resources VA Translation Table L3 Pointer
MMIOPair(0x00004410, 0xffffffff), //GEN12_TRTT_NULL_TILE_REG
MMIOPair(0x00004414, 0xfffffffe), //GEN12_TRTT_INVD_TILE_REG
MMIOPair(0x00004404, 0x000000ff), //GEN12_TRTT_VA_MASKDATA_REG
MMIOPair(0x00004408, 0x00000000), //LDWORD GMM_GEN12_TRTT_L3_POINTER
MMIOPair(0x0000440C, 0x00000000), //UDWORD GMM_GEN12_TRTT_L3_POINTER
MMIOPair(0x00004400, 0x00000001), //GEN12_TRTT_TABLE_CONTROL
MMIOPair(0x00004DFC, 0x00000000), //GEN9_TR_CHICKEN_BIT_VECTOR
MMIOPair(0x00004410, 0xffffffff), // GEN12_TRTT_NULL_TILE_REG
MMIOPair(0x00004414, 0xfffffffe), // GEN12_TRTT_INVD_TILE_REG
MMIOPair(0x00004404, 0x000000ff), // GEN12_TRTT_VA_MASKDATA_REG
MMIOPair(0x00004408, 0x00000000), // LDWORD GMM_GEN12_TRTT_L3_POINTER
MMIOPair(0x0000440C, 0x00000000), // UDWORD GMM_GEN12_TRTT_L3_POINTER
MMIOPair(0x00004400, 0x00000001), // GEN12_TRTT_TABLE_CONTROL
MMIOPair(0x00004DFC, 0x00000000), // GEN9_TR_CHICKEN_BIT_VECTOR
};
static const MMIOList mmioListRCS = {
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x00002058), 0x00000000), //CTX_WA_PTR_RCSUNIT
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000020a8), 0x00000000), //IMR
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x00002058), 0x00000000), // CTX_WA_PTR_RCSUNIT
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000020a8), 0x00000000), // IMR
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
MMIOPair(0x00002090, 0xffff0000), //CHICKEN_PWR_CTX_RASTER_1
MMIOPair(0x000020e0, 0xffff4000), //FF_SLICE_CS_CHICKEN1_RCSUNIT
MMIOPair(0x000020e4, 0xffff0000), //FF_SLICE_CS_CHICKEN2_RCSUNIT
MMIOPair(0x000020ec, 0xffff0051), //CS_DEBUG_MODE1
MMIOPair(0x00002090, 0xffff0000), // CHICKEN_PWR_CTX_RASTER_1
MMIOPair(0x000020e0, 0xffff4000), // FF_SLICE_CS_CHICKEN1_RCSUNIT
MMIOPair(0x000020e4, 0xffff0000), // FF_SLICE_CS_CHICKEN2_RCSUNIT
MMIOPair(0x000020ec, 0xffff0051), // CS_DEBUG_MODE1
// FORCE_TO_NONPRIV
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024d0), 0x00007014),
@@ -231,31 +231,31 @@ static const MMIOList mmioListRCS = {
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024f8), 0x0000e000),
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024fc), 0x0000e000),
MMIOPair(0x00002580, 0xffff0005), //CS_CHICKEN1
MMIOPair(0x0000e194, 0xffff0002), //CHICKEN_SAMPLER_2
MMIOPair(0x00002580, 0xffff0005), // CS_CHICKEN1
MMIOPair(0x0000e194, 0xffff0002), // CHICKEN_SAMPLER_2
MMIOPair(0x0000B134, 0xA0000000) //L3ALLOCREG
MMIOPair(0x0000B134, 0xA0000000) // L3ALLOCREG
};
static const MMIOList mmioListBCS = {
MMIOPair(AubMemDump::computeRegisterOffset(bcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(bcs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
};
static const MMIOList mmioListVCS = {
MMIOPair(AubMemDump::computeRegisterOffset(vcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(vcs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
};
static const MMIOList mmioListVECS = {
MMIOPair(AubMemDump::computeRegisterOffset(vecs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(vecs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
};
static MMIOList mmioListCCSInstance(uint32_t mmioBase) {
MMIOList mmioList;
mmioList.push_back(MMIOPair(0x0000ce90, 0x00030003)); //GFX_MULT_CTXT_CTL - enable multi-context with 4CCS
mmioList.push_back(MMIOPair(0x0000b170, 0x00030003)); //MULT_CTXT_CTL - enable multi-context with 4CCS
mmioList.push_back(MMIOPair(0x00014800, 0xFFFF0001)); //RCU_MODE
mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x0000229c), 0xffff8280)); //GFX_MODE
mmioList.push_back(MMIOPair(0x0000ce90, 0x00030003)); // GFX_MULT_CTXT_CTL - enable multi-context with 4CCS
mmioList.push_back(MMIOPair(0x0000b170, 0x00030003)); // MULT_CTXT_CTL - enable multi-context with 4CCS
mmioList.push_back(MMIOPair(0x00014800, 0xFFFF0001)); // RCU_MODE
mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x0000229c), 0xffff8280)); // GFX_MODE
// FORCE_TO_NONPRIV
mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024d0), 0x0000e000));
@@ -271,7 +271,7 @@ static MMIOList mmioListCCSInstance(uint32_t mmioBase) {
mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024f8), 0x0000e000));
mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024fc), 0x0000e000));
mmioList.push_back(MMIOPair(0x0000B234, 0xA0000000)); //L3ALLOCREG_CCS0
mmioList.push_back(MMIOPair(0x0000B234, 0xA0000000)); // L3ALLOCREG_CCS0
return mmioList;
};

82
shared/source/aub_mem_dump/aub_mem_dump_xehp_and_later.inl
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -152,7 +152,7 @@ const MMIOList AUBFamilyMapper<Family>::globalMMIO = {
MMIOPair(0x0000B098, 0x00300010),
MMIOPair(0x0000B09C, 0x00300010),
//PAT_INDEX
// PAT_INDEX
MMIOPair(0x00004100, 0x0000000),
MMIOPair(0x00004104, 0x0000000),
MMIOPair(0x00004108, 0x0000000),
@@ -162,42 +162,42 @@ const MMIOList AUBFamilyMapper<Family>::globalMMIO = {
MMIOPair(0x00004118, 0x0000000),
MMIOPair(0x0000411c, 0x0000000),
MMIOPair(0x00004b80, 0xffff1001), //GACB_PERF_CTRL_REG
MMIOPair(0x00007000, 0xffff0000), //CACHE_MODE_0
MMIOPair(0x00007004, 0xffff0000), //CACHE_MODE_1
MMIOPair(0x000043F8, 0x00000000), //Gen12 (A-step) chicken bit for AuxT granularity
MMIOPair(0x00009008, 0x00000200), //IDICR
MMIOPair(0x0000900c, 0x00001b40), //SNPCR
MMIOPair(0x0000b120, 0x14000002), //LTCDREG
MMIOPair(0x00042080, 0x00000000), //CHICKEN_MISC_1
MMIOPair(0x000020D4, 0xFFFF0000), //Chicken bit for CSFE
MMIOPair(0x0000B0A0, 0x00000000), //SCRATCH 2 for LNCF unit
MMIOPair(0x000094D4, 0x00000000), //Slice unit Level Clock Gating Control
MMIOPair(0x00004b80, 0xffff1001), // GACB_PERF_CTRL_REG
MMIOPair(0x00007000, 0xffff0000), // CACHE_MODE_0
MMIOPair(0x00007004, 0xffff0000), // CACHE_MODE_1
MMIOPair(0x000043F8, 0x00000000), // Gen12 (A-step) chicken bit for AuxT granularity
MMIOPair(0x00009008, 0x00000200), // IDICR
MMIOPair(0x0000900c, 0x00001b40), // SNPCR
MMIOPair(0x0000b120, 0x14000002), // LTCDREG
MMIOPair(0x00042080, 0x00000000), // CHICKEN_MISC_1
MMIOPair(0x000020D4, 0xFFFF0000), // Chicken bit for CSFE
MMIOPair(0x0000B0A0, 0x00000000), // SCRATCH 2 for LNCF unit
MMIOPair(0x000094D4, 0x00000000), // Slice unit Level Clock Gating Control
// Capture Perf MMIO register programming
MMIOPair(0x0000B004, 0x2FC0100B), //KM_ARBITER_CTRL_REG
MMIOPair(0x0000B404, 0x00000160), //KM_GLOBAL_INVALIDATION_REG
MMIOPair(0x00008708, 0x00000000), //KM_GEN12_IDI_CONTROL_REGISTER
MMIOPair(0x0000B004, 0x2FC0100B), // KM_ARBITER_CTRL_REG
MMIOPair(0x0000B404, 0x00000160), // KM_GLOBAL_INVALIDATION_REG
MMIOPair(0x00008708, 0x00000000), // KM_GEN12_IDI_CONTROL_REGISTER
// Tiled Resources VA Translation Table L3 Pointer
MMIOPair(0x00004410, 0xffffffff), //GEN12_TRTT_NULL_TILE_REG
MMIOPair(0x00004414, 0xfffffffe), //GEN12_TRTT_INVD_TILE_REG
MMIOPair(0x00004404, 0x000000ff), //GEN12_TRTT_VA_MASKDATA_REG
MMIOPair(0x00004408, 0x00000000), //LDWORD GMM_GEN12_TRTT_L3_POINTER
MMIOPair(0x0000440C, 0x00000000), //UDWORD GMM_GEN12_TRTT_L3_POINTER
MMIOPair(0x00004400, 0x00000001), //GEN12_TRTT_TABLE_CONTROL
MMIOPair(0x00004DFC, 0x00000000), //GEN9_TR_CHICKEN_BIT_VECTOR
MMIOPair(0x00004410, 0xffffffff), // GEN12_TRTT_NULL_TILE_REG
MMIOPair(0x00004414, 0xfffffffe), // GEN12_TRTT_INVD_TILE_REG
MMIOPair(0x00004404, 0x000000ff), // GEN12_TRTT_VA_MASKDATA_REG
MMIOPair(0x00004408, 0x00000000), // LDWORD GMM_GEN12_TRTT_L3_POINTER
MMIOPair(0x0000440C, 0x00000000), // UDWORD GMM_GEN12_TRTT_L3_POINTER
MMIOPair(0x00004400, 0x00000001), // GEN12_TRTT_TABLE_CONTROL
MMIOPair(0x00004DFC, 0x00000000), // GEN9_TR_CHICKEN_BIT_VECTOR
};
static const MMIOList mmioListRCS = {
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x00002058), 0x00000000), //CTX_WA_PTR_RCSUNIT
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000020a8), 0x00000000), //IMR
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x00002058), 0x00000000), // CTX_WA_PTR_RCSUNIT
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000020a8), 0x00000000), // IMR
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
MMIOPair(0x00002090, 0xffff0000), //CHICKEN_PWR_CTX_RASTER_1
MMIOPair(0x000020e0, 0xffff4000), //FF_SLICE_CS_CHICKEN1_RCSUNIT
MMIOPair(0x000020e4, 0xffff0000), //FF_SLICE_CS_CHICKEN2_RCSUNIT
MMIOPair(0x000020ec, 0xffff0051), //CS_DEBUG_MODE1
MMIOPair(0x00002090, 0xffff0000), // CHICKEN_PWR_CTX_RASTER_1
MMIOPair(0x000020e0, 0xffff4000), // FF_SLICE_CS_CHICKEN1_RCSUNIT
MMIOPair(0x000020e4, 0xffff0000), // FF_SLICE_CS_CHICKEN2_RCSUNIT
MMIOPair(0x000020ec, 0xffff0051), // CS_DEBUG_MODE1
// FORCE_TO_NONPRIV
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024d0), 0x00007014),
@@ -213,31 +213,31 @@ static const MMIOList mmioListRCS = {
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024f8), 0x0000e000),
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024fc), 0x0000e000),
MMIOPair(0x00002580, 0xffff0005), //CS_CHICKEN1
MMIOPair(0x0000e194, 0xffff0002), //CHICKEN_SAMPLER_2
MMIOPair(0x00002580, 0xffff0005), // CS_CHICKEN1
MMIOPair(0x0000e194, 0xffff0002), // CHICKEN_SAMPLER_2
MMIOPair(0x0000B134, 0xA0000000) //L3ALLOCREG
MMIOPair(0x0000B134, 0xA0000000) // L3ALLOCREG
};
static const MMIOList mmioListBCS = {
MMIOPair(AubMemDump::computeRegisterOffset(bcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(bcs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
};
static const MMIOList mmioListVCS = {
MMIOPair(AubMemDump::computeRegisterOffset(vcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(vcs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
};
static const MMIOList mmioListVECS = {
MMIOPair(AubMemDump::computeRegisterOffset(vecs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(vecs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
};
static MMIOList mmioListCCSInstance(uint32_t mmioBase) {
MMIOList mmioList;
mmioList.push_back(MMIOPair(0x0000ce90, 0x00030003)); //GFX_MULT_CTXT_CTL - enable multi-context with 4CCS
mmioList.push_back(MMIOPair(0x0000b170, 0x00030003)); //MULT_CTXT_CTL - enable multi-context with 4CCS
mmioList.push_back(MMIOPair(0x00014800, 0xFFFF0001)); //RCU_MODE
mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x0000229c), 0xffff8280)); //GFX_MODE
mmioList.push_back(MMIOPair(0x0000ce90, 0x00030003)); // GFX_MULT_CTXT_CTL - enable multi-context with 4CCS
mmioList.push_back(MMIOPair(0x0000b170, 0x00030003)); // MULT_CTXT_CTL - enable multi-context with 4CCS
mmioList.push_back(MMIOPair(0x00014800, 0xFFFF0001)); // RCU_MODE
mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x0000229c), 0xffff8280)); // GFX_MODE
// FORCE_TO_NONPRIV
mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024d0), 0x0000e000));
@@ -253,7 +253,7 @@ static MMIOList mmioListCCSInstance(uint32_t mmioBase) {
mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024f8), 0x0000e000));
mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024fc), 0x0000e000));
mmioList.push_back(MMIOPair(0x0000B234, 0xA0000000)); //L3ALLOCREG_CCS0
mmioList.push_back(MMIOPair(0x0000B234, 0xA0000000)); // L3ALLOCREG_CCS0
return mmioList;
};

4
shared/source/command_container/implicit_scaling.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -28,7 +28,7 @@ bool ImplicitScalingHelper::isImplicitScalingEnabled(const DeviceBitfield &devic
if (DebugManager.flags.EnableWalkerPartition.get() != -1) {
partitionWalker = !!DebugManager.flags.EnableWalkerPartition.get();
}
//we can't do this without local memory
// we can't do this without local memory
partitionWalker &= OSInterface::osEnableLocalMemory;
return partitionWalker;

10
shared/source/command_stream/aub_command_stream_receiver.cpp
View File

@@ -117,8 +117,8 @@ bool AubFileStream::init(uint32_t stepping, uint32_t device) {
header.metal = 0;
header.device = device;
header.csxSwizzling = CmdServicesMemTraceVersion::CsxSwizzlingValues::Disabled;
//Which recording method used:
// Phys is required for GGTT memory to be written directly to phys vs through aperture.
// Which recording method used:
// Phys is required for GGTT memory to be written directly to phys vs through aperture.
header.recordingMethod = CmdServicesMemTraceVersion::RecordingMethodValues::Phy;
header.pch = CmdServicesMemTraceVersion::PchValues::Default;
header.captureTool = CmdServicesMemTraceVersion::CaptureToolValues::GenKmdCapture;
@@ -141,7 +141,7 @@ void AubFileStream::writeMemory(uint64_t physAddress, const void *memory, size_t
auto sizeRemainder = size % sizeof(uint32_t);
if (sizeRemainder) {
//if input size is not 4 byte aligned, write extra zeros to AUB
// if input size is not 4 byte aligned, write extra zeros to AUB
uint32_t zero = 0;
write(reinterpret_cast<char *>(&zero), sizeof(uint32_t) - sizeRemainder);
}
@@ -263,7 +263,7 @@ void AubFileStream::expectMemory(uint64_t physAddress, const void *memory, size_
auto remainder = sizeThisIteration & (sizeof(uint32_t) - 1);
if (remainder) {
//if size is not 4 byte aligned, write extra zeros to AUB
// if size is not 4 byte aligned, write extra zeros to AUB
uint32_t zero = 0;
write(reinterpret_cast<char *>(&zero), sizeof(uint32_t) - remainder);
}
@@ -289,7 +289,7 @@ bool AubFileStream::addComment(const char *message) {
write(message, messageLen);
auto remainder = messageLen & (sizeof(uint32_t) - 1);
if (remainder) {
//if size is not 4 byte aligned, write extra zeros to AUB
// if size is not 4 byte aligned, write extra zeros to AUB
uint32_t zero = 0;
write(reinterpret_cast<char *>(&zero), sizeof(uint32_t) - remainder);
}

4
shared/source/command_stream/aub_command_stream_receiver_hw_base.inl
View File

@@ -607,7 +607,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::pollForCompletionImpl() {
const uint32_t mask = getMaskAndValueForPollForCompletion();
const uint32_t value = mask;
stream->registerPoll(
AubMemDump::computeRegisterOffset(mmioBase, 0x2234), //EXECLIST_STATUS
AubMemDump::computeRegisterOffset(mmioBase, 0x2234), // EXECLIST_STATUS
mask,
value,
pollNotEqual,
@@ -712,7 +712,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::writeMMIO(uint32_t offset, uint32_t
template <typename GfxFamily>
void AUBCommandStreamReceiverHw<GfxFamily>::expectMMIO(uint32_t mmioRegister, uint32_t expectedValue) {
if (hardwareContextController) {
//Add support for expectMMIO to AubStream
// Add support for expectMMIO to AubStream
return;
}
this->getAubStream()->expectMMIO(mmioRegister, expectedValue);

8
shared/source/command_stream/command_stream_receiver_simulated_common_hw_xehp_and_later.inl
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -22,16 +22,16 @@ void CommandStreamReceiverSimulatedCommonHw<GfxFamily>::initGlobalMMIO() {
}
if (this->localMemoryEnabled) {
MMIOPair guCntl = {0x00101010, 0x00000080}; //GU_CNTL
MMIOPair guCntl = {0x00101010, 0x00000080}; // GU_CNTL
stream->writeMMIO(guCntl.first, guCntl.second);
MMIOPair lmemCfg = {0x0000cf58, 0x80000000}; //LMEM_CFG
MMIOPair lmemCfg = {0x0000cf58, 0x80000000}; // LMEM_CFG
stream->writeMMIO(lmemCfg.first, lmemCfg.second);
MMIOPair tileAddrRange[] = {{0x00004900, 0x0001},
{0x00004904, 0x0001},
{0x00004908, 0x0001},
{0x0000490c, 0x0001}}; //XEHP_TILE_ADDR_RANGE
{0x0000490c, 0x0001}}; // XEHP_TILE_ADDR_RANGE
const uint32_t numberOfTiles = 4;
const uint32_t localMemorySizeGB = static_cast<uint32_t>(AubHelper::getPerTileLocalMemorySize(&this->peekHwInfo()) / MemoryConstants::gigaByte);

10
shared/source/command_stream/experimental_command_buffer.inl
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -38,15 +38,15 @@ size_t ExperimentalCommandBuffer::programExperimentalCommandBuffer() {
size_t returnOffset = currentStream->getUsed();
//begin timestamp
// begin timestamp
addTimeStampPipeControl<GfxFamily>();
addExperimentalCommands<GfxFamily>();
//end timestamp
// end timestamp
addTimeStampPipeControl<GfxFamily>();
//end
// end
auto pCmd = currentStream->getSpaceForCmd<MI_BATCH_BUFFER_END>();
*pCmd = GfxFamily::cmdInitBatchBufferEnd;
@@ -80,7 +80,7 @@ void ExperimentalCommandBuffer::addTimeStampPipeControl() {
*commandStreamReceiver->peekExecutionEnvironment().rootDeviceEnvironments[commandStreamReceiver->getRootDeviceIndex()]->getHardwareInfo(),
args);
//moving to next chunk
// moving to next chunk
timestampsOffset += sizeof(uint64_t);
DEBUG_BREAK_IF(timestamps->getUnderlyingBufferSize() < timestampsOffset);

10
shared/source/command_stream/scratch_space_controller_base.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -61,14 +61,14 @@ uint64_t ScratchSpaceControllerBase::calculateNewGSH() {
return gsh;
}
uint64_t ScratchSpaceControllerBase::getScratchPatchAddress() {
//for 32 bit scratch space pointer is being programmed in Media VFE State and is relative to 0 as General State Base Address
//for 64 bit, scratch space pointer is being programmed as "General State Base Address - scratchSpaceOffsetFor64bit"
// and "0 + scratchSpaceOffsetFor64bit" is being programmed in Media VFE state
// for 32 bit scratch space pointer is being programmed in Media VFE State and is relative to 0 as General State Base Address
// for 64 bit, scratch space pointer is being programmed as "General State Base Address - scratchSpaceOffsetFor64bit"
// and "0 + scratchSpaceOffsetFor64bit" is being programmed in Media VFE state
uint64_t scratchAddress = 0;
if (scratchAllocation) {
scratchAddress = scratchAllocation->getGpuAddressToPatch();
if (is64bit && !getMemoryManager()->peekForce32BitAllocations()) {
//this is to avoid scractch allocation offset "0"
// this is to avoid scractch allocation offset "0"
scratchAddress = ScratchSpaceConstants::scratchSpaceOffsetFor64Bit;
}
}

4
shared/source/direct_submission/windows/wddm_direct_submission.inl
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2022 Intel Corporation
* Copyright (C) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -50,7 +50,7 @@ WddmDirectSubmission<GfxFamily, Dispatcher>::~WddmDirectSubmission() {
template <typename GfxFamily, typename Dispatcher>
bool WddmDirectSubmission<GfxFamily, Dispatcher>::allocateOsResources() {
//for now only WDDM2.0
// for now only WDDM2.0
UNRECOVERABLE_IF(wddm->getWddmVersion() != WddmVersion::WDDM_2_0);
bool ret = wddm->getWddmInterface()->createMonitoredFence(ringFence);

52
shared/source/gen12lp/aub_mem_dump_gen12lp.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2022 Intel Corporation
* Copyright (C) 2019-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -147,7 +147,7 @@ const MMIOList AUBFamilyMapper<Family>::globalMMIO = {
MMIOPair(0x0000B098, 0x00300010),
MMIOPair(0x0000B09C, 0x00300010),
//PAT_INDEX
// PAT_INDEX
MMIOPair(0x00004100, 0x0000000),
MMIOPair(0x00004104, 0x0000000),
MMIOPair(0x00004108, 0x0000000),
@@ -157,24 +157,24 @@ const MMIOList AUBFamilyMapper<Family>::globalMMIO = {
MMIOPair(0x00004118, 0x0000000),
MMIOPair(0x0000411c, 0x0000000),
MMIOPair(0x00004b80, 0xffff1001), //GACB_PERF_CTRL_REG
MMIOPair(0x00007000, 0xffff0000), //CACHE_MODE_0
MMIOPair(0x00007004, 0xffff0000), //CACHE_MODE_1
MMIOPair(0x00009008, 0x00000200), //IDICR
MMIOPair(0x0000900c, 0x00001b40), //SNPCR
MMIOPair(0x0000b120, 0x14000002), //LTCDREG
MMIOPair(0x00042080, 0x00000000), //CHICKEN_MISC_1
MMIOPair(0x00004b80, 0xffff1001), // GACB_PERF_CTRL_REG
MMIOPair(0x00007000, 0xffff0000), // CACHE_MODE_0
MMIOPair(0x00007004, 0xffff0000), // CACHE_MODE_1
MMIOPair(0x00009008, 0x00000200), // IDICR
MMIOPair(0x0000900c, 0x00001b40), // SNPCR
MMIOPair(0x0000b120, 0x14000002), // LTCDREG
MMIOPair(0x00042080, 0x00000000), // CHICKEN_MISC_1
};
static const MMIOList mmioListRCS = {
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x00002058), 0x00000000), //CTX_WA_PTR_RCSUNIT
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000020a8), 0x00000000), //IMR
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x00002058), 0x00000000), // CTX_WA_PTR_RCSUNIT
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000020a8), 0x00000000), // IMR
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
MMIOPair(0x00002090, 0xffff0000), //CHICKEN_PWR_CTX_RASTER_1
MMIOPair(0x000020e0, 0xffff4000), //FF_SLICE_CS_CHICKEN1_RCSUNIT
MMIOPair(0x000020e4, 0xffff0000), //FF_SLICE_CS_CHICKEN2_RCSUNIT
MMIOPair(0x000020ec, 0xffff0051), //CS_DEBUG_MODE1
MMIOPair(0x00002090, 0xffff0000), // CHICKEN_PWR_CTX_RASTER_1
MMIOPair(0x000020e0, 0xffff4000), // FF_SLICE_CS_CHICKEN1_RCSUNIT
MMIOPair(0x000020e4, 0xffff0000), // FF_SLICE_CS_CHICKEN2_RCSUNIT
MMIOPair(0x000020ec, 0xffff0051), // CS_DEBUG_MODE1
// FORCE_TO_NONPRIV
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024d0), 0x00007014),
@@ -190,28 +190,28 @@ static const MMIOList mmioListRCS = {
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024f8), 0x0000e000),
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024fc), 0x0000e000),
MMIOPair(0x00002580, 0xffff0005), //CS_CHICKEN1
MMIOPair(0x0000e194, 0xffff0002), //CHICKEN_SAMPLER_2
MMIOPair(0x00002580, 0xffff0005), // CS_CHICKEN1
MMIOPair(0x0000e194, 0xffff0002), // CHICKEN_SAMPLER_2
MMIOPair(0x0000B134, 0xD0000020) //L3ALLOCREG
MMIOPair(0x0000B134, 0xD0000020) // L3ALLOCREG
};
static const MMIOList mmioListBCS = {
MMIOPair(AubMemDump::computeRegisterOffset(bcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(bcs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
};
static const MMIOList mmioListVCS = {
MMIOPair(AubMemDump::computeRegisterOffset(vcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(vcs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
};
static const MMIOList mmioListVECS = {
MMIOPair(AubMemDump::computeRegisterOffset(vecs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(AubMemDump::computeRegisterOffset(vecs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
};
static const MMIOList mmioListCCS = {
MMIOPair(0x0000ce90, 0x00010001), //GFX_MULT_CTXT_CTL
MMIOPair(0x00014800, 0x00010001), //RCU_MODE
MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE
MMIOPair(0x0000ce90, 0x00010001), // GFX_MULT_CTXT_CTL
MMIOPair(0x00014800, 0x00010001), // RCU_MODE
MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x0000229c), 0xffff8280), // GFX_MODE
// FORCE_TO_NONPRIV
MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024d0), 0x00007014),
@@ -227,7 +227,7 @@ static const MMIOList mmioListCCS = {
MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024f8), 0x0000e000),
MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024fc), 0x0000e000),
MMIOPair(0x0000B234, 0xD0000020) //L3ALLOCREG_CCS0
MMIOPair(0x0000B234, 0xD0000020) // L3ALLOCREG_CCS0
};
const MMIOList *AUBFamilyMapper<Family>::perEngineMMIO[aub_stream::NUM_ENGINES] = {

4
shared/source/gen12lp/command_stream_receiver_simulated_common_hw_gen12lp.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2022 Intel Corporation
* Copyright (C) 2019-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -17,7 +17,7 @@ void CommandStreamReceiverSimulatedCommonHw<Family>::initGlobalMMIO() {
}
if (this->isLocalMemoryEnabled()) {
MMIOPair lmemCfg = {0x0000cf58, 0x80000000}; //LMEM_CFG
MMIOPair lmemCfg = {0x0000cf58, 0x80000000}; // LMEM_CFG
stream->writeMMIO(lmemCfg.first, lmemCfg.second);
}
}

4
shared/source/gen8/hw_cmds_base.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -15,7 +15,7 @@
#include <cstddef>
#include <cstring>
//forward declaration for parsing logic
// forward declaration for parsing logic
template <class T>
struct CmdParse;

4
shared/source/generated/xe_hp_core/hw_cmds_generated_xe_hp_core.inl
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -5685,7 +5685,7 @@ typedef struct tagMI_ARB_CHECK {
}
inline void setPreFetchDisable(const uint32_t value) {
TheStructure.Common.Pre_FetchDisable = value;
TheStructure.Common.MaskBits = 1 << 0; //PreFetchDisable is at bit0, so set bit0 of mask to 1
TheStructure.Common.MaskBits = 1 << 0; // PreFetchDisable is at bit0, so set bit0 of mask to 1
}
inline uint32_t getPreFetchDisable() const {
return TheStructure.Common.Pre_FetchDisable;

4
shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -6011,7 +6011,7 @@ typedef struct tagMI_ARB_CHECK {
}
inline void setPreParserDisable(const bool value) {
TheStructure.Common.PreParserDisable = value;
TheStructure.Common.MaskBits = 1 << 0; //PreParserDisable is at bit0, so set bit0 of mask to 1
TheStructure.Common.MaskBits = 1 << 0; // PreParserDisable is at bit0, so set bit0 of mask to 1
}
inline bool getPreParserDisable() const {
return TheStructure.Common.PreParserDisable;

4
shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -5768,7 +5768,7 @@ typedef struct tagMI_ARB_CHECK {
}
inline void setPreFetchDisable(const uint32_t value) {
TheStructure.Common.Pre_FetchDisable = value;
TheStructure.Common.MaskBits = 1 << 0; //PreFetchDisable is at bit0, so set bit0 of mask to 1
TheStructure.Common.MaskBits = 1 << 0; // PreFetchDisable is at bit0, so set bit0 of mask to 1
}
inline uint32_t getPreFetchDisable() const {
return TheStructure.Common.Pre_FetchDisable;

6
shared/source/helpers/basic_math.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -106,11 +106,11 @@ inline uint16_t float2Half(float f) {
uint32_t fsign = (u.u >> 16) & 0x8000;
float x = std::fabs(f);
//Nan
// Nan
if (x != x) {
u.u >>= (24 - 11);
u.u &= 0x7fff;
u.u |= 0x0200; //silence the NaN
u.u |= 0x0200; // silence the NaN
return u.u | fsign;
}

4
shared/source/helpers/hw_walk_order.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2022 Intel Corporation
* Copyright (C) 2022-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -12,7 +12,7 @@
namespace NEO {
namespace HwWalkOrderHelper {
//make sure table below matches Hardware Spec
// make sure table below matches Hardware Spec
inline constexpr uint32_t walkOrderPossibilties = 6u;
inline constexpr uint8_t X = 0;
inline constexpr uint8_t Y = 1;

6
shared/source/helpers/register_offsets.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2022 Intel Corporation
* Copyright (C) 2019-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -14,7 +14,7 @@ inline constexpr uint32_t L3SQC_REG4 = 0xB118;
inline constexpr uint32_t GPGPU_WALKER_COOKIE_VALUE_BEFORE_WALKER = 0xFFFFFFFF;
inline constexpr uint32_t GPGPU_WALKER_COOKIE_VALUE_AFTER_WALKER = 0x00000000;
//Threads Dimension X/Y/Z
// Threads Dimension X/Y/Z
inline constexpr uint32_t GPUGPU_DISPATCHDIMX = 0x2500;
inline constexpr uint32_t GPUGPU_DISPATCHDIMY = 0x2504;
inline constexpr uint32_t GPUGPU_DISPATCHDIMZ = 0x2508;
@@ -42,7 +42,7 @@ inline constexpr uint32_t CS_PREDICATE_RESULT = 0x2418;
inline constexpr uint32_t CS_PREDICATE_RESULT_2 = 0x23BC;
inline constexpr uint32_t SEMA_WAIT_POLL = 0x0224c;
//Alu opcodes
// Alu opcodes
inline constexpr uint32_t NUM_ALU_INST_FOR_READ_MODIFY_WRITE = 4;
enum class AluRegisters : uint32_t {

24
shared/source/helpers/uint16_avx2.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -28,7 +28,7 @@ struct uint16x16_t {
}
uint16x16_t(uint16_t a) {
value = _mm256_set1_epi16(a); //AVX
value = _mm256_set1_epi16(a); // AVX
}
explicit uint16x16_t(const void *alignedPtr) {
@@ -54,33 +54,33 @@ struct uint16x16_t {
inline void load(const void *alignedPtr) {
DEBUG_BREAK_IF(!isAligned<32>(alignedPtr));
value = _mm256_load_si256(reinterpret_cast<const __m256i *>(alignedPtr)); //AVX
value = _mm256_load_si256(reinterpret_cast<const __m256i *>(alignedPtr)); // AVX
}
inline void loadUnaligned(const void *ptr) {
value = _mm256_loadu_si256(reinterpret_cast<const __m256i *>(ptr)); //AVX
value = _mm256_loadu_si256(reinterpret_cast<const __m256i *>(ptr)); // AVX
}
inline void store(void *alignedPtr) {
DEBUG_BREAK_IF(!isAligned<32>(alignedPtr));
_mm256_store_si256(reinterpret_cast<__m256i *>(alignedPtr), value); //AVX
_mm256_store_si256(reinterpret_cast<__m256i *>(alignedPtr), value); // AVX
}
inline void storeUnaligned(void *ptr) {
_mm256_storeu_si256(reinterpret_cast<__m256i *>(ptr), value); //AVX
_mm256_storeu_si256(reinterpret_cast<__m256i *>(ptr), value); // AVX
}
inline operator bool() const {
return _mm256_testz_si256(value, mask().value) ? false : true; //AVX
return _mm256_testz_si256(value, mask().value) ? false : true; // AVX
}
inline uint16x16_t &operator-=(const uint16x16_t &a) {
value = _mm256_sub_epi16(value, a.value); //AVX2
value = _mm256_sub_epi16(value, a.value); // AVX2
return *this;
}
inline uint16x16_t &operator+=(const uint16x16_t &a) {
value = _mm256_add_epi16(value, a.value); //AVX2
value = _mm256_add_epi16(value, a.value); // AVX2
return *this;
}
@@ -88,13 +88,13 @@ struct uint16x16_t {
uint16x16_t result;
result.value =
_mm256_xor_si256(mask().value,
_mm256_cmpgt_epi16(b.value, a.value)); //AVX2
_mm256_cmpgt_epi16(b.value, a.value)); // AVX2
return result;
}
inline friend uint16x16_t operator&&(const uint16x16_t &a, const uint16x16_t &b) {
uint16x16_t result;
result.value = _mm256_and_si256(a.value, b.value); //AVX2
result.value = _mm256_and_si256(a.value, b.value); // AVX2
return result;
}
@@ -104,7 +104,7 @@ struct uint16x16_t {
// Have to swap arguments to get intended calling semantics
result.value =
_mm256_blendv_epi8(b.value, a.value, mask.value); //AVX2
_mm256_blendv_epi8(b.value, a.value, mask.value); // AVX2
return result;
}
};

24
shared/source/helpers/uint16_sse4.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -31,7 +31,7 @@ struct uint16x8_t {
}
uint16x8_t(uint16_t a) {
value = _mm_set1_epi16(a); //SSE2
value = _mm_set1_epi16(a); // SSE2
}
explicit uint16x8_t(const void *alignedPtr) {
@@ -57,33 +57,33 @@ struct uint16x8_t {
inline void load(const void *alignedPtr) {
DEBUG_BREAK_IF(!isAligned<16>(alignedPtr));
value = _mm_load_si128(reinterpret_cast<const __m128i *>(alignedPtr)); //SSE2
value = _mm_load_si128(reinterpret_cast<const __m128i *>(alignedPtr)); // SSE2
}
inline void loadUnaligned(const void *ptr) {
value = _mm_loadu_si128(reinterpret_cast<const __m128i *>(ptr)); //SSE2
value = _mm_loadu_si128(reinterpret_cast<const __m128i *>(ptr)); // SSE2
}
inline void store(void *alignedPtr) {
DEBUG_BREAK_IF(!isAligned<16>(alignedPtr));
_mm_store_si128(reinterpret_cast<__m128i *>(alignedPtr), value); //SSE2
_mm_store_si128(reinterpret_cast<__m128i *>(alignedPtr), value); // SSE2
}
inline void storeUnaligned(void *ptr) {
_mm_storeu_si128(reinterpret_cast<__m128i *>(ptr), value); //SSE2
_mm_storeu_si128(reinterpret_cast<__m128i *>(ptr), value); // SSE2
}
inline operator bool() const {
return _mm_test_all_zeros(value, mask().value) ? false : true; //SSE4.1 alternatives?
return _mm_test_all_zeros(value, mask().value) ? false : true; // SSE4.1 alternatives?
}
inline uint16x8_t &operator-=(const uint16x8_t &a) {
value = _mm_sub_epi16(value, a.value); //SSE2
value = _mm_sub_epi16(value, a.value); // SSE2
return *this;
}
inline uint16x8_t &operator+=(const uint16x8_t &a) {
value = _mm_add_epi16(value, a.value); //SSE2
value = _mm_add_epi16(value, a.value); // SSE2
return *this;
}
@@ -91,13 +91,13 @@ struct uint16x8_t {
uint16x8_t result;
result.value =
_mm_xor_si128(mask().value,
_mm_cmplt_epi16(a.value, b.value)); //SSE2
_mm_cmplt_epi16(a.value, b.value)); // SSE2
return result;
}
inline friend uint16x8_t operator&&(const uint16x8_t &a, const uint16x8_t &b) {
uint16x8_t result;
result.value = _mm_and_si128(a.value, b.value); //SSE2
result.value = _mm_and_si128(a.value, b.value); // SSE2
return result;
}
@@ -107,7 +107,7 @@ struct uint16x8_t {
// Have to swap arguments to get intended calling semantics
result.value =
_mm_blendv_epi8(b.value, a.value, mask.value); //SSE4.1 alternatives?
_mm_blendv_epi8(b.value, a.value, mask.value); // SSE4.1 alternatives?
return result;
}
};

4
shared/source/helpers/x86_64/local_id_gen.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -43,7 +43,7 @@ LocalIDHelper::LocalIDHelper() {
LocalIDHelper LocalIDHelper::initializer;
//traditional function to generate local IDs
// traditional function to generate local IDs
void generateLocalIDs(void *buffer, uint16_t simd, const std::array<uint16_t, 3> &localWorkgroupSize, const std::array<uint8_t, 3> &dimensionsOrder, bool isImageOnlyKernel, uint32_t grfSize) {
auto threadsPerWorkGroup = static_cast<uint16_t>(getThreadsPerWG(simd, localWorkgroupSize[0] * localWorkgroupSize[1] * localWorkgroupSize[2]));
bool useLayoutForImages = isImageOnlyKernel && isCompatibleWithLayoutForImages(localWorkgroupSize, dimensionsOrder, simd);

4
shared/source/os_interface/linux/engine_info.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2022 Intel Corporation
* Copyright (C) 2022-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -143,7 +143,7 @@ void EngineInfo::setSupportedEnginesInfo(const RootDeviceEnvironment &rootDevice
uint32_t EngineInfo::getEngineTileIndex(const EngineClassInstance &engine) {
uint32_t tile = 0;
if (tileToEngineMap.empty()) {
return tile; //Empty map
return tile; // Empty map
}
for (auto itr = tileToEngineMap.begin(); itr != tileToEngineMap.end(); itr++) {

4
shared/source/os_interface/linux/local/dg1/ioctl_helper_dg1.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -26,7 +26,7 @@ uint32_t IoctlHelperImpl<gfxProduct>::createGemExt(const MemRegionsVec &memClass
if (ret == 0) {
return ret;
}
//fallback to PROD_DG1 kernel
// fallback to PROD_DG1 kernel
handle = 0u;
uint32_t regionsSize = static_cast<uint32_t>(memClassInstances.size());
std::vector<drm_i915_gem_memory_class_instance> regions(regionsSize);

6
shared/source/os_interface/os_context.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -121,7 +121,7 @@ bool OsContext::checkDirectSubmissionSupportsEngine(const DirectSubmissionProper
startOnInit = renderOverrideKey == 1 ? true : false;
}
} else {
//assume else is CCS
// assume else is CCS
int32_t computeOverrideKey = DebugManager.flags.DirectSubmissionOverrideComputeSupport.get();
if (computeOverrideKey != -1) {
supported = computeOverrideKey == 0 ? false : true;
@@ -129,7 +129,7 @@ bool OsContext::checkDirectSubmissionSupportsEngine(const DirectSubmissionProper
}
}
//enable start in context only when default support is overridden and enabled
// enable start in context only when default support is overridden and enabled
if (supported && !directSubmissionProperty.engineSupported) {
startInContext = true;
}

6
shared/source/page_fault_manager/windows/cpu_page_fault_manager_windows.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Intel Corporation
* Copyright (C) 2019-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -23,11 +23,11 @@ PageFaultManagerWindows::PageFaultManagerWindows() {
pageFaultHandler = [this](struct _EXCEPTION_POINTERS *exceptionInfo) {
if (exceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION) {
if (this->verifyPageFault(reinterpret_cast<void *>(exceptionInfo->ExceptionRecord->ExceptionInformation[1]))) {
//this is our fault that we serviced, continue app execution
// this is our fault that we serviced, continue app execution
return EXCEPTION_CONTINUE_EXECUTION;
}
}
//not our exception
// not our exception
return EXCEPTION_CONTINUE_SEARCH;
};

4
shared/source/xe_hpc_core/command_stream_receiver_hw_xe_hpc_core.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -76,7 +76,7 @@ void BlitCommandsHelper<Family>::appendBlitCommandsMemCopy(const BlitProperties
}
auto cachePolicy = GMM_RESOURCE_USAGE_OCL_BUFFER;
//if transfer size bigger then L3 size, copy with L3 disabled
// if transfer size bigger then L3 size, copy with L3 disabled
if (blitProperites.copySize.x * blitProperites.copySize.y * blitProperites.copySize.z * blitProperites.bytesPerPixel >= (rootDeviceEnvironment.getHardwareInfo()->gtSystemInfo.L3CacheSizeInKb * KB / 2)) {
cachePolicy = GMM_RESOURCE_USAGE_OCL_BUFFER_CACHELINE_MISALIGNED;
}

4
shared/test/common/helpers/memory_management.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -272,7 +272,7 @@ size_t enumerateLeak(size_t indexAllocationTop, size_t indexDeallocationTop, boo
if (eventDeallocation.address == eventAllocation.address &&
eventDeallocation.event != AllocationEvent::EVENT_UNKNOWN) {
//this memory was once freed, now it is allocated but not freed
// this memory was once freed, now it is allocated but not freed
if (requireCallStack && eventDeallocation.frames == 0) {
potentialLeak = true;
potentialLeakIndex = currentIndex;

22
shared/test/common/libult/linux/drm_mock.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -215,34 +215,34 @@ class DrmMock : public Drm {
bool queryPageFaultSupportCalled = false;
//DRM_IOCTL_I915_GEM_EXECBUFFER2
// DRM_IOCTL_I915_GEM_EXECBUFFER2
std::vector<MockExecBuffer> execBuffers{};
std::vector<MockExecObject> receivedBos{};
int execBufferResult = 0;
//DRM_IOCTL_I915_GEM_CREATE
// DRM_IOCTL_I915_GEM_CREATE
uint64_t createParamsSize = 0;
uint32_t createParamsHandle = 0;
//DRM_IOCTL_I915_GEM_SET_TILING
// DRM_IOCTL_I915_GEM_SET_TILING
uint32_t setTilingMode = 0;
uint32_t setTilingHandle = 0;
uint32_t setTilingStride = 0;
//DRM_IOCTL_PRIME_FD_TO_HANDLE
// DRM_IOCTL_PRIME_FD_TO_HANDLE
uint32_t outputHandle = 0;
int32_t inputFd = 0;
int fdToHandleRetVal = 0;
//DRM_IOCTL_HANDLE_TO_FD
// DRM_IOCTL_HANDLE_TO_FD
int32_t outputFd = 0;
bool incrementOutputFdAfterCall = false;
//DRM_IOCTL_I915_GEM_USERPTR
// DRM_IOCTL_I915_GEM_USERPTR
uint32_t returnHandle = 0;
uint64_t gpuMemSize = 3u * MemoryConstants::gigaByte;
//DRM_IOCTL_I915_QUERY
// DRM_IOCTL_I915_QUERY
QueryItem storedQueryItem = {};
//DRM_IOCTL_I915_GEM_WAIT
// DRM_IOCTL_I915_GEM_WAIT
GemWait receivedGemWait = {};
//DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT
// DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT
uint32_t storedDrmContextId{};
//DRM_IOCTL_GEM_CLOSE
// DRM_IOCTL_GEM_CLOSE
int storedRetValForGemClose = 0;
GemVmControl receivedGemVmControl{};

4
shared/test/common/mocks/mock_elf.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -118,7 +118,7 @@ struct MockElfEncoder : public NEO::Elf::ElfEncoder<NumBits> {
auto symTabSectionHeader = elfEncoder.getSectionHeader(symTabSectionIndex);
symTabSectionHeader->info = 2;
symTabSectionHeader->link = elfEncoder.getLastSectionHeaderIndex() + 1; //strtab section added as last
symTabSectionHeader->link = elfEncoder.getLastSectionHeaderIndex() + 1; // strtab section added as last
return elfEncoder.encode();
}
};

30
shared/test/common/os_interface/linux/device_command_stream_fixture.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -170,45 +170,45 @@ class DrmMockCustom : public Drm {
std::atomic<int> ioctl_res;
std::atomic<IoctlResExt *> ioctl_res_ext;
//DRM_IOCTL_I915_GEM_EXECBUFFER2
// DRM_IOCTL_I915_GEM_EXECBUFFER2
NEO::MockExecBuffer execBuffer{};
//First exec object
// First exec object
NEO::MockExecObject execBufferBufferObjects{};
//DRM_IOCTL_I915_GEM_CREATE
// DRM_IOCTL_I915_GEM_CREATE
uint64_t createParamsSize = 0;
uint32_t createParamsHandle = 0;
//DRM_IOCTL_I915_GEM_SET_TILING
// DRM_IOCTL_I915_GEM_SET_TILING
uint32_t setTilingMode = 0;
uint32_t setTilingHandle = 0;
uint32_t setTilingStride = 0;
//DRM_IOCTL_I915_GEM_GET_TILING
// DRM_IOCTL_I915_GEM_GET_TILING
uint32_t getTilingModeOut = 0;
uint32_t getTilingHandleIn = 0;
//DRM_IOCTL_PRIME_FD_TO_HANDLE
// DRM_IOCTL_PRIME_FD_TO_HANDLE
uint32_t outputHandle = 0;
int32_t inputFd = 0;
//DRM_IOCTL_PRIME_HANDLE_TO_FD
// DRM_IOCTL_PRIME_HANDLE_TO_FD
uint32_t inputHandle = 0;
int32_t outputFd = 0;
bool incrementOutputFdAfterCall = false;
int32_t inputFlags = 0;
//DRM_IOCTL_I915_GEM_USERPTR
// DRM_IOCTL_I915_GEM_USERPTR
uint32_t returnHandle = 0;
//DRM_IOCTL_I915_GEM_SET_DOMAIN
// DRM_IOCTL_I915_GEM_SET_DOMAIN
uint32_t setDomainHandle = 0;
uint32_t setDomainReadDomains = 0;
uint32_t setDomainWriteDomain = 0;
//DRM_IOCTL_I915_GETPARAM
// DRM_IOCTL_I915_GETPARAM
NEO::GetParam recordedGetParam = {0};
int getParamRetValue = 0;
//DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
// DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
NEO::GemContextParam recordedGetContextParam = {0};
uint64_t getContextParamRetValue = 0;
//DRM_IOCTL_I915_GEM_WAIT
// DRM_IOCTL_I915_GEM_WAIT
int64_t gemWaitTimeout = 0;
//DRM_IOCTL_I915_GEM_MMAP_OFFSET
// DRM_IOCTL_I915_GEM_MMAP_OFFSET
uint32_t mmapOffsetHandle = 0;
uint32_t mmapOffsetPad = 0;
uint64_t mmapOffsetExpected = 0;
@@ -216,7 +216,7 @@ class DrmMockCustom : public Drm {
bool failOnMmapOffset = false;
bool failOnPrimeFdToHandle = false;
//DRM_IOCTL_I915_GEM_CREATE_EXT
// DRM_IOCTL_I915_GEM_CREATE_EXT
uint64_t createExtSize = 0;
uint32_t createExtHandle = 0;
uint64_t createExtExtensions = 0;

8
shared/test/common/os_interface/linux/device_command_stream_fixture_context.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2022 Intel Corporation
* Copyright (C) 2022-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -10,16 +10,16 @@
#include "shared/test/common/libult/linux/drm_mock_prelim_context.h"
struct DrmMockCustomPrelimContext {
//PRELIM_DRM_IOCTL_I915_GEM_CREATE_EXT
// PRELIM_DRM_IOCTL_I915_GEM_CREATE_EXT
uint64_t createExtSize = 0;
uint32_t createExtHandle = 0;
uint64_t createExtExtensions = 0;
//PRELIM_DRM_IOCTL_I915_GEM_WAIT_USER_FENCE
// PRELIM_DRM_IOCTL_I915_GEM_WAIT_USER_FENCE
WaitUserFence receivedGemWaitUserFence{};
uint32_t gemWaitUserFenceCalled = 0;
//PRELIM_DRM_I915_GEM_EXECBUFFER_EXT_USER_FENCE
// PRELIM_DRM_I915_GEM_EXECBUFFER_EXT_USER_FENCE
uint64_t completionAddress = 0;
uint64_t completionValue = 0;

8
shared/test/common/os_interface/linux/drm_command_stream_fixture.h
View File

@@ -35,7 +35,7 @@ class DrmCommandStreamTest : public ::testing::Test {
template <typename GfxFamily>
void setUpT() {
//make sure this is disabled, we don't want to test this now
// make sure this is disabled, we don't want to test this now
DebugManager.flags.EnableForcePin.set(false);
mock = new DrmMock(mockFd, *executionEnvironment.rootDeviceEnvironments[0]);
@@ -68,7 +68,7 @@ class DrmCommandStreamTest : public ::testing::Test {
// Memory manager creates pinBB with ioctl, expect one call
EXPECT_EQ(1u, mock->ioctlCallsCount);
//assert we have memory manager
// assert we have memory manager
ASSERT_NE(nullptr, memoryManager);
mock->ioctlCount.reset();
mock->ioctlTearDownExpected.reset();
@@ -118,7 +118,7 @@ class DrmCommandStreamEnhancedTemplate : public ::testing::Test {
executionEnvironment->incRefInternal();
executionEnvironment->initGmm();
this->dbgState = std::make_unique<DebugManagerStateRestore>();
//make sure this is disabled, we don't want to test this now
// make sure this is disabled, we don't want to test this now
DebugManager.flags.EnableForcePin.set(false);
mock = new DrmType(*executionEnvironment->rootDeviceEnvironments[rootDeviceIndex]);
@@ -199,7 +199,7 @@ class DrmCommandStreamEnhancedWithFailingExecTemplate : public ::testing::Test {
executionEnvironment->incRefInternal();
executionEnvironment->initGmm();
this->dbgState = std::make_unique<DebugManagerStateRestore>();
//make sure this is disabled, we don't want to test this now
// make sure this is disabled, we don't want to test this now
DebugManager.flags.EnableForcePin.set(false);
mock = new T(*executionEnvironment->rootDeviceEnvironments[rootDeviceIndex]);

4
shared/test/common/os_interface/linux/drm_memory_manager_fixture.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2022 Intel Corporation
* Copyright (C) 2019-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -62,7 +62,7 @@ void DrmMemoryManagerFixture::setUp(DrmMockCustom *mock, bool localMemoryEnabled
memoryManager = new (std::nothrow) TestedDrmMemoryManager(localMemoryEnabled, false, false, *executionEnvironment);
executionEnvironment->memoryManager.reset(memoryManager);
//assert we have memory manager
// assert we have memory manager
ASSERT_NE(nullptr, memoryManager);
if (memoryManager->getgemCloseWorker()) {
memoryManager->getgemCloseWorker()->close(true);

10
shared/test/unit_test/compiler_interface/compiler_cache_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2022 Intel Corporation
* Copyright (C) 2019-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -36,13 +36,13 @@ TEST(HashGeneration, givenMisalignedBufferWhenPassedToUpdateFunctionThenProperPt
char *misalignedPtr = (char *)originalPtr;
misalignedPtr++;
//values really used
// values really used
misalignedPtr[0] = 1;
misalignedPtr[1] = 2;
misalignedPtr[2] = 3;
misalignedPtr[3] = 4;
misalignedPtr[4] = 5;
//values not used should be ommitted
// values not used should be ommitted
misalignedPtr[5] = 6;
misalignedPtr[6] = 7;
@@ -82,9 +82,9 @@ TEST(HashGeneration, givenMisalignedBufferWithSizeOneWhenPassedToUpdateFunctionT
char *misalignedPtr = (char *)originalPtr;
misalignedPtr++;
//values really used
// values really used
misalignedPtr[0] = 1;
//values not used should be ommitted
// values not used should be ommitted
misalignedPtr[1] = 2;
misalignedPtr[2] = 3;
misalignedPtr[3] = 4;

6
shared/test/unit_test/device_binary_format/elf/elf_decoder_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2022 Intel Corporation
* Copyright (C) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -120,7 +120,7 @@ class TestElf {
auto symTabSectionHeader = elfEncoder.getSectionHeader(symTabSectionIndex);
symTabSectionHeader->info = 4; // one greater than last LOCAL symbol
symTabSectionHeader->link = elfEncoder.getLastSectionHeaderIndex() + 1; //strtab section added as last
symTabSectionHeader->link = elfEncoder.getLastSectionHeaderIndex() + 1; // strtab section added as last
return elfEncoder.encode();
}
const int64_t relaAddend = 16;
@@ -477,7 +477,7 @@ TEST(ElfDecoder, WhenElfContainsInvalidSymbolSectionHeaderThenDecodingFailsAndEr
sectionHeader0.type = SECTION_HEADER_TYPE::SHT_SYMTAB;
sectionHeader0.size = sizeof(sectionHeader0);
sectionHeader0.offset = header.shOff;
sectionHeader0.entsize = sizeof(ElfSymbolEntry<EI_CLASS_64>) + 4; //invalid entSize
sectionHeader0.entsize = sizeof(ElfSymbolEntry<EI_CLASS_64>) + 4; // invalid entSize
storage.insert(storage.end(), reinterpret_cast<const uint8_t *>(&sectionHeader0), reinterpret_cast<const uint8_t *>(&sectionHeader0 + 1));

4
shared/test/unit_test/direct_submission/windows/wddm_direct_submission_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2022 Intel Corporation
* Copyright (C) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -188,7 +188,7 @@ HWTEST_F(WddmDirectSubmissionTest, givenWddmWhenAllocateOsResourcesResidencyFail
}
EXPECT_EQ(0u, wddmMockInterface->createMonitoredFenceCalled);
//expect 2 makeResident calls, due to fail on 1st and then retry (which also fails)
// expect 2 makeResident calls, due to fail on 1st and then retry (which also fails)
EXPECT_EQ(2u, wddm->makeResidentResult.called);
EXPECT_EQ(expectedAllocationsCnt, wddm->makeResidentResult.handleCount);
}

4
shared/test/unit_test/encoders/test_encode_dispatch_kernel_dg2_and_later.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -81,7 +81,7 @@ HWTEST2_F(CommandEncodeStatesTestDg2AndLater, GivenVariousSlmTotalSizesAndSettin
{0, PREFERRED_SLM_ALLOCATION_SIZE::PREFERRED_SLM_ALLOCATION_SIZE_0K},
{16 * KB, PREFERRED_SLM_ALLOCATION_SIZE::PREFERRED_SLM_ALLOCATION_SIZE_16K},
{32 * KB, PREFERRED_SLM_ALLOCATION_SIZE::PREFERRED_SLM_ALLOCATION_SIZE_32K},
//since we can't set 48KB as SLM size for workgroup, we need to ask for 64KB here.
// since we can't set 48KB as SLM size for workgroup, we need to ask for 64KB here.
{64 * KB, PREFERRED_SLM_ALLOCATION_SIZE::PREFERRED_SLM_ALLOCATION_SIZE_64K},
};

6
shared/test/unit_test/encoders/walker_partition_tests_pvc_and_later.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -61,10 +61,10 @@ HWTEST2_F(WalkerPartitionPvcAndLaterTests, givenProgramBatchBufferStartCommandWh
EXPECT_EQ(expectedUsedSize, totalBytesProgrammed);
if (gfxCoreFamily == IGFX_XE_HPC_CORE) {
//bits 57-63 are zeroed
// bits 57-63 are zeroed
EXPECT_EQ((gpuAddress & 0x1FFFFFFFFFFFFFF), batchBufferStart->getBatchBufferStartAddress());
} else {
//bits 48-63 are zeroed
// bits 48-63 are zeroed
EXPECT_EQ((gpuAddress & 0xFFFFFFFFFFFF), batchBufferStart->getBatchBufferStartAddress());
}
EXPECT_TRUE(batchBufferStart->getPredicationEnable());

14
shared/test/unit_test/encoders/walker_partition_tests_xehp_and_later_1.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -89,7 +89,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenWalkerPartitionWhenConst
auto batchBufferStart = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
ASSERT_NE(nullptr, batchBufferStart);
EXPECT_TRUE(batchBufferStart->getPredicationEnable());
//address routes to WALKER section which is before control section
// address routes to WALKER section which is before control section
auto address = batchBufferStart->getBatchBufferStartAddress();
EXPECT_EQ(address, gpuVirtualAddress + expectedCommandUsedSize - walkerSectionCommands);
parsedOffset += sizeof(WalkerPartition::BATCH_BUFFER_START<FamilyType>);
@@ -125,7 +125,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenWalkerPartitionWhenConst
parsedOffset += sizeof(WalkerPartition::MI_SEMAPHORE_WAIT<FamilyType>);
//final batch buffer start that routes at the end of the batch buffer
// final batch buffer start that routes at the end of the batch buffer
auto batchBufferStartFinal = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
EXPECT_NE(nullptr, batchBufferStartFinal);
EXPECT_EQ(batchBufferStartFinal->getBatchBufferStartAddress(), gpuVirtualAddress + optionalBatchBufferEndOffset);
@@ -1115,7 +1115,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenDebugModesForWalkerParti
auto batchBufferStart = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
ASSERT_NE(nullptr, batchBufferStart);
EXPECT_TRUE(batchBufferStart->getPredicationEnable());
//address routes to WALKER section which is before control section
// address routes to WALKER section which is before control section
auto address = batchBufferStart->getBatchBufferStartAddress();
EXPECT_EQ(address, gpuVirtualAddress + expectedCommandUsedSize - walkerSectionCommands);
parsedOffset += sizeof(WalkerPartition::BATCH_BUFFER_START<FamilyType>);
@@ -1144,7 +1144,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenDebugModesForWalkerParti
miSemaphoreWait = genCmdCast<WalkerPartition::MI_SEMAPHORE_WAIT<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
}
//final batch buffer start that routes at the end of the batch buffer
// final batch buffer start that routes at the end of the batch buffer
auto batchBufferStartFinal = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
EXPECT_NE(nullptr, batchBufferStartFinal);
EXPECT_EQ(batchBufferStartFinal->getBatchBufferStartAddress(), gpuVirtualAddress + optionalBatchBufferEndOffset);
@@ -1336,7 +1336,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenStaticPartitionIsPreferr
auto batchBufferStart = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
ASSERT_NE(nullptr, batchBufferStart);
EXPECT_TRUE(batchBufferStart->getPredicationEnable());
//address routes to WALKER section which is before control section
// address routes to WALKER section which is before control section
auto address = batchBufferStart->getBatchBufferStartAddress();
EXPECT_EQ(address, gpuVirtualAddress + expectedCommandUsedSize - walkerSectionCommands);
parsedOffset += sizeof(WalkerPartition::BATCH_BUFFER_START<FamilyType>);
@@ -1374,7 +1374,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenStaticPartitionIsPreferr
EXPECT_EQ(wparidCCSOffset, loadRegisterMem->getRegisterAddress());
parsedOffset += sizeof(WalkerPartition::LOAD_REGISTER_MEM<FamilyType>);
//final batch buffer start that routes at the end of the batch buffer
// final batch buffer start that routes at the end of the batch buffer
auto batchBufferStartFinal = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
EXPECT_NE(nullptr, batchBufferStartFinal);
EXPECT_EQ(batchBufferStartFinal->getBatchBufferStartAddress(), gpuVirtualAddress + totalProgrammedSize);

20
shared/test/unit_test/encoders/walker_partition_tests_xehp_and_later_2.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -309,7 +309,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenMiAtomicWhenItIsProgramm
EXPECT_FALSE(miAtomic->getWorkloadPartitionIdOffsetEnable());
auto memoryAddress = UnitTestHelper<FamilyType>::getAtomicMemoryAddress(*miAtomic);
//bits 48-63 are zeroed
// bits 48-63 are zeroed
EXPECT_EQ((gpuAddress & 0xFFFFFFFFFFFF), memoryAddress);
}
@@ -381,7 +381,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenProgramBatchBufferStartC
ASSERT_NE(nullptr, batchBufferStart);
EXPECT_EQ(expectedUsedSize, totalBytesProgrammed);
//bits 48-63 are zeroed
// bits 48-63 are zeroed
EXPECT_EQ((gpuAddress & 0xFFFFFFFFFFFF), batchBufferStart->getBatchBufferStartAddress());
EXPECT_TRUE(batchBufferStart->getPredicationEnable());
@@ -427,7 +427,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenProgramComputeWalkerWhen
EXPECT_EQ(COMPUTE_WALKER<FamilyType>::PARTITION_TYPE::PARTITION_TYPE_Z, walkerCommand->getPartitionType());
EXPECT_EQ(6u, walkerCommand->getPartitionSize());
//if we program with partition Count == 1 then do not trigger partition stuff
// if we program with partition Count == 1 then do not trigger partition stuff
walker.setPartitionType(COMPUTE_WALKER<FamilyType>::PARTITION_TYPE::PARTITION_TYPE_DISABLED);
walkerCommandAddress = cmdBufferAddress;
programPartitionedWalker<FamilyType>(cmdBufferAddress, totalBytesProgrammed, &walker, 1u, false);
@@ -919,7 +919,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenSelfCleanupSectionWhenDe
auto batchBufferStart = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
ASSERT_NE(nullptr, batchBufferStart);
EXPECT_TRUE(batchBufferStart->getPredicationEnable());
//address routes to WALKER section which is before control section
// address routes to WALKER section which is before control section
auto address = batchBufferStart->getBatchBufferStartAddress();
EXPECT_EQ(address, gpuVirtualAddress + expectedCommandUsedSize - walkerSectionCommands);
parsedOffset += sizeof(WalkerPartition::BATCH_BUFFER_START<FamilyType>);
@@ -961,7 +961,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenSelfCleanupSectionWhenDe
parsedOffset += sizeof(WalkerPartition::MI_SEMAPHORE_WAIT<FamilyType>);
//final batch buffer start that routes at the end of the batch buffer
// final batch buffer start that routes at the end of the batch buffer
auto batchBufferStartFinal = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
ASSERT_NE(nullptr, batchBufferStartFinal);
EXPECT_EQ(batchBufferStartFinal->getBatchBufferStartAddress(), gpuVirtualAddress + cleanupSectionOffset);
@@ -1123,7 +1123,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenSelfCleanupAndAtomicsUse
auto batchBufferStart = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
ASSERT_NE(nullptr, batchBufferStart);
EXPECT_TRUE(batchBufferStart->getPredicationEnable());
//address routes to WALKER section which is before control section
// address routes to WALKER section which is before control section
auto address = batchBufferStart->getBatchBufferStartAddress();
EXPECT_EQ(address, gpuVirtualAddress + expectedCommandUsedSize - walkerSectionCommands);
parsedOffset += sizeof(WalkerPartition::BATCH_BUFFER_START<FamilyType>);
@@ -1166,7 +1166,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenSelfCleanupAndAtomicsUse
parsedOffset += sizeof(WalkerPartition::MI_SEMAPHORE_WAIT<FamilyType>);
//final batch buffer start that routes at the end of the batch buffer
// final batch buffer start that routes at the end of the batch buffer
auto batchBufferStartFinal = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
ASSERT_NE(nullptr, batchBufferStartFinal);
EXPECT_EQ(batchBufferStartFinal->getBatchBufferStartAddress(), gpuVirtualAddress + cleanupSectionOffset);
@@ -1329,7 +1329,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenDynamicPartitioningWhenP
auto batchBufferStart = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
ASSERT_NE(nullptr, batchBufferStart);
EXPECT_TRUE(batchBufferStart->getPredicationEnable());
//address routes to WALKER section which is before control section
// address routes to WALKER section which is before control section
auto address = batchBufferStart->getBatchBufferStartAddress();
EXPECT_EQ(address, gpuVirtualAddress + expectedCommandUsedSize - walkerSectionCommands);
parsedOffset += sizeof(WalkerPartition::BATCH_BUFFER_START<FamilyType>);
@@ -1340,7 +1340,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, WalkerPartitionTests, givenDynamicPartitioningWhenP
EXPECT_EQ(miSetPredicate->getPredicateEnable(), MI_SET_PREDICATE<FamilyType>::PREDICATE_ENABLE::PREDICATE_ENABLE_PREDICATE_DISABLE);
parsedOffset += sizeof(WalkerPartition::MI_SET_PREDICATE<FamilyType>);
//final batch buffer start that routes at the end of the batch buffer
// final batch buffer start that routes at the end of the batch buffer
auto batchBufferStartFinal = genCmdCast<WalkerPartition::BATCH_BUFFER_START<FamilyType> *>(ptrOffset(cmdBuffer, parsedOffset));
ASSERT_NE(nullptr, batchBufferStartFinal);
EXPECT_EQ(batchBufferStartFinal->getBatchBufferStartAddress(), gpuVirtualAddress + cleanupSectionOffset);

10
shared/test/unit_test/helpers/flattened_id_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -251,7 +251,7 @@ INSTANTIATE_TEST_CASE_P(AllCombinations, FlattenedIDFixture, ::testing::Combine(
// NOTE: You'll need a unique test prefix
INSTANTIATE_TEST_CASE_P(SingleTest, FlattenedIDFixture,
::testing::Combine(
::testing::Values(32), //SIMD
::testing::Values(5), //LWSX
::testing::Values(6), //LWSY
::testing::Values(7))); //LWSZ
::testing::Values(32), // SIMD
::testing::Values(5), // LWSX
::testing::Values(6), // LWSY
::testing::Values(7))); // LWSZ

4
shared/test/unit_test/helpers/flush_stamp_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -46,7 +46,7 @@ TEST(FlushStampTest, WhenSettingStampValueThenItIsSet) {
TEST(FlushStampTest, WhenReplacingStampObjectThenRefCountIsUpdated) {
FlushStampTracker flushStampTracker(true);
EXPECT_EQ(1, flushStampTracker.getStampReference()->getRefInternalCount()); //obj to release
EXPECT_EQ(1, flushStampTracker.getStampReference()->getRefInternalCount()); // obj to release
auto stampObj = new FlushStampTrackingObj();
EXPECT_EQ(0, stampObj->getRefInternalCount()); // no owner

12
shared/test/unit_test/helpers/local_id_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -488,8 +488,8 @@ INSTANTIATE_TEST_CASE_P(LayoutForImagesTests, LocalIdsLayoutForImagesTest, ::tes
// NOTE: You'll need a unique test prefix
INSTANTIATE_TEST_CASE_P(SingleTest, LocalIDFixture,
::testing::Combine(
::testing::Values(32), //SIMD
::testing::Values(32), //GRF
::testing::Values(5), //LWSX
::testing::Values(6), //LWSY
::testing::Values(7))); //LWSZ
::testing::Values(32), // SIMD
::testing::Values(32), // GRF
::testing::Values(5), // LWSX
::testing::Values(6), // LWSY
::testing::Values(7))); // LWSZ

10
shared/test/unit_test/helpers/string_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -16,9 +16,9 @@ TEST(StringHelpers, GivenParamsWhenUsingStrncpyThenReturnIsCorrect) {
char dst[1024] = "";
char src[1024] = "HelloWorld";
//preconditions
// preconditions
ASSERT_EQ(sizeof(dst), sizeof(src));
//String must be smaller than array capacity
// String must be smaller than array capacity
ASSERT_LT(strlen(src), sizeof(src));
auto ret = strncpy_s(nullptr, 1024, src, 1024);
@@ -147,9 +147,9 @@ TEST(StringHelpers, GivenParamsWhenUsingMemcpyThenReturnIsCorrect) {
char dst[1024] = "";
char src[1024] = "HelloWorld";
//preconditions
// preconditions
ASSERT_EQ(sizeof(dst), sizeof(src));
//String must be smaller than array capacity
// String must be smaller than array capacity
ASSERT_LT(strlen(src), sizeof(src));
auto ret = memcpy_s(nullptr, sizeof(dst), src, sizeof(src));

8
shared/test/unit_test/main.cpp
View File

@@ -90,16 +90,16 @@ void applyWorkarounds() {
ss >> val;
}
//intialize rand
// intialize rand
srand(static_cast<unsigned int>(time(nullptr)));
//Create at least on thread to prevent false memory leaks in tests using threads
// Create at least on thread to prevent false memory leaks in tests using threads
std::thread t([&]() {
});
tempThreadID = t.get_id();
t.join();
//Create FileLogger to prevent false memory leaks
// Create FileLogger to prevent false memory leaks
{
NEO::fileLoggerInstance();
}
@@ -184,7 +184,7 @@ int main(int argc, char **argv) {
dumpTestStats = true;
++i;
dumpTestStatsFileName = std::string(argv[i]);
} else if (!strcmp("--disable_pagefaulting_tests", argv[i])) { //disable tests which raise page fault signal during execution
} else if (!strcmp("--disable_pagefaulting_tests", argv[i])) { // disable tests which raise page fault signal during execution
NEO::PagaFaultManagerTestConfig::disabled = true;
} else if (!strcmp("--tbx", argv[i])) {
if (testMode == TestMode::AubTests) {

4
shared/test/unit_test/memory_manager/deferrable_allocation_deletion_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -166,7 +166,7 @@ TEST_F(DeferrableAllocationDeletionTest, givenNotUsedAllocationWhenApplyDeletion
EXPECT_FALSE(allocation->isUsed());
EXPECT_EQ(0u, memoryManager->freeGraphicsMemoryCalled);
while (!asyncDeleter->doWorkInBackground)
std::this_thread::yield(); //wait for start async thread work
std::this_thread::yield(); // wait for start async thread work
std::unique_lock<std::mutex> lock(asyncDeleter->queueMutex);
asyncDeleter->allowExit = true;
lock.unlock();

6
shared/test/unit_test/memory_manager/host_ptr_manager_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -433,7 +433,7 @@ TEST_F(HostPtrManagerTest, GivenHostPtrFilledWith3TripleFragmentsWhenAskedForPop
ASSERT_EQ(3u, reqs.requiredFragmentsCount);
FragmentStorage fragments[maxFragmentsCount];
//check all fragments
// check all fragments
for (int i = 0; i < maxFragmentsCount; i++) {
fragments[i].fragmentCpuPointer = const_cast<void *>(reqs.allocationFragments[i].allocationPtr);
fragments[i].fragmentSize = reqs.allocationFragments[i].allocationSize;
@@ -701,7 +701,7 @@ TEST_F(HostPtrManagerTest, GivenHostPtrManagerFilledWithBigFragmentWhenAskedForF
EXPECT_EQ(OverlapStatus::FRAGMENT_NOT_OVERLAPING_WITH_ANY_OTHER, overlapStatus);
EXPECT_EQ(nullptr, oustideFragment);
//partialOverlap
// partialOverlap
auto ptrPartial = (void *)(((uintptr_t)bigPtr + bigSize) - 100);
auto partialBigSize = MemoryConstants::pageSize * 100;

10
shared/test/unit_test/memory_manager/internal_allocation_storage_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -53,26 +53,26 @@ TEST_F(InternalAllocationStorageTest, whenCleanAllocationListThenRemoveOnlyCompl
storage->storeAllocation(std::unique_ptr<GraphicsAllocation>(allocation2), TEMPORARY_ALLOCATION);
storage->storeAllocation(std::unique_ptr<GraphicsAllocation>(allocation3), TEMPORARY_ALLOCATION);
//head point to alloc 2, tail points to alloc3
// head point to alloc 2, tail points to alloc3
EXPECT_TRUE(csr->getTemporaryAllocations().peekContains(*allocation));
EXPECT_TRUE(csr->getTemporaryAllocations().peekContains(*allocation2));
EXPECT_TRUE(csr->getTemporaryAllocations().peekContains(*allocation3));
EXPECT_EQ(-1, verifyDListOrder(csr->getTemporaryAllocations().peekHead(), allocation, allocation2, allocation3));
//now remove element form the middle
// now remove element form the middle
storage->cleanAllocationList(6, TEMPORARY_ALLOCATION);
EXPECT_TRUE(csr->getTemporaryAllocations().peekContains(*allocation));
EXPECT_FALSE(csr->getTemporaryAllocations().peekContains(*allocation2));
EXPECT_TRUE(csr->getTemporaryAllocations().peekContains(*allocation3));
EXPECT_EQ(-1, verifyDListOrder(csr->getTemporaryAllocations().peekHead(), allocation, allocation3));
//now remove head
// now remove head
storage->cleanAllocationList(11, TEMPORARY_ALLOCATION);
EXPECT_FALSE(csr->getTemporaryAllocations().peekContains(*allocation));
EXPECT_FALSE(csr->getTemporaryAllocations().peekContains(*allocation2));
EXPECT_TRUE(csr->getTemporaryAllocations().peekContains(*allocation3));
//now remove tail
// now remove tail
storage->cleanAllocationList(16, TEMPORARY_ALLOCATION);
EXPECT_TRUE(csr->getTemporaryAllocations().peekIsEmpty());
}

32
shared/test/unit_test/memory_manager/multi_graphics_allocation_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2022 Intel Corporation
* Copyright (C) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -124,11 +124,11 @@ struct MultiGraphicsAllocationTests : ::testing::Test {
TEST_F(MultiGraphicsAllocationTests, whenCreatingMultiGraphicsAllocationWithSharedStorageThenMigrationIsNotRequired) {
AllocationProperties allocationProperties{0u,
true, //allocateMemory
true, // allocateMemory
MemoryConstants::pageSize,
AllocationType::BUFFER_HOST_MEMORY,
false, //multiOsContextCapable
false, //isMultiStorageAllocationParam
false, // multiOsContextCapable
false, // isMultiStorageAllocationParam
systemMemoryBitfield};
auto ptr = memoryManager->createMultiGraphicsAllocationInSystemMemoryPool(rootDeviceIndices, allocationProperties, multiGraphicsAllocation);
@@ -147,11 +147,11 @@ TEST_F(MultiGraphicsAllocationTests, whenCreatingMultiGraphicsAllocationWithExis
uint8_t hostPtr[MemoryConstants::pageSize]{};
AllocationProperties allocationProperties{0u,
false, //allocateMemory
false, // allocateMemory
MemoryConstants::pageSize,
AllocationType::BUFFER_HOST_MEMORY,
false, //multiOsContextCapable
false, //isMultiStorageAllocationParam
false, // multiOsContextCapable
false, // isMultiStorageAllocationParam
systemMemoryBitfield};
multiGraphicsAllocation.addAllocation(memoryManager->allocateGraphicsMemoryWithProperties(allocationProperties, hostPtr));
@@ -168,11 +168,11 @@ TEST_F(MultiGraphicsAllocationTests, whenCreatingMultiGraphicsAllocationWithExis
TEST_F(MultiGraphicsAllocationTests, whenCreatingMultiGraphicsAllocationWithSeparatedStorageThenMigrationIsRequired) {
AllocationProperties allocationProperties{0u,
true, //allocateMemory
true, // allocateMemory
MemoryConstants::pageSize,
AllocationType::BUFFER_HOST_MEMORY,
false, //multiOsContextCapable
false, //isMultiStorageAllocationParam
false, // multiOsContextCapable
false, // isMultiStorageAllocationParam
systemMemoryBitfield};
multiGraphicsAllocation.addAllocation(memoryManager->allocateGraphicsMemoryWithProperties(allocationProperties));
@@ -188,11 +188,11 @@ TEST_F(MultiGraphicsAllocationTests, whenCreatingMultiGraphicsAllocationWithSepa
TEST_F(MultiGraphicsAllocationTests, givenMultiGraphicsAllocationThatRequiresMigrationWhenCopyOrMoveMultiGraphicsAllocationThenTheCopyStillRequiresMigration) {
AllocationProperties allocationProperties{0u,
true, //allocateMemory
true, // allocateMemory
MemoryConstants::pageSize,
AllocationType::BUFFER_HOST_MEMORY,
false, //multiOsContextCapable
false, //isMultiStorageAllocationParam
false, // multiOsContextCapable
false, // isMultiStorageAllocationParam
systemMemoryBitfield};
multiGraphicsAllocation.addAllocation(memoryManager->allocateGraphicsMemoryWithProperties(allocationProperties));
@@ -220,11 +220,11 @@ struct MigrationSyncDataTests : public MultiGraphicsAllocationTests {
void SetUp() override {
MultiGraphicsAllocationTests::SetUp();
AllocationProperties allocationProperties{0u,
true, //allocateMemory
true, // allocateMemory
MemoryConstants::pageSize,
AllocationType::BUFFER_HOST_MEMORY,
false, //multiOsContextCapable
false, //isMultiStorageAllocationParam
false, // multiOsContextCapable
false, // isMultiStorageAllocationParam
systemMemoryBitfield};
multiGraphicsAllocation.addAllocation(memoryManager->allocateGraphicsMemoryWithProperties(allocationProperties));

12
shared/test/unit_test/os_interface/linux/drm_buffer_object_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -55,14 +55,14 @@ TEST_F(DrmBufferObjectTest, GivenDetectedGpuHangDuringEvictUnusedAllocationsWhen
}
TEST_F(DrmBufferObjectTest, WhenSettingTilingThenCallSucceeds) {
mock->ioctl_expected.total = 1; //set_tiling
mock->ioctl_expected.total = 1; // set_tiling
auto tilingY = mock->getIoctlHelper()->getDrmParamValue(DrmParam::TilingY);
auto ret = bo->setTiling(tilingY, 0);
EXPECT_TRUE(ret);
}
TEST_F(DrmBufferObjectTest, WhenSettingSameTilingThenCallSucceeds) {
mock->ioctl_expected.total = 0; //set_tiling
mock->ioctl_expected.total = 0; // set_tiling
auto tilingY = mock->getIoctlHelper()->getDrmParamValue(DrmParam::TilingY);
bo->tilingMode = tilingY;
auto ret = bo->setTiling(tilingY, 0);
@@ -70,7 +70,7 @@ TEST_F(DrmBufferObjectTest, WhenSettingSameTilingThenCallSucceeds) {
}
TEST_F(DrmBufferObjectTest, GivenInvalidTilingWhenSettingTilingThenCallFails) {
mock->ioctl_expected.total = 1; //set_tiling
mock->ioctl_expected.total = 1; // set_tiling
auto tilingY = mock->getIoctlHelper()->getDrmParamValue(DrmParam::TilingY);
mock->ioctl_res = -1;
auto ret = bo->setTiling(tilingY, 0);
@@ -91,7 +91,7 @@ TEST_F(DrmBufferObjectTest, givenAddressThatWhenSizeIsAddedCrosses32BitBoundaryW
bo->setAddress(((uint64_t)1u << 32) - 0x1000u);
bo->setSize(0x1000);
bo->fillExecObject(execObject, osContext.get(), 0, 1);
//base address + size > size of 32bit address space
// base address + size > size of 32bit address space
EXPECT_TRUE(execObject.has48BAddressSupportFlag());
}
@@ -102,7 +102,7 @@ TEST_F(DrmBufferObjectTest, givenAddressThatWhenSizeIsAddedWithin32BitBoundaryWh
bo->setAddress(((uint64_t)1u << 32) - 0x1000u);
bo->setSize(0xFFF);
bo->fillExecObject(execObject, osContext.get(), 0, 1);
//base address + size < size of 32bit address space
// base address + size < size of 32bit address space
EXPECT_TRUE(execObject.has48BAddressSupportFlag());
}

4
shared/test/unit_test/os_interface/linux/drm_command_stream_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2022 Intel Corporation
* Copyright (C) 2022-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -16,7 +16,7 @@
namespace NEO {
extern ApiSpecificConfig::ApiType apiTypeForUlts;
} //namespace NEO
} // namespace NEO
using namespace NEO;
HWTEST_TEMPLATED_F(DrmCommandStreamTest, givenL0ApiConfigWhenCreatingDrmCsrThenEnableImmediateDispatch) {

4
shared/test/unit_test/os_interface/linux/drm_command_stream_xehp_and_later_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2022 Intel Corporation
* Copyright (C) 2022-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -163,7 +163,7 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, DrmCommandStreamMultiTileMemExecTest, GivenDrmSuppo
volatile TagAddressType *completionAddress = defaultEngine.commandStreamReceiver->getTagAddress();
completionAddress += (TagAllocationLayout::completionFenceOffset / sizeof(TagAddressType));
*completionAddress = 2; //1st context is ready
*completionAddress = 2; // 1st context is ready
completionAddress += (postSyncOffset / sizeof(TagAddressType));
*completionAddress = 1;

4
shared/test/unit_test/os_interface/linux/drm_memory_manager_localmem_upstream_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2022 Intel Corporation
* Copyright (C) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -653,7 +653,7 @@ TEST_F(DrmMemoryManagerLocalMemoryWithCustomMockTest, givenDrmMemoryManagerWithL
using DrmMemoryManagerFailInjectionTest = Test<DrmMemoryManagerFixtureImpl>;
HWTEST2_F(DrmMemoryManagerFailInjectionTest, givenEnabledLocalMemoryWhenNewFailsThenAllocateInDevicePoolReturnsStatusErrorAndNullallocation, NonDefaultIoctlsSupported) {
mock->ioctl_expected.total = -1; //don't care
mock->ioctl_expected.total = -1; // don't care
class MockGfxPartition : public GfxPartition {
public:
MockGfxPartition() : GfxPartition(reservedCpuAddressRange) {

6
shared/test/unit_test/os_interface/linux/drm_mock_impl.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2022 Intel Corporation
* Copyright (C) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -27,13 +27,13 @@ class DrmTipMock : public DrmMock {
uint32_t i915QuerySuccessCount = std::numeric_limits<uint32_t>::max();
uint32_t queryMemoryRegionInfoSuccessCount = std::numeric_limits<uint32_t>::max();
//DRM_IOCTL_I915_GEM_CREATE_EXT
// DRM_IOCTL_I915_GEM_CREATE_EXT
drm_i915_gem_create_ext createExt{};
MemoryClassInstance memRegions{};
uint32_t numRegions = 0;
int gemCreateExtRetVal = 0;
//DRM_IOCTL_I915_GEM_MMAP_OFFSET
// DRM_IOCTL_I915_GEM_MMAP_OFFSET
__u64 mmapOffsetFlagsReceived = 0;
__u64 offset = 0;
int mmapOffsetRetVal = 0;

4
shared/test/unit_test/os_interface/windows/wddm_command_stream_l0_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2022 Intel Corporation
* Copyright (C) 2022-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -39,7 +39,7 @@
namespace NEO {
extern ApiSpecificConfig::ApiType apiTypeForUlts;
} //namespace NEO
} // namespace NEO
using namespace NEO;
template <typename GfxFamily>

4
shared/test/unit_test/utilities/debug_file_reader_tests.inl
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -134,7 +134,7 @@ TEST(SettingsFileReader, givenHexNumbersSemiColonSeparatedListInInputStreamWhenP
auto reader = std::make_unique<TestSettingsFileReader>();
ASSERT_NE(nullptr, reader);
//No settings should be parsed initially
// No settings should be parsed initially
EXPECT_EQ(0u, reader->getStringSettingsCount());
std::stringstream inputLineWithSemiColonList("KeyName = 0x1234;0x5555");

4
shared/test/unit_test/utilities/heap_allocator_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022 Intel Corporation
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -771,7 +771,7 @@ TEST(HeapAllocatorTest, WhenMemoryIsAllocatedThenAllocationsDoNotOverlap) {
}
}
//at this point we should be able to allocate full size
// at this point we should be able to allocate full size
size_t totalSize = (size_t)(allocatorSize - reqAlignment);
auto finalPtr = heapAllocator->allocate(totalSize);
EXPECT_NE(0llu, finalPtr);

4
shared/test/unit_test/utilities/perf_profiler_tests.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2020-2021 Intel Corporation
* Copyright (C) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -68,7 +68,7 @@ TEST(PerfProfiler, WhenDestroyingAllThenAllObjectsAreDestroyed) {
EXPECT_EQ(0, PerfProfiler::getCurrentCounter());
PerfProfilerMock::addNullObjects(); // skip null objects
EXPECT_EQ(1, PerfProfiler::getCurrentCounter());
PerfProfiler::destroyAll(); //destroy no object although counter is incorrect
PerfProfiler::destroyAll(); // destroy no object although counter is incorrect
EXPECT_EQ(0, PerfProfiler::getCurrentCounter());
EXPECT_EQ(nullptr, PerfProfiler::getObject(0));
}