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Store page entry bits in PageTable entries

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- set Present bit when entry is allocated regardless entry bits passed.

Change-Id: Ib1393927f66c4ed0b577a4df58d2760fbff86df7
This commit is contained in:
Hoppe, Mateusz
2018-09-18 13:17:55 -07:00
committed by sys_ocldev
parent 803a946e3f
commit 4af432ae10
11 changed files with 263 additions and 256 deletions
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43
runtime/memory_manager/page_table.cpp
View File

@@ -1,23 +1,8 @@
/*
* Copyright (c) 2017 - 2018, Intel Corporation
* Copyright (C) 2017-2018 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
* SPDX-License-Identifier: MIT
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "runtime/memory_manager/page_table.h"
@@ -25,24 +10,28 @@
namespace OCLRT {
uintptr_t PTE::map(uintptr_t vm, size_t size, uint32_t memoryBank) {
uintptr_t PTE::map(uintptr_t vm, size_t size, uint64_t entryBits, uint32_t memoryBank) {
const size_t shift = 12;
const uint32_t mask = (1 << bits) - 1;
size_t indexStart = (vm >> shift) & mask;
size_t indexEnd = ((vm + size - 1) >> shift) & mask;
uintptr_t res = -1;
entryBits &= 0xfff;
entryBits |= 0x1;
for (size_t index = indexStart; index <= indexEnd; index++) {
if (entries[index] == 0x0) {
uint64_t tmp = allocator->reservePage(memoryBank);
entries[index] = reinterpret_cast<void *>(tmp | 0x1);
entries[index] = reinterpret_cast<void *>(tmp | entryBits);
} else {
entries[index] = reinterpret_cast<void *>((reinterpret_cast<uintptr_t>(entries[index]) & 0xfffff000u) | entryBits);
}
res = std::min(reinterpret_cast<uintptr_t>(entries[index]) & 0xfffffffeu, res);
res = std::min(reinterpret_cast<uintptr_t>(entries[index]) & 0xfffff000u, res);
}
return (res & ~0x1) + (vm & (pageSize - 1));
return (res & ~entryBits) + (vm & (pageSize - 1));
}
void PTE::pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker, uint32_t memoryBank) {
void PTE::pageWalk(uintptr_t vm, size_t size, size_t offset, uint64_t entryBits, PageWalker &pageWalker, uint32_t memoryBank) {
static const uint32_t bits = 9;
const size_t shift = 12;
const uint32_t mask = (1 << bits) - 1;
@@ -50,16 +39,20 @@ void PTE::pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWal
size_t indexEnd = ((vm + size - 1) >> shift) & mask;
uint64_t res = -1;
uintptr_t rem = vm & (pageSize - 1);
entryBits &= 0xfff;
entryBits |= 0x1;
for (size_t index = indexStart; index <= indexEnd; index++) {
if (entries[index] == 0x0) {
uint64_t tmp = allocator->reservePage(memoryBank);
entries[index] = reinterpret_cast<void *>(tmp | 0x1);
entries[index] = reinterpret_cast<void *>(tmp | entryBits);
} else {
entries[index] = reinterpret_cast<void *>((reinterpret_cast<uintptr_t>(entries[index]) & 0xfffff000u) | entryBits);
}
res = reinterpret_cast<uintptr_t>(entries[index]) & 0xfffffffeu;
res = reinterpret_cast<uintptr_t>(entries[index]) & 0xfffff000u;
size_t lSize = std::min(pageSize - rem, size);
pageWalker((res & ~0x1) + rem, lSize, offset);
pageWalker((res & ~0x1) + rem, lSize, offset, reinterpret_cast<uintptr_t>(entries[index]) & 0xfffu);
size -= lSize;
offset += lSize;

29
runtime/memory_manager/page_table.h
View File

@@ -1,23 +1,8 @@
/*
* Copyright (c) 2017 - 2018, Intel Corporation
* Copyright (C) 2017-2018 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
* SPDX-License-Identifier: MIT
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#pragma once
@@ -44,7 +29,7 @@ class PageTableHelper {
static const uint32_t memoryBankNotSpecified = 0;
};
typedef std::function<void(uint64_t addr, size_t size, size_t offset)> PageWalker;
typedef std::function<void(uint64_t addr, size_t size, size_t offset, uint64_t entryBits)> PageWalker;
template <class T, uint32_t level, uint32_t bits = 9>
class PageTable {
public:
@@ -57,8 +42,8 @@ class PageTable {
delete e;
}
virtual uintptr_t map(uintptr_t vm, size_t size, uint32_t memoryBank);
virtual void pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker, uint32_t memoryBank);
virtual uintptr_t map(uintptr_t vm, size_t size, uint64_t entryBits, uint32_t memoryBank);
virtual void pageWalk(uintptr_t vm, size_t size, size_t offset, uint64_t entryBits, PageWalker &pageWalker, uint32_t memoryBank);
static const size_t pageSize = 1 << 12;
static size_t getBits() {
@@ -78,8 +63,8 @@ class PTE : public PageTable<void, 0u> {
public:
PTE(PhysicalAddressAllocator *physicalAddressAllocator) : PageTable<void, 0u>(physicalAddressAllocator) {}
uintptr_t map(uintptr_t vm, size_t size, uint32_t memoryBank) override;
void pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker, uint32_t memoryBank) override;
uintptr_t map(uintptr_t vm, size_t size, uint64_t entryBits, uint32_t memoryBank) override;
void pageWalk(uintptr_t vm, size_t size, size_t offset, uint64_t entryBits, PageWalker &pageWalker, uint32_t memoryBank) override;
static const uint32_t level = 0;
static const uint32_t bits = 9;

31
runtime/memory_manager/page_table.inl
View File

@@ -1,29 +1,14 @@
/*
* Copyright (c) 2018, Intel Corporation
* Copyright (C) 2018 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
* SPDX-License-Identifier: MIT
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
namespace OCLRT {
template <>
inline uintptr_t PageTable<void, 0, 9>::map(uintptr_t vm, size_t size, uint32_t memoryBank) {
inline uintptr_t PageTable<void, 0, 9>::map(uintptr_t vm, size_t size, uint64_t entryBits, uint32_t memoryBank) {
return 0;
}
@@ -33,11 +18,11 @@ inline size_t PageTable<void, 0, 9>::getBits() {
}
template <>
inline void PageTable<void, 0, 9>::pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker, uint32_t memoryBank) {
inline void PageTable<void, 0, 9>::pageWalk(uintptr_t vm, size_t size, size_t offset, uint64_t entryBits, PageWalker &pageWalker, uint32_t memoryBank) {
}
template <class T, uint32_t level, uint32_t bits>
inline uintptr_t PageTable<T, level, bits>::map(uintptr_t vm, size_t size, uint32_t memoryBank) {
inline uintptr_t PageTable<T, level, bits>::map(uintptr_t vm, size_t size, uint64_t entryBits, uint32_t memoryBank) {
const size_t shift = T::getBits() + 12;
const uintptr_t mask = (1 << bits) - 1;
size_t indexStart = (vm >> shift) & mask;
@@ -55,13 +40,13 @@ inline uintptr_t PageTable<T, level, bits>::map(uintptr_t vm, size_t size, uint3
if (entries[index] == nullptr) {
entries[index] = new T(allocator);
}
res = std::min((entries[index])->map(vmStart, vmEnd - vmStart + 1, memoryBank), res);
res = std::min((entries[index])->map(vmStart, vmEnd - vmStart + 1, entryBits, memoryBank), res);
}
return res;
}
template <class T, uint32_t level, uint32_t bits>
inline void PageTable<T, level, bits>::pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker, uint32_t memoryBank) {
inline void PageTable<T, level, bits>::pageWalk(uintptr_t vm, size_t size, size_t offset, uint64_t entryBits, PageWalker &pageWalker, uint32_t memoryBank) {
const size_t shift = T::getBits() + 12;
const uintptr_t mask = (1 << bits) - 1;
size_t indexStart = (vm >> shift) & mask;
@@ -78,7 +63,7 @@ inline void PageTable<T, level, bits>::pageWalk(uintptr_t vm, size_t size, size_
if (entries[index] == nullptr) {
entries[index] = new T(allocator);
}
entries[index]->pageWalk(vmStart, vmEnd - vmStart + 1, offset, pageWalker, memoryBank);
entries[index]->pageWalk(vmStart, vmEnd - vmStart + 1, offset, entryBits, pageWalker, memoryBank);
offset += (vmEnd - vmStart + 1);
}