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Update i915 prelim headers

Browse Source 
https://github.com/intel-gpu/drm-uapi-helper/releases/tag/v2.0-rc9

Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
This commit is contained in:
Bartosz Dunajski
2022-02-24 11:13:29 +00:00
committed by Compute-Runtime-Automation
parent 292f16d423
commit 4cdc4ff9c8
2 changed files with 206 additions and 28 deletions
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200
third_party/uapi/prelim/drm/i915_drm.h vendored
View File

@@ -623,6 +623,14 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
/*
* Indicates the 2k user priority levels are statically mapped into 3 buckets as
* follows:
*
* -1k to -1 Low priority
* 0 Normal priority
* 1 to 1k Highest priority
*/
#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
#define I915_PARAM_HUC_STATUS 42
@@ -2072,6 +2080,61 @@ struct i915_context_engines_parallel_submit {
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
/**
* DOC: Context Engine Map uAPI
*
* Context engine map is a new way of addressing engines when submitting batch-
* buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
* inside the flags field of `struct drm_i915_gem_execbuffer2`.
*
* To use it created GEM contexts need to be configured with a list of engines
* the user is intending to submit to. This is accomplished using the
* `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
* i915_context_param_engines`.
*
* For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
* configured map.
*
* Example of creating such context and submitting against it:
*
* .. code-block:: C
*
* I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
* .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
* { I915_ENGINE_CLASS_COPY, 0 } }
* };
* struct drm_i915_gem_context_create_ext_setparam p_engines = {
* .base = {
* .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
* },
* .param = {
* .param = I915_CONTEXT_PARAM_ENGINES,
* .value = to_user_pointer(&engines),
* .size = sizeof(engines),
* },
* };
* struct drm_i915_gem_context_create_ext create = {
* .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
* .extensions = to_user_pointer(&p_engines);
* };
*
* ctx_id = gem_context_create_ext(drm_fd, &create);
*
* // We have now created a GEM context with two engines in the map:
* // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
* // will not be accessible from this context.
*
* ...
* execbuf.rsvd1 = ctx_id;
* execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
* gem_execbuf(drm_fd, &execbuf);
*
* ...
* execbuf.rsvd1 = ctx_id;
* execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
* gem_execbuf(drm_fd, &execbuf);
*/
struct i915_context_param_engines {
__u64 extensions; /* linked chain of extension blocks, 0 terminates */
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
@@ -2106,8 +2169,6 @@ struct drm_i915_gem_context_destroy {
* The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
* returned in the outparam @id.
*
* No flags are defined, with all bits reserved and must be zero.
*
* An extension chain maybe provided, starting with @extensions, and terminated
* by the @next_extension being 0. Currently, mem region extension is defined.
*
@@ -2407,6 +2468,7 @@ struct drm_i915_query_item {
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
#define DRM_I915_QUERY_ENGINE_INFO 2
#define DRM_I915_QUERY_PERF_CONFIG 3
#define DRM_I915_QUERY_MEMORY_REGIONS 4
/* Must be kept compact -- no holes and well documented */
/**
@@ -2554,8 +2616,6 @@ struct drm_i915_query_topology_info {
* struct drm_i915_engine_info
*
* Describes one engine and it's capabilities as known to the driver.
*
* FIXME: revert to upstream version after UMD switch to PRELIM version
*/
struct drm_i915_engine_info {
/** @engine: Engine class and instance. */
@@ -2649,6 +2709,138 @@ struct drm_i915_query_perf_config {
__u8 data[];
};
/**
* enum drm_i915_gem_memory_class - Supported memory classes
*/
enum drm_i915_gem_memory_class {
/** @I915_MEMORY_CLASS_SYSTEM: System memory */
I915_MEMORY_CLASS_SYSTEM = 0,
/** @I915_MEMORY_CLASS_DEVICE: Device local-memory */
I915_MEMORY_CLASS_DEVICE,
};
/**
* struct drm_i915_gem_memory_class_instance - Identify particular memory region
*/
struct drm_i915_gem_memory_class_instance {
/** @memory_class: See enum drm_i915_gem_memory_class */
__u16 memory_class;
/** @memory_instance: Which instance */
__u16 memory_instance;
};
/**
* struct drm_i915_memory_region_info - Describes one region as known to the
* driver.
*
* Note that we reserve some stuff here for potential future work. As an example
* we might want expose the capabilities for a given region, which could include
* things like if the region is CPU mappable/accessible, what are the supported
* mapping types etc.
*
* Note that to extend struct drm_i915_memory_region_info and struct
* drm_i915_query_memory_regions in the future the plan is to do the following:
*
* .. code-block:: C
*
* struct drm_i915_memory_region_info {
* struct drm_i915_gem_memory_class_instance region;
* union {
* __u32 rsvd0;
* __u32 new_thing1;
* };
* ...
* union {
* __u64 rsvd1[8];
* struct {
* __u64 new_thing2;
* __u64 new_thing3;
* ...
* };
* };
* };
*
* With this things should remain source compatible between versions for
* userspace, even as we add new fields.
*
* Note this is using both struct drm_i915_query_item and struct drm_i915_query.
* For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS
* at &drm_i915_query_item.query_id.
*/
struct drm_i915_memory_region_info {
/** @region: The class:instance pair encoding */
struct drm_i915_gem_memory_class_instance region;
/** @rsvd0: MBZ */
__u32 rsvd0;
/** @probed_size: Memory probed by the driver (-1 = unknown) */
__u64 probed_size;
/** @unallocated_size: Estimate of memory remaining (-1 = unknown) */
__u64 unallocated_size;
/** @rsvd1: MBZ */
__u64 rsvd1[8];
};
/**
* struct drm_i915_query_memory_regions
*
* The region info query enumerates all regions known to the driver by filling
* in an array of struct drm_i915_memory_region_info structures.
*
* Example for getting the list of supported regions:
*
* .. code-block:: C
*
* struct drm_i915_query_memory_regions *info;
* struct drm_i915_query_item item = {
* .query_id = DRM_I915_QUERY_MEMORY_REGIONS;
* };
* struct drm_i915_query query = {
* .num_items = 1,
* .items_ptr = (uintptr_t)&item,
* };
* int err, i;
*
* // First query the size of the blob we need, this needs to be large
* // enough to hold our array of regions. The kernel will fill out the
* // item.length for us, which is the number of bytes we need.
* err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
* if (err) ...
*
* info = calloc(1, item.length);
* // Now that we allocated the required number of bytes, we call the ioctl
* // again, this time with the data_ptr pointing to our newly allocated
* // blob, which the kernel can then populate with the all the region info.
* item.data_ptr = (uintptr_t)&info,
*
* err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
* if (err) ...
*
* // We can now access each region in the array
* for (i = 0; i < info->num_regions; i++) {
* struct drm_i915_memory_region_info mr = info->regions[i];
* u16 class = mr.region.class;
* u16 instance = mr.region.instance;
*
* ....
* }
*
* free(info);
*/
struct drm_i915_query_memory_regions {
/** @num_regions: Number of supported regions */
__u32 num_regions;
/** @rsvd: MBZ */
__u32 rsvd[3];
/** @regions: Info about each supported region */
struct drm_i915_memory_region_info regions[];
};
#include "i915_drm_prelim.h"
/* ID of the protected content session managed by i915 when PXP is active */

34
third_party/uapi/prelim/drm/i915_drm_prelim.h vendored
View File

@@ -6,7 +6,7 @@
#ifndef __I915_DRM_PRELIM_H__
#define __I915_DRM_PRELIM_H__
#include "drm.h"
#include "i915_drm.h"
/*
* Modifications to structs/values defined here are subject to
@@ -419,21 +419,6 @@ struct prelim_drm_i915_query_item {
#define PRELIM_DRM_I915_QUERY_L3_BANK_COUNT (PRELIM_DRM_I915_QUERY | 14)
};
/*
* Number of BB in execbuf2 IOCTL - 1, used to submit more than BB in a single
* execbuf2 IOCTL.
*
* Return -EINVAL if more than 1 BB (value 0) is specified if
* PRELIM_I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT hasn't been called on the gem
* context first. Also returns -EINVAL if gem context has been setup with
* I915_PARALLEL_BB_PREEMPT_BOUNDARY and the number BBs not equal to the total
* number hardware contexts in the gem context.
*/
#define PRELIM_I915_EXEC_NUMBER_BB_LSB (48)
#define PRELIM_I915_EXEC_NUMBER_BB_MASK (0x3full << PRELIM_I915_EXEC_NUMBER_BB_LSB)
#define PRELIM_I915_EXEC_NUMBER_BB_MSB (54)
#define PRELIM_I915_EXEC_NUMBER_BB_MASK_MSB (1ull << PRELIM_I915_EXEC_NUMBER_BB_MSB)
/*
* In XEHPSDV total number of engines can be more than the maximum supported
* engines by I915_EXEC_RING_MASK.
@@ -488,7 +473,7 @@ enum prelim_drm_i915_oa_format {
PRELIM_I915_OAC_FORMAT_A24u64_B8_C8,
PRELIM_I915_OA_FORMAT_A38u64_R2u64_B8_C8,
PRELIM_I915_OAM_FORMAT_A2u64_R2u64_B8_C8,
PRELIM_I915_OAC_FORMAT_A24u22_B8_C8,
PRELIM_I915_OAC_FORMAT_A22u32_R2u32_B8_C8,
PRELIM_I915_OA_FORMAT_MAX /* non-ABI */
};
@@ -1228,6 +1213,13 @@ struct prelim_drm_i915_vm_bind_ext_sync_fence {
__u64 val;
};
struct prelim_drm_i915_gem_vm_control {
#define PRELIM_I915_VM_CREATE_FLAGS_DISABLE_SCRATCH (1 << 16)
#define PRELIM_I915_VM_CREATE_FLAGS_ENABLE_PAGE_FAULT (1 << 17)
#define PRELIM_I915_VM_CREATE_FLAGS_USE_VM_BIND (1 << 18)
#define PRELIM_I915_VM_CREATE_FLAGS_UNKNOWN (~(GENMASK(18, 16)))
};
struct prelim_drm_i915_gem_vm_region_ext {
#define PRELIM_I915_GEM_VM_CONTROL_EXT_REGION (PRELIM_I915_USER_EXT | 0)
struct i915_user_extension base;
@@ -1236,12 +1228,6 @@ struct prelim_drm_i915_gem_vm_region_ext {
__u32 pad;
};
struct prelim_drm_i915_gem_vm_control {
#define PRELIM_I915_VM_CREATE_FLAGS_DISABLE_SCRATCH (1 << 16)
#define PRELIM_I915_VM_CREATE_FLAGS_ENABLE_PAGE_FAULT (1 << 17)
#define PRELIM_I915_VM_CREATE_FLAGS_UNKNOWN (~(GENMASK(17, 16)))
};
struct prelim_drm_i915_vm_bind_ext_set_pat {
#define PRELIM_I915_VM_BIND_EXT_SET_PAT (PRELIM_I915_USER_EXT | 2)
struct i915_user_extension base;
@@ -1293,7 +1279,7 @@ struct prelim_drm_i915_gem_clos_free {
*/
struct prelim_drm_i915_gem_cache_reserve {
__u16 clos_index;
__u16 cache_level; // e.g. 3 for L3
__u16 cache_level; /* e.g. 3 for L3 */
__u16 num_ways;
__u16 pad16;
};