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Enforce ALU register type for EncodeMath interface

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General purpose register cannot be used for MI_MATH
calculations. ALU registers must be used.

To prevent passing general purpose register into the
EncodeMath interface, enforce a ALU register type
at compile time.

Change-Id: I98aa8605cde27e7003029d33b3ef3bcfb2306878
Signed-off-by: Sebastian Sanchez <sebastian.sanchez@intel.com>
This commit is contained in:
Sebastian Sanchez
2020-02-25 10:23:04 -08:00
committed by sys_ocldev
parent 2def8cdeec
commit 54b2763466
9 changed files with 138 additions and 103 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
shared/source/command_container/command_encoder.h
View File

@@ -9,6 +9,7 @@
#include "shared/source/command_container/cmdcontainer.h"
#include "shared/source/command_stream/linear_stream.h"
#include "shared/source/execution_environment/execution_environment.h"
#include "shared/source/helpers/register_offsets.h"
#include "shared/source/helpers/simd_helper.h"
#include "shared/source/kernel/dispatch_kernel_encoder_interface.h"
@@ -55,7 +56,10 @@ struct EncodeMath {
using MI_MATH = typename GfxFamily::MI_MATH;
static uint32_t *commandReserve(CommandContainer &container);
static void addition(CommandContainer &container, uint32_t firstOperandRegister, uint32_t secondOperandRegister, uint32_t finalResultRegister);
static void addition(CommandContainer &container,
AluRegisters firstOperandRegister,
AluRegisters secondOperandRegister,
AluRegisters finalResultRegister);
};
template <typename GfxFamily>
@@ -70,14 +74,14 @@ struct EncodeMathMMIO {
static void encodeGreaterThanPredicate(CommandContainer &container, uint64_t lhsVal, uint32_t rhsVal);
static void encodeAlu(MI_MATH_ALU_INST_INLINE *pAluParam, uint32_t srcA, uint32_t srcB, uint32_t op, uint32_t dest, uint32_t result);
static void encodeAlu(MI_MATH_ALU_INST_INLINE *pAluParam, AluRegisters srcA, AluRegisters srcB, AluRegisters op, AluRegisters dest, AluRegisters result);
static void encodeAluSubStoreCarry(MI_MATH_ALU_INST_INLINE *pAluParam, uint32_t regA, uint32_t regB, uint32_t finalResultRegister);
static void encodeAluSubStoreCarry(MI_MATH_ALU_INST_INLINE *pAluParam, AluRegisters regA, AluRegisters regB, AluRegisters finalResultRegister);
static void encodeAluAdd(MI_MATH_ALU_INST_INLINE *pAluParam,
uint32_t firstOperandRegister,
uint32_t secondOperandRegister,
uint32_t finalResultRegister);
AluRegisters firstOperandRegister,
AluRegisters secondOperandRegister,
AluRegisters finalResultRegister);
};
template <typename GfxFamily>

52
shared/source/command_container/command_encoder.inl
View File

@@ -69,12 +69,12 @@ void EncodeMathMMIO<Family>::encodeMulRegVal(CommandContainer &container, uint32
i = 0;
while (i < logLws) {
if (val & (1 << i)) {
EncodeMath<Family>::addition(container, ALU_REGISTER_R_1,
ALU_REGISTER_R_0, ALU_REGISTER_R_2);
EncodeMath<Family>::addition(container, AluRegisters::R_1,
AluRegisters::R_0, AluRegisters::R_2);
EncodeSetMMIO<Family>::encodeREG(container, CS_GPR_R1, CS_GPR_R2);
}
EncodeMath<Family>::addition(container, ALU_REGISTER_R_0,
ALU_REGISTER_R_0, ALU_REGISTER_R_2);
EncodeMath<Family>::addition(container, AluRegisters::R_0,
AluRegisters::R_0, AluRegisters::R_2);
EncodeSetMMIO<Family>::encodeREG(container, CS_GPR_R0, CS_GPR_R2);
i++;
}
@@ -104,8 +104,8 @@ void EncodeMathMMIO<Family>::encodeGreaterThanPredicate(CommandContainer &contai
reinterpret_cast<MI_MATH *>(cmd)->DW0.BitField.DwordLength = NUM_ALU_INST_FOR_READ_MODIFY_WRITE - 1;
cmd++;
/* CS_GPR_R* registers map to ALU_REGISTER_R_* registers */
encodeAluSubStoreCarry(reinterpret_cast<MI_MATH_ALU_INST_INLINE *>(cmd), ALU_REGISTER_R_0, ALU_REGISTER_R_1, ALU_REGISTER_R_2);
/* CS_GPR_R* registers map to AluRegisters::R_* registers */
encodeAluSubStoreCarry(reinterpret_cast<MI_MATH_ALU_INST_INLINE *>(cmd), AluRegisters::R_0, AluRegisters::R_1, AluRegisters::R_2);
EncodeSetMMIO<Family>::encodeREG(container, CS_PREDICATE_RESULT, CS_GPR_R2);
}
@@ -122,33 +122,33 @@ void EncodeMathMMIO<Family>::encodeGreaterThanPredicate(CommandContainer &contai
* data from "postOperationStateRegister" will be copied.
*/
template <typename Family>
void EncodeMathMMIO<Family>::encodeAlu(MI_MATH_ALU_INST_INLINE *pAluParam, uint32_t srcA, uint32_t srcB, uint32_t op, uint32_t finalResultRegister, uint32_t postOperationStateRegister) {
pAluParam->DW0.BitField.ALUOpcode = ALU_OPCODE_LOAD;
pAluParam->DW0.BitField.Operand1 = ALU_REGISTER_R_SRCA;
pAluParam->DW0.BitField.Operand2 = srcA;
void EncodeMathMMIO<Family>::encodeAlu(MI_MATH_ALU_INST_INLINE *pAluParam, AluRegisters srcA, AluRegisters srcB, AluRegisters op, AluRegisters finalResultRegister, AluRegisters postOperationStateRegister) {
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(AluRegisters::OPCODE_LOAD);
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_SRCA);
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(srcA);
pAluParam++;
pAluParam->DW0.BitField.ALUOpcode = ALU_OPCODE_LOAD;
pAluParam->DW0.BitField.Operand1 = ALU_REGISTER_R_SRCB;
pAluParam->DW0.BitField.Operand2 = srcB;
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(AluRegisters::OPCODE_LOAD);
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(AluRegisters::R_SRCB);
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(srcB);
pAluParam++;
/* Order of operation: Operand1 <ALUOpcode> Operand2 */
pAluParam->DW0.BitField.ALUOpcode = op;
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(op);
pAluParam->DW0.BitField.Operand1 = 0;
pAluParam->DW0.BitField.Operand2 = 0;
pAluParam++;
pAluParam->DW0.BitField.ALUOpcode = ALU_OPCODE_STORE;
pAluParam->DW0.BitField.Operand1 = finalResultRegister;
pAluParam->DW0.BitField.Operand2 = postOperationStateRegister;
pAluParam->DW0.BitField.ALUOpcode = static_cast<uint32_t>(AluRegisters::OPCODE_STORE);
pAluParam->DW0.BitField.Operand1 = static_cast<uint32_t>(finalResultRegister);
pAluParam->DW0.BitField.Operand2 = static_cast<uint32_t>(postOperationStateRegister);
pAluParam++;
}
template <typename Family>
void EncodeMathMMIO<Family>::encodeAluSubStoreCarry(MI_MATH_ALU_INST_INLINE *pAluParam, uint32_t regA, uint32_t regB, uint32_t finalResultRegister) {
void EncodeMathMMIO<Family>::encodeAluSubStoreCarry(MI_MATH_ALU_INST_INLINE *pAluParam, AluRegisters regA, AluRegisters regB, AluRegisters finalResultRegister) {
/* regB is subtracted from regA */
encodeAlu(pAluParam, regA, regB, ALU_OPCODE_SUB, finalResultRegister, ALU_REGISTER_R_CF);
encodeAlu(pAluParam, regA, regB, AluRegisters::OPCODE_SUB, finalResultRegister, AluRegisters::R_CF);
}
template <typename Family>
@@ -167,9 +167,9 @@ uint32_t *EncodeMath<Family>::commandReserve(CommandContainer &container) {
template <typename Family>
void EncodeMath<Family>::addition(CommandContainer &container,
uint32_t firstOperandRegister,
uint32_t secondOperandRegister,
uint32_t finalResultRegister) {
AluRegisters firstOperandRegister,
AluRegisters secondOperandRegister,
AluRegisters finalResultRegister) {
uint32_t *cmd = EncodeMath<Family>::commandReserve(container);
EncodeMath<Family>::MI_MATH_ALU_INST_INLINE *pAluParam =
reinterpret_cast<MI_MATH_ALU_INST_INLINE *>(cmd);
@@ -181,10 +181,10 @@ void EncodeMath<Family>::addition(CommandContainer &container,
template <typename Family>
void EncodeMathMMIO<Family>::encodeAluAdd(MI_MATH_ALU_INST_INLINE *pAluParam,
uint32_t firstOperandRegister,
uint32_t secondOperandRegister,
uint32_t finalResultRegister) {
encodeAlu(pAluParam, firstOperandRegister, secondOperandRegister, ALU_OPCODE_ADD, finalResultRegister, ALU_REGISTER_R_ACCU);
AluRegisters firstOperandRegister,
AluRegisters secondOperandRegister,
AluRegisters finalResultRegister) {
encodeAlu(pAluParam, firstOperandRegister, secondOperandRegister, AluRegisters::OPCODE_ADD, finalResultRegister, AluRegisters::R_ACCU);
}
template <typename Family>

56
shared/source/helpers/register_offsets.h
View File

@@ -41,34 +41,36 @@ constexpr uint32_t CS_PREDICATE_RESULT = 0x2418;
//Alu opcodes
constexpr uint32_t NUM_ALU_INST_FOR_READ_MODIFY_WRITE = 4;
constexpr uint32_t ALU_OPCODE_LOAD = 0x080;
constexpr uint32_t ALU_OPCODE_STORE = 0x180;
constexpr uint32_t ALU_OPCODE_ADD = 0x100;
constexpr uint32_t ALU_OPCODE_SUB = 0x101;
constexpr uint32_t ALU_OPCODE_AND = 0x102;
constexpr uint32_t ALU_OPCODE_OR = 0x103;
enum class AluRegisters : uint32_t {
OPCODE_LOAD = 0x080,
OPCODE_STORE = 0x180,
OPCODE_ADD = 0x100,
OPCODE_SUB = 0x101,
OPCODE_AND = 0x102,
OPCODE_OR = 0x103,
constexpr uint32_t ALU_REGISTER_R_0 = 0x0;
constexpr uint32_t ALU_REGISTER_R_1 = 0x1;
constexpr uint32_t ALU_REGISTER_R_2 = 0x2;
constexpr uint32_t ALU_REGISTER_R_3 = 0x3;
constexpr uint32_t ALU_REGISTER_R_4 = 0x4;
constexpr uint32_t ALU_REGISTER_R_5 = 0x5;
constexpr uint32_t ALU_REGISTER_R_6 = 0x6;
constexpr uint32_t ALU_REGISTER_R_7 = 0x7;
constexpr uint32_t ALU_REGISTER_R_8 = 0x8;
constexpr uint32_t ALU_REGISTER_R_9 = 0x9;
constexpr uint32_t ALU_REGISTER_R_10 = 0xA;
constexpr uint32_t ALU_REGISTER_R_11 = 0xB;
constexpr uint32_t ALU_REGISTER_R_12 = 0xC;
constexpr uint32_t ALU_REGISTER_R_13 = 0xD;
constexpr uint32_t ALU_REGISTER_R_14 = 0xE;
constexpr uint32_t ALU_REGISTER_R_15 = 0xF;
R_0 = 0x0,
R_1 = 0x1,
R_2 = 0x2,
R_3 = 0x3,
R_4 = 0x4,
R_5 = 0x5,
R_6 = 0x6,
R_7 = 0x7,
R_8 = 0x8,
R_9 = 0x9,
R_10 = 0xA,
R_11 = 0xB,
R_12 = 0xC,
R_13 = 0xD,
R_14 = 0xE,
R_15 = 0xF,
constexpr uint32_t ALU_REGISTER_R_SRCA = 0x20;
constexpr uint32_t ALU_REGISTER_R_SRCB = 0x21;
constexpr uint32_t ALU_REGISTER_R_ACCU = 0x31;
constexpr uint32_t ALU_REGISTER_R_ZF = 0x32;
constexpr uint32_t ALU_REGISTER_R_CF = 0x33;
R_SRCA = 0x20,
R_SRCB = 0x21,
R_ACCU = 0x31,
R_ZF = 0x32,
R_CF = 0x33
};
constexpr uint32_t GP_THREAD_TIME_REG_ADDRESS_OFFSET_LOW = 0x23A8;