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Refactor PIPE_CONTROL programming

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Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
This commit is contained in:
Dunajski, Bartosz
2022-08-19 15:56:22 +00:00
committed by Compute-Runtime-Automation
parent 40bc79fd6a
commit 595cfebaef
37 changed files with 80 additions and 90 deletions
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4
level_zero/core/source/cmdqueue/cmdqueue_hw.inl
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@@ -121,7 +121,7 @@ ze_result_t CommandQueueHw<gfxCoreFamily>::executeCommandListsRegular(
linearStreamSizeEstimate += this->estimateLinearStreamSizeComplementary(ctx, phCommandLists, numCommandLists);
linearStreamSizeEstimate += this->computePreemptionSize(ctx, phCommandLists, numCommandLists);
linearStreamSizeEstimate += this->computeDebuggerCmdsSize(ctx);
linearStreamSizeEstimate += NEO::MemorySynchronizationCommands<GfxFamily>::getSizeForBarrierWithPostSyncOperation(this->device->getHwInfo());
linearStreamSizeEstimate += NEO::MemorySynchronizationCommands<GfxFamily>::getSizeForBarrierWithPostSyncOperation(this->device->getHwInfo(), false);
NEO::LinearStream child(nullptr);
if (const auto ret = this->makeAlignedChildStreamAndSetGpuBase(child, linearStreamSizeEstimate); ret != ZE_RESULT_SUCCESS) {
@@ -491,7 +491,7 @@ size_t CommandQueueHw<gfxCoreFamily>::computePreemptionSize(
if (ctx.statePreemption != commandListPreemption) {
if (this->preemptionCmdSyncProgramming) {
preemptionSize += NEO::MemorySynchronizationCommands<GfxFamily>::getSizeForSingleBarrier();
preemptionSize += NEO::MemorySynchronizationCommands<GfxFamily>::getSizeForSingleBarrier(false);
}
preemptionSize += NEO::PreemptionHelper::getRequiredCmdStreamSize<GfxFamily>(commandListPreemption, ctx.statePreemption);
ctx.statePreemption = commandListPreemption;

4
level_zero/core/source/cmdqueue/cmdqueue_hw_base.inl
View File

@@ -92,9 +92,9 @@ void CommandQueueHw<gfxCoreFamily>::programStateBaseAddress(uint64_t gsba, bool
template <GFXCORE_FAMILY gfxCoreFamily>
size_t CommandQueueHw<gfxCoreFamily>::estimateStateBaseAddressCmdSize() {
using STATE_BASE_ADDRESS = typename GfxFamily::STATE_BASE_ADDRESS;
using PIPE_CONTROL = typename GfxFamily::PIPE_CONTROL;
size_t size = sizeof(STATE_BASE_ADDRESS) + sizeof(PIPE_CONTROL) + NEO::EncodeWA<GfxFamily>::getAdditionalPipelineSelectSize(*device->getNEODevice(), this->csr->isRcs());
size_t size = sizeof(STATE_BASE_ADDRESS) + NEO::MemorySynchronizationCommands<GfxFamily>::getSizeForSingleBarrier(false) +
NEO::EncodeWA<GfxFamily>::getAdditionalPipelineSelectSize(*device->getNEODevice(), this->csr->isRcs());
if (NEO::Debugger::isDebugEnabled(internalUsage) && device->getL0Debugger() != nullptr) {
const size_t trackedAddressesCount = 6;

3
level_zero/core/source/cmdqueue/cmdqueue_xe_hp_core_and_later.inl
View File

@@ -94,7 +94,6 @@ void CommandQueueHw<gfxCoreFamily>::programStateBaseAddress(uint64_t gsba, bool
template <GFXCORE_FAMILY gfxCoreFamily>
size_t CommandQueueHw<gfxCoreFamily>::estimateStateBaseAddressCmdSize() {
using STATE_BASE_ADDRESS = typename GfxFamily::STATE_BASE_ADDRESS;
using PIPE_CONTROL = typename GfxFamily::PIPE_CONTROL;
using _3DSTATE_BINDING_TABLE_POOL_ALLOC = typename GfxFamily::_3DSTATE_BINDING_TABLE_POOL_ALLOC;
NEO::Device *neoDevice = device->getNEODevice();
@@ -103,7 +102,7 @@ size_t CommandQueueHw<gfxCoreFamily>::estimateStateBaseAddressCmdSize() {
size_t size = 0;
if (NEO::ApiSpecificConfig::getBindlessConfiguration()) {
size += sizeof(STATE_BASE_ADDRESS) + sizeof(PIPE_CONTROL) + sizeof(_3DSTATE_BINDING_TABLE_POOL_ALLOC);
size += sizeof(STATE_BASE_ADDRESS) + NEO::MemorySynchronizationCommands<GfxFamily>::getSizeForSingleBarrier(false) + sizeof(_3DSTATE_BINDING_TABLE_POOL_ALLOC);
if (hwInfoConfig.isAdditionalStateBaseAddressWARequired(hwInfo)) {
size += sizeof(STATE_BASE_ADDRESS);