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feature: Add support for pcie downgrade in BMG

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Related-To: NEO-15270

Signed-off-by: shubham kumar <shubham.kumar@intel.com>
This commit is contained in:
shubham kumar
2025-07-14 17:16:22 +00:00
committed by Compute-Runtime-Automation
parent 6033a10513
commit 5a1d6ac552
53 changed files with 901 additions and 66 deletions
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3
level_zero/include/level_zero/CMakeLists.txt
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@@ -1,5 +1,5 @@
#
# Copyright (C) 2024 Intel Corporation
# Copyright (C) 2024-2025 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
@@ -8,6 +8,7 @@ set(L0_API_INCLUDE_FILES
${CMAKE_CURRENT_SOURCE_DIR}/ze_intel_gpu.h
${CMAKE_CURRENT_SOURCE_DIR}/ze_stypes.h
${CMAKE_CURRENT_SOURCE_DIR}/zet_intel_gpu_debug.h
${CMAKE_CURRENT_SOURCE_DIR}/zes_intel_gpu_sysman.h
)
target_sources(${L0_STATIC_LIB_NAME}

4
level_zero/include/level_zero/ze_stypes.h
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@@ -44,4 +44,8 @@ using zet_structure_type_ext_t = uint32_t;
#define ZET_INTEL_STRUCTURE_TYPE_METRIC_SOURCE_ID_EXP static_cast<zet_structure_type_ext_t>(0x0001000a)
#define ZET_INTEL_STRUCTURE_TYPE_METRIC_DECODED_BUFFER_PROPERTIES_EXP static_cast<zet_structure_type_ext_t>(0x0001000b)
// Sysman structure types
#define ZES_INTEL_PCI_LINK_SPEED_DOWNGRADE_EXP_STATE static_cast<zet_structure_type_ext_t>(0x00040001)
#define ZES_INTEL_PCI_LINK_SPEED_DOWNGRADE_EXP_PROPERTIES static_cast<zet_structure_type_ext_t>(0x00040002)
#endif

71
level_zero/include/level_zero/zes_intel_gpu_sysman.h Normal file
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@@ -0,0 +1,71 @@
/*
* Copyright (C) 2025 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#ifndef _ZES_INTEL_GPU_SYSMAN_H
#define _ZES_INTEL_GPU_SYSMAN_H
#include "level_zero/include/level_zero/ze_stypes.h"
#include <level_zero/zes_api.h>
#if defined(__cplusplus)
#pragma once
extern "C" {
#endif
#include <stdint.h>
#define ZES_INTEL_GPU_SYSMAN_VERSION_MAJOR 0
#define ZES_INTEL_GPU_SYSMAN_VERSION_MINOR 1
///////////////////////////////////////////////////////////////////////////////
/// @brief Query pcie downgrade status extension Version(s)
typedef enum _zes_intel_pci_link_speed_downgrade_exp_state_version_t {
ZES_INTEL_PCI_LINK_SPEED_DOWNGRADE_EXP_STATE_VERSION_1_0 = ZE_MAKE_VERSION(1, 0), ///< version 1.0
ZES_INTEL_PCI_LINK_SPEED_DOWNGRADE_EXP_STATE_VERSION_CURRENT = ZE_MAKE_VERSION(1, 0), ///< latest known version
ZES_INTEL_PCI_LINK_SPEED_DOWNGRADE_EXP_STATE_VERSION_FORCE_UINT32 = 0x7fffffff
} zes_intel_pci_link_speed_downgrade_exp_state_version_t;
///////////////////////////////////////////////////////////////////////////////
/// @brief Query pcie downgrade status.
/// This structure can be passed in the 'pNext' of zes_pci_state_t
typedef struct _zes_intel_pci_link_speed_downgrade_exp_state_t {
zet_structure_type_ext_t stype; ///< [in] type of this structure
void *pNext; ///< [in][optional] must be null or a pointer to an extension-specific
///< structure (i.e. contains stype and pNext).
ze_bool_t pciLinkSpeedDowngradeStatus; ///< [out] Returns the current PCIe downgrade status .
} zes_intel_pci_link_speed_downgrade_exp_state_t;
///////////////////////////////////////////////////////////////////////////////
/// @brief Query pcie downgrade capability extension Version(s)
typedef enum _zes_intel_pci_link_speed_downgrade_exp_properties_version_t {
ZES_INTEL_PCI_LINK_SPEED_DOWNGRADE_EXP_PROPERTIES_VERSION_1_0 = ZE_MAKE_VERSION(1, 0), ///< version 1.0
ZES_INTEL_PCI_LINK_SPEED_DOWNGRADE_EXP_PROPERTIES_VERSION_CURRENT = ZE_MAKE_VERSION(1, 0), ///< latest known version
ZES_INTEL_PCI_LINK_SPEED_DOWNGRADE_EXP_PROPERTIES_VERSION_FORCE_UINT32 = 0x7fffffff
} zes_intel_pci_link_speed_downgrade_exp_properties_version_t;
///////////////////////////////////////////////////////////////////////////////
/// @brief Query pcie downgrade capability.
/// This structure can be passed in the 'pNext' of zes_pci_properties_t
typedef struct _zes_intel_pci_link_speed_downgrade_exp_properties_t {
zet_structure_type_ext_t stype; ///< [in] type of this structure
void *pNext; ///< [in][optional] must be null or a pointer to an extension-specific
///< structure (i.e. contains stype and pNext).
ze_bool_t pciLinkSpeedUpdateCapable; ///< [out] Returns if PCIe downgrade capability is available.
int32_t maxPciGenSupported; ///< [out] Returns the max supported PCIe generation of the device. -1 indicated the infomation is not available
} zes_intel_pci_link_speed_downgrade_exp_properties_t;
ze_result_t ZE_APICALL zesIntelDevicePciLinkSpeedUpdateExp(
zes_device_handle_t hDevice, ///< [in] handle of the device
ze_bool_t downgradeUpgrade, ///< [in] boolean value to decide wheather to perform PCIe downgrade(true) or upgrade(false)
zes_device_action_t *pendingAction ///< [out] Pending action
);
#if defined(__cplusplus)
} // extern "C"
#endif
#endif