From 5a3fd1dc9475dbe2535a147c6bbb4e9421398696 Mon Sep 17 00:00:00 2001 From: Szymon Morek Date: Wed, 8 Dec 2021 10:10:27 +0000 Subject: [PATCH] Check i915 version at runtime Related-To: NEO-6510 Check which prelim version is being used. Select proper IoctlHelper based on that version. If no version found, switch to upstream instead. Source of prelim headers: https://github.com/intel-gpu/drm-uapi-helper Signed-off-by: Szymon Morek --- .../os_interface/linux/CMakeLists.txt | 7 +- .../os_interface/linux/drm_mock_impl.h | 6 +- .../os_interface/linux/drm_tests.cpp | 29 + .../linux/ioctl_helper_default_tests.cpp | 40 - .../linux/ioctl_helper_tests_dg1.cpp | 7 +- .../linux/ioctl_helper_tests_prelim.cpp | 97 + ...dv.cpp => ioctl_helper_tests_upstream.cpp} | 10 +- .../os_interface/linux/prelim_helper_func.cpp | 41 + .../device/drm/card1/prelim_uapi_version | 1 + .../source/os_interface/linux/CMakeLists.txt | 9 +- shared/source/os_interface/linux/drm_neo.cpp | 14 + shared/source/os_interface/linux/drm_neo.h | 1 + .../source/os_interface/linux/drm_query.cpp | 2 +- .../os_interface/linux/ioctl_helper.cpp | 10 - .../source/os_interface/linux/ioctl_helper.h | 15 +- .../linux/ioctl_helper_default.cpp | 24 - .../linux/ioctl_helper_getter.cpp | 38 + .../linux/ioctl_helper_prelim.cpp | 52 + ...e_hp_sdv.cpp => ioctl_helper_upstream.cpp} | 11 +- .../linux/local/xe_hp_sdv/CMakeLists.txt | 13 - .../enable_ioctl_helper_xe_hp_sdv.cpp | 21 - .../source/os_interface/linux/memory_info.cpp | 3 +- .../uapi/{xe_hp_sdv => prelim}/drm/drm.h | 306 +-- .../{xe_hp_sdv => prelim}/drm/drm_fourcc.h | 538 ++++- .../uapi/{xe_hp_sdv => prelim}/drm/drm_mode.h | 253 ++- .../uapi/{xe_hp_sdv => prelim}/drm/i915_drm.h | 857 ++------ third_party/uapi/prelim/drm/i915_drm_prelim.h | 1742 +++++++++++++++++ .../uapi/prelim/drm/intel_hwconfig_types.h | 102 + 28 files changed, 3116 insertions(+), 1133 deletions(-) delete mode 100644 opencl/test/unit_test/os_interface/linux/ioctl_helper_default_tests.cpp create mode 100644 opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_prelim.cpp rename opencl/test/unit_test/os_interface/linux/{ioctl_helper_tests_xe_hp_sdv.cpp => ioctl_helper_tests_upstream.cpp} (84%) create mode 100644 opencl/test/unit_test/os_interface/linux/prelim_helper_func.cpp create mode 100644 opencl/test/unit_test/test_files/linux/devices/device/drm/card1/prelim_uapi_version delete mode 100644 shared/source/os_interface/linux/ioctl_helper_default.cpp create mode 100644 shared/source/os_interface/linux/ioctl_helper_getter.cpp create mode 100644 shared/source/os_interface/linux/ioctl_helper_prelim.cpp rename shared/source/os_interface/linux/{local/xe_hp_sdv/ioctl_helper_xe_hp_sdv.cpp => ioctl_helper_upstream.cpp} (80%) delete mode 100644 shared/source/os_interface/linux/local/xe_hp_sdv/CMakeLists.txt delete mode 100644 shared/source/os_interface/linux/local/xe_hp_sdv/enable_ioctl_helper_xe_hp_sdv.cpp rename third_party/uapi/{xe_hp_sdv => prelim}/drm/drm.h (83%) rename third_party/uapi/{xe_hp_sdv => prelim}/drm/drm_fourcc.h (61%) rename third_party/uapi/{xe_hp_sdv => prelim}/drm/drm_mode.h (78%) rename third_party/uapi/{xe_hp_sdv => prelim}/drm/i915_drm.h (75%) create mode 100644 third_party/uapi/prelim/drm/i915_drm_prelim.h create mode 100644 third_party/uapi/prelim/drm/intel_hwconfig_types.h diff --git a/opencl/test/unit_test/os_interface/linux/CMakeLists.txt b/opencl/test/unit_test/os_interface/linux/CMakeLists.txt index a6083e1d02..b595495b98 100644 --- a/opencl/test/unit_test/os_interface/linux/CMakeLists.txt +++ b/opencl/test/unit_test/os_interface/linux/CMakeLists.txt @@ -34,7 +34,8 @@ set(IGDRCL_SRCS_tests_os_interface_linux ${CMAKE_CURRENT_SOURCE_DIR}/hw_info_config_linux_tests.cpp ${CMAKE_CURRENT_SOURCE_DIR}/hw_info_config_linux_tests.h ${CMAKE_CURRENT_SOURCE_DIR}/linux_create_command_queue_with_properties_tests.cpp - ${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}ioctl_helper_default_tests.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/ioctl_helper_tests_prelim.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/prelim_helper_func.cpp ${CMAKE_CURRENT_SOURCE_DIR}/mock_os_time_linux.h ${CMAKE_CURRENT_SOURCE_DIR}/mock_performance_counters_linux.cpp ${CMAKE_CURRENT_SOURCE_DIR}/mock_performance_counters_linux.h @@ -58,9 +59,9 @@ if(TESTS_DG1 AND "${BRANCH_TYPE}" STREQUAL "") ) endif() -if(TESTS_XE_HP_SDV AND "${BRANCH_TYPE}" STREQUAL "") +if("${BRANCH_TYPE}" STREQUAL "") list(APPEND IGDRCL_SRCS_tests_os_interface_linux - ${CMAKE_CURRENT_SOURCE_DIR}/ioctl_helper_tests_xe_hp_sdv.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/ioctl_helper_tests_upstream.cpp ) endif() diff --git a/opencl/test/unit_test/os_interface/linux/drm_mock_impl.h b/opencl/test/unit_test/os_interface/linux/drm_mock_impl.h index 906c95abf5..6915a09fec 100644 --- a/opencl/test/unit_test/os_interface/linux/drm_mock_impl.h +++ b/opencl/test/unit_test/os_interface/linux/drm_mock_impl.h @@ -36,7 +36,11 @@ class DrmTipMock : public DrmMock { __u64 offset = 0; int mmapOffsetRetVal = 0; - virtual int handleRemainingRequests(unsigned long request, void *arg) { + void getPrelimVersion(std::string &prelimVersion) override { + prelimVersion = ""; + } + + virtual int handleRemainingRequests(unsigned long request, void *arg) override { if ((request == DRM_IOCTL_I915_QUERY) && (arg != nullptr)) { if (i915QuerySuccessCount == 0) { return EINVAL; diff --git a/opencl/test/unit_test/os_interface/linux/drm_tests.cpp b/opencl/test/unit_test/os_interface/linux/drm_tests.cpp index 4231b9c284..550113ba60 100644 --- a/opencl/test/unit_test/os_interface/linux/drm_tests.cpp +++ b/opencl/test/unit_test/os_interface/linux/drm_tests.cpp @@ -909,3 +909,32 @@ TEST(DrmTest, whenCheckedIfResourcesCleanupCanBeSkippedThenReturnsFalse) { EXPECT_FALSE(pDrm->skipResourceCleanup()); delete pDrm; } + +TEST(DrmQueryTest, givenUapiPrelimVersionThenReturnCorrectString) { + auto executionEnvironment = std::make_unique(); + executionEnvironment->prepareRootDeviceEnvironments(1); + DrmMock drm{*executionEnvironment->rootDeviceEnvironments[0]}; + + std::string prelimVersionFile = "test_files/linux/devices/device/drm/card1/prelim_uapi_version"; + EXPECT_TRUE(fileExists(prelimVersionFile)); + + drm.setPciPath("device"); + + std::string prelimVersion = ""; + drm.getPrelimVersion(prelimVersion); + + EXPECT_EQ("2.0", prelimVersion); +} + +TEST(DrmQueryTest, givenUapiPrelimVersionWithInvalidPathThenReturnEmptyString) { + auto executionEnvironment = std::make_unique(); + executionEnvironment->prepareRootDeviceEnvironments(1); + DrmMock drm{*executionEnvironment->rootDeviceEnvironments[0]}; + + drm.setPciPath("invalidPath"); + + std::string prelimVersion = "2.0"; + drm.getPrelimVersion(prelimVersion); + + EXPECT_TRUE(prelimVersion.empty()); +} diff --git a/opencl/test/unit_test/os_interface/linux/ioctl_helper_default_tests.cpp b/opencl/test/unit_test/os_interface/linux/ioctl_helper_default_tests.cpp deleted file mode 100644 index 14a887ba0f..0000000000 --- a/opencl/test/unit_test/os_interface/linux/ioctl_helper_default_tests.cpp +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#include "shared/source/execution_environment/execution_environment.h" -#include "shared/source/os_interface/linux/ioctl_helper.h" -#include "shared/source/os_interface/linux/memory_info.h" -#include "shared/test/common/libult/linux/drm_mock.h" - -#include "test.h" - -using namespace NEO; - -TEST(IoctlHelperTestsDefault, givenUnsupportedPlatformWhenCreateGemExtThenReturnErrorNumber) { - auto executionEnvironment = std::make_unique(); - executionEnvironment->prepareRootDeviceEnvironments(1); - auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); - - drm_i915_memory_region_info regionInfo[2] = {}; - regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0}; - regionInfo[0].probed_size = 8 * GB; - regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; - regionInfo[1].probed_size = 16 * GB; - - auto ioctlHelper = IoctlHelper::get(IGFX_UNKNOWN); - uint32_t handle = 0; - auto ret = ioctlHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); - - EXPECT_EQ(-1u, ret); -} - -TEST(IoctlHelperTestsDefault, givenUnsupportedPlatformWhenTranslateIfRequiredReturnSameData) { - auto *data = new uint8_t{}; - auto ioctlHelper = IoctlHelper::get(IGFX_UNKNOWN); - auto ret = ioctlHelper->translateIfRequired(data, 1); - EXPECT_EQ(ret.get(), data); -} diff --git a/opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_dg1.cpp b/opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_dg1.cpp index b70e0cad70..2391a15dc2 100644 --- a/opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_dg1.cpp +++ b/opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_dg1.cpp @@ -9,7 +9,6 @@ #include "shared/source/os_interface/linux/ioctl_helper.h" #include "shared/source/os_interface/linux/memory_info.h" #include "shared/test/common/helpers/debug_manager_state_restore.h" -#include "shared/test/common/helpers/default_hw_info.h" #include "opencl/test/unit_test/os_interface/linux/drm_mock_impl.h" #include "opencl/test/unit_test/os_interface/linux/drm_mock_prod_dg1.h" @@ -30,7 +29,7 @@ DG1TEST_F(IoctlHelperTestsDg1, givenDg1WhenCreateGemExtThenReturnCorrectValue) { regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; regionInfo[1].probed_size = 16 * GB; - auto ioctlHelper = IoctlHelper::get(defaultHwInfo->platform.eProductFamily); + auto ioctlHelper = IoctlHelper::get(drm.get()); uint32_t handle = 0; auto ret = ioctlHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); @@ -53,7 +52,7 @@ DG1TEST_F(IoctlHelperTestsDg1, givenDg1WithDrmTipWhenCreateGemExtWithDebugFlagTh regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; testing::internal::CaptureStdout(); - auto ioctlHelper = IoctlHelper::get(defaultHwInfo->platform.eProductFamily); + auto ioctlHelper = IoctlHelper::get(drm.get()); uint32_t handle = 0; auto ret = ioctlHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); @@ -77,7 +76,7 @@ DG1TEST_F(IoctlHelperTestsDg1, givenDg1WhenCreateGemExtWithDebugFlagThenPrintDeb regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; testing::internal::CaptureStdout(); - auto ioctlHelper = IoctlHelper::get(defaultHwInfo->platform.eProductFamily); + auto ioctlHelper = IoctlHelper::get(drm.get()); uint32_t handle = 0; auto ret = ioctlHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); diff --git a/opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_prelim.cpp b/opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_prelim.cpp new file mode 100644 index 0000000000..18130b124d --- /dev/null +++ b/opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_prelim.cpp @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/execution_environment/execution_environment.h" +#include "shared/source/os_interface/linux/ioctl_helper.h" +#include "shared/test/common/helpers/debug_manager_state_restore.h" +#include "shared/test/common/helpers/default_hw_info.h" +#include "shared/test/common/libult/linux/drm_mock.h" + +#include "test.h" + +using namespace NEO; + +extern int handlePrelimRequests(unsigned long request, void *arg); + +class DrmPrelimMock : public DrmMock { + public: + DrmPrelimMock(RootDeviceEnvironment &rootDeviceEnvironment) : DrmPrelimMock(rootDeviceEnvironment, defaultHwInfo.get()) {} + DrmPrelimMock(RootDeviceEnvironment &rootDeviceEnvironment, HardwareInfo *inputHwInfo) : DrmMock(rootDeviceEnvironment) { + rootDeviceEnvironment.setHwInfo(inputHwInfo); + rootDeviceEnvironment.getMutableHardwareInfo()->platform.eProductFamily = IGFX_UNKNOWN; + } + + void getPrelimVersion(std::string &prelimVersion) override { + prelimVersion = "2.0"; + } + + int handleRemainingRequests(unsigned long request, void *arg) override { + return handlePrelimRequests(request, arg); + } +}; + +TEST(IoctlHelperTestsPrelim, givenPrelimsWhenCreateGemExtThenReturnSuccess) { + auto executionEnvironment = std::make_unique(); + executionEnvironment->prepareRootDeviceEnvironments(1); + auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); + + drm_i915_memory_region_info regionInfo[2] = {}; + regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0}; + regionInfo[0].probed_size = 8 * GB; + regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; + regionInfo[1].probed_size = 16 * GB; + + auto ioctlHelper = IoctlHelper::get(drm.get()); + uint32_t handle = 0; + auto ret = ioctlHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); + + EXPECT_EQ(1u, handle); + EXPECT_EQ(0u, ret); + EXPECT_EQ(1u, drm->ioctlCallsCount); +} + +TEST(IoctlHelperTestsPrelim, givenPrelimsWhenCreateGemExtWithDebugFlagThenPrintDebugInfo) { + DebugManagerStateRestore stateRestore; + DebugManager.flags.PrintBOCreateDestroyResult.set(true); + + auto executionEnvironment = std::make_unique(); + executionEnvironment->prepareRootDeviceEnvironments(1); + auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); + + drm_i915_memory_region_info regionInfo[2] = {}; + regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0}; + regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; + + testing::internal::CaptureStdout(); + auto ioctlHelper = IoctlHelper::get(drm.get()); + uint32_t handle = 0; + ioctlHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); + + std::string output = testing::internal::GetCapturedStdout(); + std::string expectedOutput("Performing GEM_CREATE_EXT with { size: 1024, param: 0x1000000010001, memory class: 1, memory instance: 0 }\nGEM_CREATE_EXT has returned: 0 BO-1 with size: 1024\n"); + EXPECT_EQ(expectedOutput, output); +} + +TEST(IoctlHelperTestsPrelim, givenPrelimsWhenTranslateIfRequiredThenReturnSameData) { + auto executionEnvironment = std::make_unique(); + executionEnvironment->prepareRootDeviceEnvironments(1); + auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); + auto *data = new uint8_t{}; + auto ioctlHelper = IoctlHelper::get(drm.get()); + auto ret = ioctlHelper->translateIfRequired(data, 1); + EXPECT_EQ(ret.get(), data); +} + +TEST(IoctlHelperTestsDefault, givenPrelimsWhenCallIoctlThenProperIoctlRegistered) { + auto executionEnvironment = std::make_unique(); + executionEnvironment->prepareRootDeviceEnvironments(1); + auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); + drm_i915_gem_context_create_ext arg{}; + auto ret = IoctlHelper::ioctl(drm.get(), DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &arg); + EXPECT_EQ(0u, ret); + EXPECT_EQ(1u, drm->ioctlCallsCount); +} diff --git a/opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_xe_hp_sdv.cpp b/opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_upstream.cpp similarity index 84% rename from opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_xe_hp_sdv.cpp rename to opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_upstream.cpp index c77ee7d9ba..a679d23655 100644 --- a/opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_xe_hp_sdv.cpp +++ b/opencl/test/unit_test/os_interface/linux/ioctl_helper_tests_upstream.cpp @@ -15,9 +15,7 @@ using namespace NEO; -using IoctlHelperTestsXeHpSdv = ::testing::Test; - -XEHPTEST_F(IoctlHelperTestsXeHpSdv, givenXeHpSdvWhenCreateGemExtThenReturnCorrectValue) { +TEST(IoctlHelperTestsUpstream, givenUpstreamWhenCreateGemExtThenReturnCorrectValue) { auto executionEnvironment = std::make_unique(); executionEnvironment->prepareRootDeviceEnvironments(1); auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); @@ -28,7 +26,7 @@ XEHPTEST_F(IoctlHelperTestsXeHpSdv, givenXeHpSdvWhenCreateGemExtThenReturnCorrec regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; regionInfo[1].probed_size = 16 * GB; - auto ioctlHelper = IoctlHelper::get(defaultHwInfo->platform.eProductFamily); + auto ioctlHelper = IoctlHelper::get(drm.get()); uint32_t handle = 0; auto ret = ioctlHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); @@ -39,7 +37,7 @@ XEHPTEST_F(IoctlHelperTestsXeHpSdv, givenXeHpSdvWhenCreateGemExtThenReturnCorrec EXPECT_EQ(I915_MEMORY_CLASS_DEVICE, drm->memRegions.memory_class); } -XEHPTEST_F(IoctlHelperTestsXeHpSdv, givenXeHpSdvWhenCreateGemExtWithDebugFlagThenPrintDebugInfo) { +TEST(IoctlHelperTestsUpstream, givenUpstreamWhenCreateGemExtWithDebugFlagThenPrintDebugInfo) { DebugManagerStateRestore stateRestore; DebugManager.flags.PrintBOCreateDestroyResult.set(true); @@ -52,7 +50,7 @@ XEHPTEST_F(IoctlHelperTestsXeHpSdv, givenXeHpSdvWhenCreateGemExtWithDebugFlagThe regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; testing::internal::CaptureStdout(); - auto ioctlHelper = IoctlHelper::get(defaultHwInfo->platform.eProductFamily); + auto ioctlHelper = IoctlHelper::get(drm.get()); uint32_t handle = 0; ioctlHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); diff --git a/opencl/test/unit_test/os_interface/linux/prelim_helper_func.cpp b/opencl/test/unit_test/os_interface/linux/prelim_helper_func.cpp new file mode 100644 index 0000000000..f4a6980dfc --- /dev/null +++ b/opencl/test/unit_test/os_interface/linux/prelim_helper_func.cpp @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "test.h" + +#include "third_party/uapi/prelim/drm/i915_drm.h" + +int handlePrelimRequests(unsigned long request, void *arg) { + if (request == PRELIM_DRM_IOCTL_I915_GEM_CREATE_EXT) { + auto createExtParams = static_cast(arg); + if (createExtParams->size == 0) { + return EINVAL; + } + createExtParams->handle = 1u; + auto extensions = reinterpret_cast(createExtParams->extensions); + if (extensions == nullptr) { + return EINVAL; + } + auto setparamRegion = *extensions; + if (setparamRegion.base.name != PRELIM_I915_GEM_CREATE_EXT_SETPARAM) { + return EINVAL; + } + if ((setparamRegion.param.size == 0) || + (setparamRegion.param.param != (PRELIM_I915_OBJECT_PARAM | PRELIM_I915_PARAM_MEMORY_REGIONS))) { + return EINVAL; + } + auto data = reinterpret_cast(setparamRegion.param.data); + if (data == nullptr) { + return EINVAL; + } + + if ((data->memory_class != PRELIM_I915_MEMORY_CLASS_SYSTEM) && (data->memory_class != PRELIM_I915_MEMORY_CLASS_DEVICE)) { + return EINVAL; + } + } + return 0; +} diff --git a/opencl/test/unit_test/test_files/linux/devices/device/drm/card1/prelim_uapi_version b/opencl/test/unit_test/test_files/linux/devices/device/drm/card1/prelim_uapi_version new file mode 100644 index 0000000000..cd5ac039d6 --- /dev/null +++ b/opencl/test/unit_test/test_files/linux/devices/device/drm/card1/prelim_uapi_version @@ -0,0 +1 @@ +2.0 diff --git a/shared/source/os_interface/linux/CMakeLists.txt b/shared/source/os_interface/linux/CMakeLists.txt index 9fc552fcaf..ef318e8d0b 100644 --- a/shared/source/os_interface/linux/CMakeLists.txt +++ b/shared/source/os_interface/linux/CMakeLists.txt @@ -50,7 +50,8 @@ set(NEO_CORE_OS_INTERFACE_LINUX ${CMAKE_CURRENT_SOURCE_DIR}/linux_inc.cpp ${CMAKE_CURRENT_SOURCE_DIR}/ioctl_helper.h ${CMAKE_CURRENT_SOURCE_DIR}/ioctl_helper.cpp - ${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}ioctl_helper_default.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/ioctl_helper_prelim.cpp + ${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}ioctl_helper_getter.cpp ${CMAKE_CURRENT_SOURCE_DIR}/engine_info.h ${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}engine_info_impl.h ${CMAKE_CURRENT_SOURCE_DIR}/flags${BRANCH_DIR_SUFFIX}drm_query_flags.h @@ -104,5 +105,11 @@ else() ) endif() +if("${BRANCH_TYPE}" STREQUAL "") + list(APPEND NEO_CORE_OS_INTERFACE_LINUX + ${CMAKE_CURRENT_SOURCE_DIR}/ioctl_helper_upstream.cpp + ) +endif() + set_property(GLOBAL PROPERTY NEO_CORE_OS_INTERFACE_LINUX ${NEO_CORE_OS_INTERFACE_LINUX}) add_subdirectories() diff --git a/shared/source/os_interface/linux/drm_neo.cpp b/shared/source/os_interface/linux/drm_neo.cpp index 5d971997b6..16c1280af3 100644 --- a/shared/source/os_interface/linux/drm_neo.cpp +++ b/shared/source/os_interface/linux/drm_neo.cpp @@ -895,4 +895,18 @@ void Drm::setupSystemInfo(HardwareInfo *hwInfo, SystemInfo *sysInfo) { gtSysInfo->MaxDualSubSlicesSupported = sysInfo->getMaxDualSubSlicesSupported(); } +void Drm::getPrelimVersion(std::string &prelimVersion) { + std::string sysFsPciPath = getSysFsPciPath(); + std::string prelimVersionPath = sysFsPciPath + "/prelim_uapi_version"; + + std::ifstream ifs(prelimVersionPath.c_str(), std::ifstream::in); + + if (ifs.fail()) { + prelimVersion = ""; + } else { + ifs >> prelimVersion; + } + ifs.close(); +} + } // namespace NEO diff --git a/shared/source/os_interface/linux/drm_neo.h b/shared/source/os_interface/linux/drm_neo.h index b98acc9580..5ab83bcf82 100644 --- a/shared/source/os_interface/linux/drm_neo.h +++ b/shared/source/os_interface/linux/drm_neo.h @@ -147,6 +147,7 @@ class Drm : public DriverModel { int setupHardwareInfo(DeviceDescriptor *, bool); void setupSystemInfo(HardwareInfo *hwInfo, SystemInfo *sysInfo); void setupCacheInfo(const HardwareInfo &hwInfo); + MOCKABLE_VIRTUAL void getPrelimVersion(std::string &prelimVersion); PhysicalDevicePciBusInfo getPciBusInfo() const override; diff --git a/shared/source/os_interface/linux/drm_query.cpp b/shared/source/os_interface/linux/drm_query.cpp index 900e087ffa..4e370e3567 100644 --- a/shared/source/os_interface/linux/drm_query.cpp +++ b/shared/source/os_interface/linux/drm_query.cpp @@ -58,7 +58,7 @@ bool Drm::queryMemoryInfo() { auto length = 0; auto dataQuery = this->query(DRM_I915_QUERY_MEMORY_REGIONS, DrmQueryItemFlags::empty, length); if (dataQuery) { - auto ioctlHelper = IoctlHelper::get(pHwInfo->platform.eProductFamily); + auto ioctlHelper = IoctlHelper::get(this); auto data = ioctlHelper->translateIfRequired(dataQuery.release(), length); auto memRegions = reinterpret_cast(data.get()); this->memoryInfo.reset(new MemoryInfo(memRegions->regions, memRegions->num_regions)); diff --git a/shared/source/os_interface/linux/ioctl_helper.cpp b/shared/source/os_interface/linux/ioctl_helper.cpp index 6fde8652d5..3cdff85b64 100644 --- a/shared/source/os_interface/linux/ioctl_helper.cpp +++ b/shared/source/os_interface/linux/ioctl_helper.cpp @@ -11,16 +11,6 @@ namespace NEO { -IoctlHelper *ioctlHelperFactory[IGFX_MAX_PRODUCT] = {}; - -IoctlHelper *IoctlHelper::get(PRODUCT_FAMILY product) { - auto ioctlHelper = ioctlHelperFactory[product]; - if (!ioctlHelper) { - return IoctlHelperDefault::get(); - } - return ioctlHelper; -} - uint32_t IoctlHelper::ioctl(Drm *drm, unsigned long request, void *arg) { return drm->ioctl(request, arg); } diff --git a/shared/source/os_interface/linux/ioctl_helper.h b/shared/source/os_interface/linux/ioctl_helper.h index f71872faf4..dcd342f412 100644 --- a/shared/source/os_interface/linux/ioctl_helper.h +++ b/shared/source/os_interface/linux/ioctl_helper.h @@ -20,7 +20,8 @@ extern IoctlHelper *ioctlHelperFactory[IGFX_MAX_PRODUCT]; class IoctlHelper { public: - static IoctlHelper *get(PRODUCT_FAMILY product); + virtual ~IoctlHelper() {} + static IoctlHelper *get(Drm *product); static uint32_t ioctl(Drm *drm, unsigned long request, void *arg); virtual uint32_t createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) = 0; @@ -38,12 +39,14 @@ class IoctlHelperImpl : public IoctlHelper { std::unique_ptr translateIfRequired(uint8_t *dataQuery, int32_t length) override; }; -class IoctlHelperDefault : public IoctlHelper { +class IoctlHelperUpstream : public IoctlHelper { + public: + uint32_t createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) override; + std::unique_ptr translateIfRequired(uint8_t *dataQuery, int32_t length) override; +}; + +class IoctlHelperPrelim20 : public IoctlHelper { public: - static IoctlHelper *get() { - static IoctlHelperDefault instance; - return &instance; - } uint32_t createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) override; std::unique_ptr translateIfRequired(uint8_t *dataQuery, int32_t length) override; }; diff --git a/shared/source/os_interface/linux/ioctl_helper_default.cpp b/shared/source/os_interface/linux/ioctl_helper_default.cpp deleted file mode 100644 index b3baa8c187..0000000000 --- a/shared/source/os_interface/linux/ioctl_helper_default.cpp +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#include "shared/source/helpers/debug_helpers.h" -#include "shared/source/os_interface/linux/drm_neo.h" -#include "shared/source/os_interface/linux/ioctl_helper.h" - -namespace NEO { - -uint32_t IoctlHelperDefault::createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) { - DEBUG_BREAK_IF(true); - return -1; -} - -std::unique_ptr IoctlHelperDefault::translateIfRequired(uint8_t *dataQuery, int32_t length) { - DEBUG_BREAK_IF(true); - return std::unique_ptr(dataQuery); -} - -} // namespace NEO diff --git a/shared/source/os_interface/linux/ioctl_helper_getter.cpp b/shared/source/os_interface/linux/ioctl_helper_getter.cpp new file mode 100644 index 0000000000..3d91974be3 --- /dev/null +++ b/shared/source/os_interface/linux/ioctl_helper_getter.cpp @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/execution_environment/root_device_environment.h" +#include "shared/source/helpers/hw_info.h" +#include "shared/source/os_interface/linux/drm_neo.h" +#include "shared/source/os_interface/linux/ioctl_helper.h" + +#include +#include +#include + +namespace NEO { + +IoctlHelper *ioctlHelperFactory[IGFX_MAX_PRODUCT] = {}; + +std::map> ioctlHelperImpls{ + {"", std::make_shared()}, + {"2.0", std::make_shared()}}; + +IoctlHelper *IoctlHelper::get(Drm *drm) { + auto product = drm->getRootDeviceEnvironment().getHardwareInfo()->platform.eProductFamily; + + auto productSpecificIoctlHelper = ioctlHelperFactory[product]; + if (productSpecificIoctlHelper) { + return productSpecificIoctlHelper; + } + + std::string prelimVersion = ""; + drm->getPrelimVersion(prelimVersion); + return ioctlHelperImpls[prelimVersion].get(); +} + +} // namespace NEO diff --git a/shared/source/os_interface/linux/ioctl_helper_prelim.cpp b/shared/source/os_interface/linux/ioctl_helper_prelim.cpp new file mode 100644 index 0000000000..d663ed79ad --- /dev/null +++ b/shared/source/os_interface/linux/ioctl_helper_prelim.cpp @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/debug_settings/debug_settings_manager.h" +#include "shared/source/os_interface/linux/ioctl_helper.h" + +#include "third_party/uapi/prelim/drm/i915_drm.h" + +namespace NEO { + +uint32_t IoctlHelperPrelim20::createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) { + prelim_drm_i915_gem_object_param regionParam{}; + regionParam.size = dataSize; + regionParam.data = reinterpret_cast(data); + regionParam.param = PRELIM_I915_OBJECT_PARAM | PRELIM_I915_PARAM_MEMORY_REGIONS; + + prelim_drm_i915_gem_create_ext_setparam setparamRegion{}; + setparamRegion.base.name = PRELIM_I915_GEM_CREATE_EXT_SETPARAM; + setparamRegion.param = regionParam; + + prelim_drm_i915_gem_create_ext createExt{}; + createExt.size = allocSize; + createExt.extensions = reinterpret_cast(&setparamRegion); + + printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "Performing GEM_CREATE_EXT with { size: %lu, param: 0x%llX", + allocSize, regionParam.param); + + if (DebugManager.flags.PrintBOCreateDestroyResult.get()) { + for (uint32_t i = 0; i < dataSize; i++) { + auto region = reinterpret_cast(data)[i]; + printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, ", memory class: %d, memory instance: %d", + region.memory_class, region.memory_instance); + } + printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "%s", " }\n"); + } + + auto ret = IoctlHelper::ioctl(drm, PRELIM_DRM_IOCTL_I915_GEM_CREATE_EXT, &createExt); + + printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "GEM_CREATE_EXT has returned: %d BO-%u with size: %lu\n", ret, createExt.handle, createExt.size); + handle = createExt.handle; + return ret; +} + +std::unique_ptr IoctlHelperPrelim20::translateIfRequired(uint8_t *dataQuery, int32_t length) { + return std::unique_ptr(dataQuery); +} + +} // namespace NEO diff --git a/shared/source/os_interface/linux/local/xe_hp_sdv/ioctl_helper_xe_hp_sdv.cpp b/shared/source/os_interface/linux/ioctl_helper_upstream.cpp similarity index 80% rename from shared/source/os_interface/linux/local/xe_hp_sdv/ioctl_helper_xe_hp_sdv.cpp rename to shared/source/os_interface/linux/ioctl_helper_upstream.cpp index 75dae7282c..6b17be1228 100644 --- a/shared/source/os_interface/linux/local/xe_hp_sdv/ioctl_helper_xe_hp_sdv.cpp +++ b/shared/source/os_interface/linux/ioctl_helper_upstream.cpp @@ -8,13 +8,11 @@ #include "shared/source/debug_settings/debug_settings_manager.h" #include "shared/source/os_interface/linux/ioctl_helper.h" -#include "third_party/uapi/xe_hp_sdv/drm/i915_drm.h" +#include "third_party/uapi/drm/i915_drm.h" namespace NEO { -constexpr static auto gfxProduct = IGFX_XE_HP_SDV; -template <> -uint32_t IoctlHelperImpl::createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) { +uint32_t IoctlHelperUpstream::createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) { drm_i915_gem_create_ext_memory_regions memRegions; memRegions.num_regions = dataSize; memRegions.regions = reinterpret_cast(data); @@ -43,11 +41,8 @@ uint32_t IoctlHelperImpl::createGemExt(Drm *drm, void *data, uint32_ return ret; } -template <> -std::unique_ptr IoctlHelperImpl::translateIfRequired(uint8_t *dataQuery, int32_t length) { +std::unique_ptr IoctlHelperUpstream::translateIfRequired(uint8_t *dataQuery, int32_t length) { return std::unique_ptr(dataQuery); } -template class IoctlHelperImpl; - } // namespace NEO diff --git a/shared/source/os_interface/linux/local/xe_hp_sdv/CMakeLists.txt b/shared/source/os_interface/linux/local/xe_hp_sdv/CMakeLists.txt deleted file mode 100644 index 60345b2ea7..0000000000 --- a/shared/source/os_interface/linux/local/xe_hp_sdv/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (C) 2021 Intel Corporation -# -# SPDX-License-Identifier: MIT -# - -if(SUPPORT_XE_HP_SDV AND "${BRANCH_TYPE}" STREQUAL "") - set(NEO_CORE_OS_INTERFACE_LINUX_LOCAL_XE_HP_SDV - ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt - ${CMAKE_CURRENT_SOURCE_DIR}/ioctl_helper_xe_hp_sdv.cpp - ) - set_property(GLOBAL APPEND PROPERTY NEO_CORE_OS_INTERFACE_LINUX ${NEO_CORE_OS_INTERFACE_LINUX_LOCAL_XE_HP_SDV}) -endif() diff --git a/shared/source/os_interface/linux/local/xe_hp_sdv/enable_ioctl_helper_xe_hp_sdv.cpp b/shared/source/os_interface/linux/local/xe_hp_sdv/enable_ioctl_helper_xe_hp_sdv.cpp deleted file mode 100644 index 6728bab2de..0000000000 --- a/shared/source/os_interface/linux/local/xe_hp_sdv/enable_ioctl_helper_xe_hp_sdv.cpp +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#include "shared/source/os_interface/linux/ioctl_helper.h" - -namespace NEO { -extern IoctlHelper *ioctlHelperFactory[IGFX_MAX_PRODUCT]; - -struct EnableProductIoctlHelperXeHpSdv { - EnableProductIoctlHelperXeHpSdv() { - IoctlHelper *pIoctlHelper = IoctlHelperImpl::get(); - ioctlHelperFactory[IGFX_XE_HP_SDV] = pIoctlHelper; - } -}; - -static EnableProductIoctlHelperXeHpSdv enableIoctlHelperXeHpSdv; -} // namespace NEO diff --git a/shared/source/os_interface/linux/memory_info.cpp b/shared/source/os_interface/linux/memory_info.cpp index 6a24201966..4720bc2f59 100644 --- a/shared/source/os_interface/linux/memory_info.cpp +++ b/shared/source/os_interface/linux/memory_info.cpp @@ -19,8 +19,7 @@ namespace NEO { uint32_t MemoryInfo::createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) { - auto pHwInfo = drm->getRootDeviceEnvironment().getHardwareInfo(); - return IoctlHelper::get(pHwInfo->platform.eProductFamily)->createGemExt(drm, data, dataSize, allocSize, handle); + return IoctlHelper::get(drm)->createGemExt(drm, data, dataSize, allocSize, handle); } drm_i915_gem_memory_class_instance MemoryInfo::getMemoryRegionClassAndInstance(uint32_t memoryBank, const HardwareInfo &hwInfo) { diff --git a/third_party/uapi/xe_hp_sdv/drm/drm.h b/third_party/uapi/prelim/drm/drm.h similarity index 83% rename from third_party/uapi/xe_hp_sdv/drm/drm.h rename to third_party/uapi/prelim/drm/drm.h index 3b810b53ba..f64e6b8091 100644 --- a/third_party/uapi/xe_hp_sdv/drm/drm.h +++ b/third_party/uapi/prelim/drm/drm.h @@ -1,10 +1,11 @@ -/* +/** + * \file drm.h * Header for the Direct Rendering Manager * - * Author: Rickard E. (Rik) Faith + * \author Rickard E. (Rik) Faith * - * Acknowledgments: - * Dec 1999, Richard Henderson , move to generic cmpxchg. + * \par Acknowledgments: + * Dec 1999, Richard Henderson , move to generic \c cmpxchg. */ /* @@ -35,13 +36,7 @@ #ifndef _DRM_H_ #define _DRM_H_ -#if defined(__KERNEL__) - -#include -#include -typedef unsigned int drm_handle_t; - -#elif defined(__linux__) +#if defined(__linux__) #include #include @@ -84,7 +79,7 @@ typedef unsigned int drm_context_t; typedef unsigned int drm_drawable_t; typedef unsigned int drm_magic_t; -/* +/** * Cliprect. * * \warning: If you change this structure, make sure you change @@ -100,7 +95,7 @@ struct drm_clip_rect { unsigned short y2; }; -/* +/** * Drawable information. */ struct drm_drawable_info { @@ -108,7 +103,7 @@ struct drm_drawable_info { struct drm_clip_rect *rects; }; -/* +/** * Texture region, */ struct drm_tex_region { @@ -119,7 +114,7 @@ struct drm_tex_region { unsigned int age; }; -/* +/** * Hardware lock. * * The lock structure is a simple cache-line aligned integer. To avoid @@ -131,7 +126,7 @@ struct drm_hw_lock { char padding[60]; /**< Pad to cache line */ }; -/* +/** * DRM_IOCTL_VERSION ioctl argument type. * * \sa drmGetVersion(). @@ -141,33 +136,33 @@ struct drm_version { int version_minor; /**< Minor version */ int version_patchlevel; /**< Patch level */ __kernel_size_t name_len; /**< Length of name buffer */ - char __user *name; /**< Name of driver */ + char *name; /**< Name of driver */ __kernel_size_t date_len; /**< Length of date buffer */ - char __user *date; /**< User-space buffer to hold date */ + char *date; /**< User-space buffer to hold date */ __kernel_size_t desc_len; /**< Length of desc buffer */ - char __user *desc; /**< User-space buffer to hold desc */ + char *desc; /**< User-space buffer to hold desc */ }; -/* +/** * DRM_IOCTL_GET_UNIQUE ioctl argument type. * * \sa drmGetBusid() and drmSetBusId(). */ struct drm_unique { __kernel_size_t unique_len; /**< Length of unique */ - char __user *unique; /**< Unique name for driver instantiation */ + char *unique; /**< Unique name for driver instantiation */ }; struct drm_list { int count; /**< Length of user-space structures */ - struct drm_version __user *version; + struct drm_version *version; }; struct drm_block { int unused; }; -/* +/** * DRM_IOCTL_CONTROL ioctl argument type. * * \sa drmCtlInstHandler() and drmCtlUninstHandler(). @@ -182,7 +177,7 @@ struct drm_control { int irq; }; -/* +/** * Type of memory to map. */ enum drm_map_type { @@ -194,7 +189,7 @@ enum drm_map_type { _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ }; -/* +/** * Memory mapping flags. */ enum drm_map_flags { @@ -213,7 +208,7 @@ struct drm_ctx_priv_map { void *handle; /**< Handle of map */ }; -/* +/** * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls * argument type. * @@ -230,7 +225,7 @@ struct drm_map { /* Private data */ }; -/* +/** * DRM_IOCTL_GET_CLIENT ioctl argument type. */ struct drm_client { @@ -262,7 +257,7 @@ enum drm_stat_type { /* Add to the *END* of the list */ }; -/* +/** * DRM_IOCTL_GET_STATS ioctl argument type. */ struct drm_stats { @@ -273,7 +268,7 @@ struct drm_stats { } data[15]; }; -/* +/** * Hardware locking flags. */ enum drm_lock_flags { @@ -288,7 +283,7 @@ enum drm_lock_flags { _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ }; -/* +/** * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. * * \sa drmGetLock() and drmUnlock(). @@ -298,7 +293,7 @@ struct drm_lock { enum drm_lock_flags flags; }; -/* +/** * DMA flags * * \warning @@ -327,7 +322,7 @@ enum drm_dma_flags { _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ }; -/* +/** * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. * * \sa drmAddBufs(). @@ -350,23 +345,23 @@ struct drm_buf_desc { */ }; -/* +/** * DRM_IOCTL_INFO_BUFS ioctl argument type. */ struct drm_buf_info { int count; /**< Entries in list */ - struct drm_buf_desc __user *list; + struct drm_buf_desc *list; }; -/* +/** * DRM_IOCTL_FREE_BUFS ioctl argument type. */ struct drm_buf_free { int count; - int __user *list; + int *list; }; -/* +/** * Buffer information * * \sa drm_buf_map. @@ -375,23 +370,23 @@ struct drm_buf_pub { int idx; /**< Index into the master buffer list */ int total; /**< Buffer size */ int used; /**< Amount of buffer in use (for DMA) */ - void __user *address; /**< Address of buffer */ + void *address; /**< Address of buffer */ }; -/* +/** * DRM_IOCTL_MAP_BUFS ioctl argument type. */ struct drm_buf_map { int count; /**< Length of the buffer list */ #ifdef __cplusplus - void __user *virt; + void *virt; #else - void __user *virtual; /**< Mmap'd area in user-virtual */ + void *virtual; /**< Mmap'd area in user-virtual */ #endif - struct drm_buf_pub __user *list; /**< Buffer information */ + struct drm_buf_pub *list; /**< Buffer information */ }; -/* +/** * DRM_IOCTL_DMA ioctl argument type. * * Indices here refer to the offset into the buffer list in drm_buf_get. @@ -401,13 +396,13 @@ struct drm_buf_map { struct drm_dma { int context; /**< Context handle */ int send_count; /**< Number of buffers to send */ - int __user *send_indices; /**< List of handles to buffers */ - int __user *send_sizes; /**< Lengths of data to send */ + int *send_indices; /**< List of handles to buffers */ + int *send_sizes; /**< Lengths of data to send */ enum drm_dma_flags flags; /**< Flags */ int request_count; /**< Number of buffers requested */ int request_size; /**< Desired size for buffers */ - int __user *request_indices; /**< Buffer information */ - int __user *request_sizes; + int *request_indices; /**< Buffer information */ + int *request_sizes; int granted_count; /**< Number of buffers granted */ }; @@ -416,7 +411,7 @@ enum drm_ctx_flags { _DRM_CONTEXT_2DONLY = 0x02 }; -/* +/** * DRM_IOCTL_ADD_CTX ioctl argument type. * * \sa drmCreateContext() and drmDestroyContext(). @@ -426,22 +421,22 @@ struct drm_ctx { enum drm_ctx_flags flags; }; -/* +/** * DRM_IOCTL_RES_CTX ioctl argument type. */ struct drm_ctx_res { int count; - struct drm_ctx __user *contexts; + struct drm_ctx *contexts; }; -/* +/** * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. */ struct drm_draw { drm_drawable_t handle; }; -/* +/** * DRM_IOCTL_UPDATE_DRAW ioctl argument type. */ typedef enum { @@ -455,14 +450,14 @@ struct drm_update_draw { unsigned long long data; }; -/* +/** * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. */ struct drm_auth { drm_magic_t magic; }; -/* +/** * DRM_IOCTL_IRQ_BUSID ioctl argument type. * * \sa drmGetInterruptFromBusID(). @@ -504,7 +499,7 @@ struct drm_wait_vblank_reply { long tval_usec; }; -/* +/** * DRM_IOCTL_WAIT_VBLANK ioctl argument type. * * \sa drmWaitVBlank(). @@ -517,7 +512,7 @@ union drm_wait_vblank { #define _DRM_PRE_MODESET 1 #define _DRM_POST_MODESET 2 -/* +/** * DRM_IOCTL_MODESET_CTL ioctl argument type * * \sa drmModesetCtl(). @@ -527,7 +522,7 @@ struct drm_modeset_ctl { __u32 cmd; }; -/* +/** * DRM_IOCTL_AGP_ENABLE ioctl argument type. * * \sa drmAgpEnable(). @@ -536,7 +531,7 @@ struct drm_agp_mode { unsigned long mode; /**< AGP mode */ }; -/* +/** * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. * * \sa drmAgpAlloc() and drmAgpFree(). @@ -548,7 +543,7 @@ struct drm_agp_buffer { unsigned long physical; /**< Physical used by i810 */ }; -/* +/** * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. * * \sa drmAgpBind() and drmAgpUnbind(). @@ -558,7 +553,7 @@ struct drm_agp_binding { unsigned long offset; /**< In bytes -- will round to page boundary */ }; -/* +/** * DRM_IOCTL_AGP_INFO ioctl argument type. * * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), @@ -579,7 +574,7 @@ struct drm_agp_info { unsigned short id_device; }; -/* +/** * DRM_IOCTL_SG_ALLOC ioctl argument type. */ struct drm_scatter_gather { @@ -587,7 +582,7 @@ struct drm_scatter_gather { unsigned long handle; /**< Used for mapping / unmapping */ }; -/* +/** * DRM_IOCTL_SET_VERSION ioctl argument type. */ struct drm_set_version { @@ -597,14 +592,14 @@ struct drm_set_version { int drm_dd_minor; }; -/* DRM_IOCTL_GEM_CLOSE ioctl argument type */ +/** DRM_IOCTL_GEM_CLOSE ioctl argument type */ struct drm_gem_close { /** Handle of the object to be closed. */ __u32 handle; __u32 pad; }; -/* DRM_IOCTL_GEM_FLINK ioctl argument type */ +/** DRM_IOCTL_GEM_FLINK ioctl argument type */ struct drm_gem_flink { /** Handle for the object being named */ __u32 handle; @@ -613,7 +608,7 @@ struct drm_gem_flink { __u32 name; }; -/* DRM_IOCTL_GEM_OPEN ioctl argument type */ +/** DRM_IOCTL_GEM_OPEN ioctl argument type */ struct drm_gem_open { /** Name of object being opened */ __u32 name; @@ -625,150 +620,33 @@ struct drm_gem_open { __u64 size; }; -/** - * DRM_CAP_DUMB_BUFFER - * - * If set to 1, the driver supports creating dumb buffers via the - * &DRM_IOCTL_MODE_CREATE_DUMB ioctl. - */ #define DRM_CAP_DUMB_BUFFER 0x1 -/** - * DRM_CAP_VBLANK_HIGH_CRTC - * - * If set to 1, the kernel supports specifying a :ref:`CRTC index` - * in the high bits of &drm_wait_vblank_request.type. - * - * Starting kernel version 2.6.39, this capability is always set to 1. - */ #define DRM_CAP_VBLANK_HIGH_CRTC 0x2 -/** - * DRM_CAP_DUMB_PREFERRED_DEPTH - * - * The preferred bit depth for dumb buffers. - * - * The bit depth is the number of bits used to indicate the color of a single - * pixel excluding any padding. This is different from the number of bits per - * pixel. For instance, XRGB8888 has a bit depth of 24 but has 32 bits per - * pixel. - * - * Note that this preference only applies to dumb buffers, it's irrelevant for - * other types of buffers. - */ #define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 -/** - * DRM_CAP_DUMB_PREFER_SHADOW - * - * If set to 1, the driver prefers userspace to render to a shadow buffer - * instead of directly rendering to a dumb buffer. For best speed, userspace - * should do streaming ordered memory copies into the dumb buffer and never - * read from it. - * - * Note that this preference only applies to dumb buffers, it's irrelevant for - * other types of buffers. - */ #define DRM_CAP_DUMB_PREFER_SHADOW 0x4 -/** - * DRM_CAP_PRIME - * - * Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT - * and &DRM_PRIME_CAP_EXPORT. - * - * PRIME buffers are exposed as dma-buf file descriptors. See - * Documentation/gpu/drm-mm.rst, section "PRIME Buffer Sharing". - */ #define DRM_CAP_PRIME 0x5 -/** - * DRM_PRIME_CAP_IMPORT - * - * If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME - * buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl. - */ #define DRM_PRIME_CAP_IMPORT 0x1 -/** - * DRM_PRIME_CAP_EXPORT - * - * If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME - * buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl. - */ #define DRM_PRIME_CAP_EXPORT 0x2 -/** - * DRM_CAP_TIMESTAMP_MONOTONIC - * - * If set to 0, the kernel will report timestamps with ``CLOCK_REALTIME`` in - * struct drm_event_vblank. If set to 1, the kernel will report timestamps with - * ``CLOCK_MONOTONIC``. See ``clock_gettime(2)`` for the definition of these - * clocks. - * - * Starting from kernel version 2.6.39, the default value for this capability - * is 1. Starting kernel version 4.15, this capability is always set to 1. - */ #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 -/** - * DRM_CAP_ASYNC_PAGE_FLIP - * - * If set to 1, the driver supports &DRM_MODE_PAGE_FLIP_ASYNC. - */ #define DRM_CAP_ASYNC_PAGE_FLIP 0x7 -/** - * DRM_CAP_CURSOR_WIDTH - * - * The ``CURSOR_WIDTH`` and ``CURSOR_HEIGHT`` capabilities return a valid - * width x height combination for the hardware cursor. The intention is that a - * hardware agnostic userspace can query a cursor plane size to use. +/* + * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight + * combination for the hardware cursor. The intention is that a hardware + * agnostic userspace can query a cursor plane size to use. * * Note that the cross-driver contract is to merely return a valid size; * drivers are free to attach another meaning on top, eg. i915 returns the * maximum plane size. */ #define DRM_CAP_CURSOR_WIDTH 0x8 -/** - * DRM_CAP_CURSOR_HEIGHT - * - * See &DRM_CAP_CURSOR_WIDTH. - */ #define DRM_CAP_CURSOR_HEIGHT 0x9 -/** - * DRM_CAP_ADDFB2_MODIFIERS - * - * If set to 1, the driver supports supplying modifiers in the - * &DRM_IOCTL_MODE_ADDFB2 ioctl. - */ #define DRM_CAP_ADDFB2_MODIFIERS 0x10 -/** - * DRM_CAP_PAGE_FLIP_TARGET - * - * If set to 1, the driver supports the &DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE and - * &DRM_MODE_PAGE_FLIP_TARGET_RELATIVE flags in - * &drm_mode_crtc_page_flip_target.flags for the &DRM_IOCTL_MODE_PAGE_FLIP - * ioctl. - */ #define DRM_CAP_PAGE_FLIP_TARGET 0x11 -/** - * DRM_CAP_CRTC_IN_VBLANK_EVENT - * - * If set to 1, the kernel supports reporting the CRTC ID in - * &drm_event_vblank.crtc_id for the &DRM_EVENT_VBLANK and - * &DRM_EVENT_FLIP_COMPLETE events. - * - * Starting kernel version 4.12, this capability is always set to 1. - */ #define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 -/** - * DRM_CAP_SYNCOBJ - * - * If set to 1, the driver supports sync objects. See - * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects". - */ #define DRM_CAP_SYNCOBJ 0x13 -/** - * DRM_CAP_SYNCOBJ_TIMELINE - * - * If set to 1, the driver supports timeline operations on sync objects. See - * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects". - */ #define DRM_CAP_SYNCOBJ_TIMELINE 0x14 -/* DRM_IOCTL_GET_CAP ioctl argument type */ +/** DRM_IOCTL_GET_CAP ioctl argument type */ struct drm_get_cap { __u64 capability; __u64 value; @@ -777,12 +655,9 @@ struct drm_get_cap { /** * DRM_CLIENT_CAP_STEREO_3D * - * If set to 1, the DRM core will expose the stereo 3D capabilities of the + * if set to 1, the DRM core will expose the stereo 3D capabilities of the * monitor by advertising the supported 3D layouts in the flags of struct - * drm_mode_modeinfo. See ``DRM_MODE_FLAG_3D_*``. - * - * This capability is always supported for all drivers starting from kernel - * version 3.13. + * drm_mode_modeinfo. */ #define DRM_CLIENT_CAP_STEREO_3D 1 @@ -791,9 +666,6 @@ struct drm_get_cap { * * If set to 1, the DRM core will expose all planes (overlay, primary, and * cursor) to userspace. - * - * This capability has been introduced in kernel version 3.15. Starting from - * kernel version 3.17, this capability is always supported for all drivers. */ #define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 @@ -803,13 +675,6 @@ struct drm_get_cap { * If set to 1, the DRM core will expose atomic properties to userspace. This * implicitly enables &DRM_CLIENT_CAP_UNIVERSAL_PLANES and * &DRM_CLIENT_CAP_ASPECT_RATIO. - * - * If the driver doesn't support atomic mode-setting, enabling this capability - * will fail with -EOPNOTSUPP. - * - * This capability has been introduced in kernel version 4.0. Starting from - * kernel version 4.2, this capability is always supported for atomic-capable - * drivers. */ #define DRM_CLIENT_CAP_ATOMIC 3 @@ -817,10 +682,6 @@ struct drm_get_cap { * DRM_CLIENT_CAP_ASPECT_RATIO * * If set to 1, the DRM core will provide aspect ratio information in modes. - * See ``DRM_MODE_FLAG_PIC_AR_*``. - * - * This capability is always supported for all drivers starting from kernel - * version 4.18. */ #define DRM_CLIENT_CAP_ASPECT_RATIO 4 @@ -828,15 +689,20 @@ struct drm_get_cap { * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS * * If set to 1, the DRM core will expose special connectors to be used for - * writing back to memory the scene setup in the commit. The client must enable - * &DRM_CLIENT_CAP_ATOMIC first. - * - * This capability is always supported for atomic-capable drivers starting from - * kernel version 4.19. + * writing back to memory the scene setup in the commit. Depends on client + * also supporting DRM_CLIENT_CAP_ATOMIC */ #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 -/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ +/** + * Add support for advance gamma mode UAPI + * If set to 1, DRM will enable advance gamma mode + * UAPI to process the gamma mode based on extended + * range and segments. + */ +#define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6 + +/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ struct drm_set_client_cap { __u64 capability; __u64 value; @@ -1050,16 +916,6 @@ extern "C" { #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) -/** - * DRM_IOCTL_MODE_RMFB - Remove a framebuffer. - * - * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL - * argument is a framebuffer object ID. - * - * Warning: removing a framebuffer currently in-use on an enabled plane will - * disable that plane. The CRTC the plane is linked to may also be disabled - * (depending on driver capabilities). - */ #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) #define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) #define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) @@ -1098,7 +954,7 @@ extern "C" { #define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2) -/* +/** * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x9f. * Generic IOCTLS restart at 0xA0. @@ -1109,7 +965,7 @@ extern "C" { #define DRM_COMMAND_BASE 0x40 #define DRM_COMMAND_END 0xA0 -/* +/** * Header for events written back to userspace on the drm fd. The * type defines the type of event, the length specifies the total * length of the event (including the header), and user_data is @@ -1150,7 +1006,6 @@ struct drm_event_crtc_sequence { }; /* typedef area */ -#ifndef __KERNEL__ typedef struct drm_clip_rect drm_clip_rect_t; typedef struct drm_drawable_info drm_drawable_info_t; typedef struct drm_tex_region drm_tex_region_t; @@ -1192,7 +1047,6 @@ typedef struct drm_agp_binding drm_agp_binding_t; typedef struct drm_agp_info drm_agp_info_t; typedef struct drm_scatter_gather drm_scatter_gather_t; typedef struct drm_set_version drm_set_version_t; -#endif #if defined(__cplusplus) } diff --git a/third_party/uapi/xe_hp_sdv/drm/drm_fourcc.h b/third_party/uapi/prelim/drm/drm_fourcc.h similarity index 61% rename from third_party/uapi/xe_hp_sdv/drm/drm_fourcc.h rename to third_party/uapi/prelim/drm/drm_fourcc.h index 17dc3a817b..e4b64426b3 100644 --- a/third_party/uapi/xe_hp_sdv/drm/drm_fourcc.h +++ b/third_party/uapi/prelim/drm/drm_fourcc.h @@ -24,7 +24,6 @@ #ifndef DRM_FOURCC_H #define DRM_FOURCC_H -#define __user #include "drm.h" #if defined(__cplusplus) @@ -59,6 +58,30 @@ extern "C" { * may preserve meaning - such as number of planes - from the fourcc code, * whereas others may not. * + * Modifiers must uniquely encode buffer layout. In other words, a buffer must + * match only a single modifier. A modifier must not be a subset of layouts of + * another modifier. For instance, it's incorrect to encode pitch alignment in + * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel + * aligned modifier. That said, modifiers can have implicit minimal + * requirements. + * + * For modifiers where the combination of fourcc code and modifier can alias, + * a canonical pair needs to be defined and used by all drivers. Preferred + * combinations are also encouraged where all combinations might lead to + * confusion and unnecessarily reduced interoperability. An example for the + * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. + * + * There are two kinds of modifier users: + * + * - Kernel and user-space drivers: for drivers it's important that modifiers + * don't alias, otherwise two drivers might support the same format but use + * different aliases, preventing them from sharing buffers in an efficient + * format. + * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users + * see modifiers as opaque tokens they can check for equality and intersect. + * These users musn't need to know to reason about the modifier value + * (i.e. they are not expected to extract information out of the modifier). + * * Vendors should document their modifier usage in as much detail as * possible, to ensure maximum compatibility across devices, drivers and * applications. @@ -156,6 +179,12 @@ extern "C" { #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +/* + * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits + * of unused padding per component: + */ +#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ + /* packed YCbCr */ #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ @@ -237,6 +266,12 @@ extern "C" { #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ +/* + * 2 plane YCbCr + * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian + * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian + */ +#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ /* * 2 plane YCbCr MSB aligned @@ -266,6 +301,22 @@ extern "C" { */ #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ +/* 3 plane non-subsampled (444) YCbCr + * 16 bits per component, but only 10 bits are used and 6 bits are padded + * index 0: Y plane, [15:0] Y:x [10:6] little endian + * index 1: Cb plane, [15:0] Cb:x [10:6] little endian + * index 2: Cr plane, [15:0] Cr:x [10:6] little endian + */ +#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') + +/* 3 plane non-subsampled (444) YCrCb + * 16 bits per component, but only 10 bits are used and 6 bits are padded + * index 0: Y plane, [15:0] Y:x [10:6] little endian + * index 1: Cr plane, [15:0] Cr:x [10:6] little endian + * index 2: Cb plane, [15:0] Cb:x [10:6] little endian + */ +#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') + /* * 3 plane YCbCr * index 0: Y plane, [7:0] Y @@ -299,7 +350,6 @@ extern "C" { */ /* Vendor Ids: */ -#define DRM_FORMAT_MOD_NONE 0 #define DRM_FORMAT_MOD_VENDOR_NONE 0 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 @@ -310,6 +360,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 +#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a /* add more to the end as needed */ @@ -318,14 +369,49 @@ extern "C" { #define fourcc_mod_code(vendor, val) \ ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) +/* + * Intel modifiers for new platforms should be added using the PRELIM_ prefix + * and the intel_prelim_fourcc_mod_code macro, while the upstreaming of the + * platform should happen without the prefix using the fourcc_mod_code macro. + */ +#define INTEL_PRELIM_ID_FLAG (1ULL << 55) + +#define intel_prelim_fourcc_mod_code(val) \ + (fourcc_mod_code(INTEL, (val)) | INTEL_PRELIM_ID_FLAG) + /* * Format Modifier tokens: * * When adding a new token please document the layout with a code comment, * similar to the fourcc codes above. drm_fourcc.h is considered the * authoritative source for all of these. + * + * Generic modifier names: + * + * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names + * for layouts which are common across multiple vendors. To preserve + * compatibility, in cases where a vendor-specific definition already exists and + * a generic name for it is desired, the common name is a purely symbolic alias + * and must use the same numerical value as the original definition. + * + * Note that generic names should only be used for modifiers which describe + * generic layouts (such as pixel re-ordering), which may have + * independently-developed support across multiple vendors. + * + * In future cases where a generic layout is identified before merging with a + * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor + * 'NONE' could be considered. This should only be for obvious, exceptional + * cases to avoid polluting the 'GENERIC' namespace with modifiers which only + * apply to a single vendor. + * + * Generic names should not be used for cases where multiple hardware vendors + * have implementations of the same standardised compression scheme (such as + * AFBC). In those cases, all implementations should use the same format + * modifier(s), reflecting the vendor of the standard. */ +#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE + /* * Invalid Modifier * @@ -345,6 +431,16 @@ extern "C" { */ #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) +/* + * Deprecated: use DRM_FORMAT_MOD_LINEAR instead + * + * The "none" format modifier doesn't actually mean that the modifier is + * implicit, instead it means that the layout is linear. Whether modifiers are + * used is out-of-band information carried in an API-specific way (e.g. in a + * flag for drm_mode_fb_cmd2). + */ +#define DRM_FORMAT_MOD_NONE 0 + /* Intel framebuffer modifiers */ /* @@ -355,9 +451,12 @@ extern "C" { * a platform-dependent stride. On top of that the memory can apply * platform-depending swizzling of some higher address bits into bit6. * - * This format is highly platforms specific and not useful for cross-driver - * sharing. It exists since on a given platform it does uniquely identify the - * layout in a simple way for i915-specific userspace. + * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. + * On earlier platforms the is highly platforms specific and not useful for + * cross-driver sharing. It exists since on a given platform it does uniquely + * identify the layout in a simple way for i915-specific userspace, which + * facilitated conversion of userspace to modifiers. Additionally the exact + * format on some really old platforms is not known. */ #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) @@ -370,9 +469,12 @@ extern "C" { * memory can apply platform-depending swizzling of some higher address bits * into bit6. * - * This format is highly platforms specific and not useful for cross-driver - * sharing. It exists since on a given platform it does uniquely identify the - * layout in a simple way for i915-specific userspace. + * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. + * On earlier platforms the is highly platforms specific and not useful for + * cross-driver sharing. It exists since on a given platform it does uniquely + * identify the layout in a simple way for i915-specific userspace, which + * facilitated conversion of userspace to modifiers. Additionally the exact + * format on some really old platforms is not known. */ #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) @@ -435,29 +537,71 @@ extern "C" { */ #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) -/* ID #8 is reserved for TGL CCS_CC */ +/* + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render + * compression. + * + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear + * and at index 1. The clear color is stored at index 2, and the pitch should + * be ignored. The clear color structure is 256 bits. The first 128 bits + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented + * by 32 bits. The raw clear color is consumed by the 3d engine and generates + * the converted clear color of size 64 bits. The first 32 bits store the Lower + * Converted Clear Color value and the next 32 bits store the Higher Converted + * Clear Color value when applicable. The Converted Clear Color values are + * consumed by the DE. The last 64 bits are used to store Color Discard Enable + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line + * corresponds to an area of 4x1 tiles in the main surface. The main surface + * pitch is required to be a multiple of 4 tile widths. + */ +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) /* - * Intel color control surfaces (CCS) for DG1 render compression. - * - * The layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, but since - * DG1 may have a different hashing/compression algorithm, the actual contents - * of compressed buffers may not be safely shareable between TGL and DG1, hence - * the new modifier assignment. + * TODO: Remove the non-PRELIM version of DG2 CCS modifiers in the 9-11 ID range + * Backport the upstream ADL-P CCS modifiers using the 9-11 ID range. */ -#define I915_FORMAT_MOD_Y_TILED_DG1_RC_CCS fourcc_mod_code(INTEL, 9) /* - * Intel color control surfaces (CCS) for Gen-12 media compression + * Intel F-tiling(aka Tile4) layout * - * The layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, but since - * DG1 may have a different hashing/compression algorithm, the actual contents - * of compressed buffers may not be safely shareable between TGL and DG1, hence - * the new modifier assignment. + * This is a tiled layout using 4Kb tiles in row-major layout. + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD + * (16 bytes) chunks column-major.. */ -#define I915_FORMAT_MOD_Y_TILED_DG1_MC_CCS fourcc_mod_code(INTEL, 10) +#define I915_FORMAT_MOD_F_TILED fourcc_mod_code(INTEL, 12) -/* ID #11 is reserved for DG1 CCS_CC */ +/* + * Intel color control surfaces (CCS) for DG2 render compression. + * + * DG2 uses a new compression format for render compression. The general + * layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, + * but a new hashing/compression algorithm is used, so a fresh modifier must + * be associated with buffers of this type. Render compression uses 128 byte + * compression blocks. + */ +#define I915_FORMAT_MOD_F_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 9) +#define PRELIM_I915_FORMAT_MOD_F_TILED_DG2_RC_CCS intel_prelim_fourcc_mod_code(13) + +/* + * Intel color control surfaces (CCS) for DG2 media compression. + * + * DG2 uses a new compression format for media compression. The general + * layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, + * but a new hashing/compression algorithm is used, so a fresh modifier must + * be associated with buffers of this type. Media compression uses 256 byte + * compression blocks. + */ +#define I915_FORMAT_MOD_F_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 10) +#define PRELIM_I915_FORMAT_MOD_F_TILED_DG2_MC_CCS intel_prelim_fourcc_mod_code(14) + +/* + * Intel color control surfaces (CCS) for DG2 clear color render compression. + * + * DG2 uses a unified compression format for clear color render compression. + * The general layout is a tiled layout using 4Kb tiles i.e. Tile4 layout. + */ +#define I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 11) +#define PRELIM_I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC intel_prelim_fourcc_mod_code(15) /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks @@ -546,7 +690,113 @@ extern "C" { #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) /* - * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later + * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, + * and Tegra GPUs starting with Tegra K1. + * + * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies + * based on the architecture generation. GOBs themselves are then arranged in + * 3D blocks, with the block dimensions (in terms of GOBs) always being a power + * of two, and hence expressible as their log2 equivalent (E.g., "2" represents + * a block depth or height of "4"). + * + * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format + * in full detail. + * + * Macro + * Bits Param Description + * ---- ----- ----------------------------------------------------------------- + * + * 3:0 h log2(height) of each block, in GOBs. Placed here for + * compatibility with the existing + * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. + * + * 4:4 - Must be 1, to indicate block-linear layout. Necessary for + * compatibility with the existing + * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. + * + * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block + * size). Must be zero. + * + * Note there is no log2(width) parameter. Some portions of the + * hardware support a block width of two gobs, but it is impractical + * to use due to lack of support elsewhere, and has no known + * benefits. + * + * 11:9 - Reserved (To support 2D-array textures with variable array stride + * in blocks, specified via log2(tile width in blocks)). Must be + * zero. + * + * 19:12 k Page Kind. This value directly maps to a field in the page + * tables of all GPUs >= NV50. It affects the exact layout of bits + * in memory and can be derived from the tuple + * + * (format, GPU model, compression type, samples per pixel) + * + * Where compression type is defined below. If GPU model were + * implied by the format modifier, format, or memory buffer, page + * kind would not need to be included in the modifier itself, but + * since the modifier should define the layout of the associated + * memory buffer independent from any device or other context, it + * must be included here. + * + * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed + * starting with Fermi GPUs. Additionally, the mapping between page + * kind and bit layout has changed at various points. + * + * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping + * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping + * 2 = Gob Height 8, Turing+ Page Kind mapping + * 3 = Reserved for future use. + * + * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further + * bit remapping step that occurs at an even lower level than the + * page kind and block linear swizzles. This causes the layout of + * surfaces mapped in those SOC's GPUs to be incompatible with the + * equivalent mapping on other GPUs in the same system. + * + * 0 = Tegra K1 - Tegra Parker/TX2 Layout. + * 1 = Desktop GPU and Tegra Xavier+ Layout + * + * 25:23 c Lossless Framebuffer Compression type. + * + * 0 = none + * 1 = ROP/3D, layout 1, exact compression format implied by Page + * Kind field + * 2 = ROP/3D, layout 2, exact compression format implied by Page + * Kind field + * 3 = CDE horizontal + * 4 = CDE vertical + * 5 = Reserved for future use + * 6 = Reserved for future use + * 7 = Reserved for future use + * + * 55:25 - Reserved for future use. Must be zero. + */ +#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ + fourcc_mod_code(NVIDIA, (0x10 | \ + ((h) & 0xf) | \ + (((k) & 0xff) << 12) | \ + (((g) & 0x3) << 20) | \ + (((s) & 0x1) << 22) | \ + (((c) & 0x7) << 23))) + +/* To grandfather in prior block linear format modifiers to the above layout, + * the page kind "0", which corresponds to "pitch/linear" and hence is unusable + * with block-linear layouts, is remapped within drivers to the value 0xfe, + * which corresponds to the "generic" kind used for simple single-sample + * uncompressed color formats on Fermi - Volta GPUs. + */ +static __inline__ __u64 +drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) +{ + if (!(modifier & 0x10) || (modifier & (0xff << 12))) + return modifier; + else + return modifier | (0xfe << 12); +} + +/* + * 16Bx2 Block Linear layout, used by Tegra K1 and later * * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked * vertically by a power of 2 (1 to 32 GOBs) to form a block. @@ -567,20 +817,20 @@ extern "C" { * in full detail. */ #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ - fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ - fourcc_mod_code(NVIDIA, 0x10) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ - fourcc_mod_code(NVIDIA, 0x11) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ - fourcc_mod_code(NVIDIA, 0x12) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ - fourcc_mod_code(NVIDIA, 0x13) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ - fourcc_mod_code(NVIDIA, 0x14) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ - fourcc_mod_code(NVIDIA, 0x15) + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) /* * Some Broadcom modifiers take parameters, for example the number of @@ -805,6 +1055,18 @@ extern "C" { */ #define AFBC_FORMAT_MOD_BCH (1ULL << 11) +/* AFBC uncompressed storage mode + * + * Indicates that the buffer is using AFBC uncompressed storage mode. + * In this mode all superblock payloads in the buffer use the uncompressed + * storage mode, which is usually only used for data which cannot be compressed. + * The buffer layout is the same as for AFBC buffers without USM set, this only + * affects the storage mode of the individual superblocks. Note that even a + * buffer without USM set may use uncompressed storage mode for some or all + * superblocks, USM just guarantees it for all. + */ +#define AFBC_FORMAT_MOD_USM (1ULL << 12) + /* * Arm 16x16 Block U-Interleaved modifier * @@ -829,6 +1091,220 @@ extern "C" { */ #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) +/* + * Amlogic Video Framebuffer Compression modifiers + * + * Amlogic uses a proprietary lossless image compression protocol and format + * for their hardware video codec accelerators, either video decoders or + * video input encoders. + * + * It considerably reduces memory bandwidth while writing and reading + * frames in memory. + * + * The underlying storage is considered to be 3 components, 8bit or 10-bit + * per component YCbCr 420, single plane : + * - DRM_FORMAT_YUV420_8BIT + * - DRM_FORMAT_YUV420_10BIT + * + * The first 8 bits of the mode defines the layout, then the following 8 bits + * defines the options changing the layout. + * + * Not all combinations are valid, and different SoCs may support different + * combinations of layout and options. + */ +#define __fourcc_mod_amlogic_layout_mask 0xf +#define __fourcc_mod_amlogic_options_shift 8 +#define __fourcc_mod_amlogic_options_mask 0xf + +#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ + fourcc_mod_code(AMLOGIC, \ + ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ + (((__options) & __fourcc_mod_amlogic_options_mask) \ + << __fourcc_mod_amlogic_options_shift)) + +/* Amlogic FBC Layouts */ + +/* + * Amlogic FBC Basic Layout + * + * The basic layout is composed of: + * - a body content organized in 64x32 superblocks with 4096 bytes per + * superblock in default mode. + * - a 32 bytes per 128x64 header block + * + * This layout is transferrable between Amlogic SoCs supporting this modifier. + */ +#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) + +/* + * Amlogic FBC Scatter Memory layout + * + * Indicates the header contains IOMMU references to the compressed + * frames content to optimize memory access and layout. + * + * In this mode, only the header memory address is needed, thus the + * content memory organization is tied to the current producer + * execution and cannot be saved/dumped neither transferrable between + * Amlogic SoCs supporting this modifier. + * + * Due to the nature of the layout, these buffers are not expected to + * be accessible by the user-space clients, but only accessible by the + * hardware producers and consumers. + * + * The user-space clients should expect a failure while trying to mmap + * the DMA-BUF handle returned by the producer. + */ +#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) + +/* Amlogic FBC Layout Options Bit Mask */ + +/* + * Amlogic FBC Memory Saving mode + * + * Indicates the storage is packed when pixel size is multiple of word + * boudaries, i.e. 8bit should be stored in this mode to save allocation + * memory. + * + * This mode reduces body layout to 3072 bytes per 64x32 superblock with + * the basic layout and 3200 bytes per 64x32 superblock combined with + * the scatter layout. + */ +#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) + +/* + * AMD modifiers + * + * Memory layout: + * + * without DCC: + * - main surface + * + * with DCC & without DCC_RETILE: + * - main surface in plane 0 + * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) + * + * with DCC & DCC_RETILE: + * - main surface in plane 0 + * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) + * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) + * + * For multi-plane formats the above surfaces get merged into one plane for + * each format plane, based on the required alignment only. + * + * Bits Parameter Notes + * ----- ------------------------ --------------------------------------------- + * + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* + * 12:8 TILE Values are AMD_FMT_MOD_TILE__* + * 13 DCC + * 14 DCC_RETILE + * 15 DCC_PIPE_ALIGN + * 16 DCC_INDEPENDENT_64B + * 17 DCC_INDEPENDENT_128B + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* + * 20 DCC_CONSTANT_ENCODE + * 23:21 PIPE_XOR_BITS Only for some chips + * 26:24 BANK_XOR_BITS Only for some chips + * 29:27 PACKERS Only for some chips + * 32:30 RB Only for some chips + * 35:33 PIPE Only for some chips + * 55:36 - Reserved for future use, must be zero + */ +#define AMD_FMT_MOD fourcc_mod_code(AMD, 0) + +#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) + +/* Reserve 0 for GFX8 and older */ +#define AMD_FMT_MOD_TILE_VER_GFX9 1 +#define AMD_FMT_MOD_TILE_VER_GFX10 2 +#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 + +/* + * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical + * version. + */ +#define AMD_FMT_MOD_TILE_GFX9_64K_S 9 + +/* + * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has + * GFX9 as canonical version. + */ +#define AMD_FMT_MOD_TILE_GFX9_64K_D 10 +#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 +#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 +#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 + +#define AMD_FMT_MOD_DCC_BLOCK_64B 0 +#define AMD_FMT_MOD_DCC_BLOCK_128B 1 +#define AMD_FMT_MOD_DCC_BLOCK_256B 2 + +#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 +#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF +#define AMD_FMT_MOD_TILE_SHIFT 8 +#define AMD_FMT_MOD_TILE_MASK 0x1F + +/* Whether DCC compression is enabled. */ +#define AMD_FMT_MOD_DCC_SHIFT 13 +#define AMD_FMT_MOD_DCC_MASK 0x1 + +/* + * Whether to include two DCC surfaces, one which is rb & pipe aligned, and + * one which is not-aligned. + */ +#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 +#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 + +/* Only set if DCC_RETILE = false */ +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 + +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 + +/* + * DCC supports embedding some clear colors directly in the DCC surface. + * However, on older GPUs the rendering HW ignores the embedded clear color + * and prefers the driver provided color. This necessitates doing a fastclear + * eliminate operation before a process transfers control. + * + * If this bit is set that means the fastclear eliminate is not needed for these + * embeddable colors. + */ +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 + +/* + * The below fields are for accounting for per GPU differences. These are only + * relevant for GFX9 and later and if the tile field is *_X/_T. + * + * PIPE_XOR_BITS = always needed + * BANK_XOR_BITS = only for TILE_VER_GFX9 + * PACKERS = only for TILE_VER_GFX10_RBPLUS + * RB = only for TILE_VER_GFX9 & DCC + * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) + */ +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 +#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 +#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 +#define AMD_FMT_MOD_PACKERS_SHIFT 27 +#define AMD_FMT_MOD_PACKERS_MASK 0x7 +#define AMD_FMT_MOD_RB_SHIFT 30 +#define AMD_FMT_MOD_RB_MASK 0x7 +#define AMD_FMT_MOD_PIPE_SHIFT 33 +#define AMD_FMT_MOD_PIPE_MASK 0x7 + +#define AMD_FMT_MOD_SET(field, value) \ + ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) +#define AMD_FMT_MOD_GET(field, value) \ + (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) +#define AMD_FMT_MOD_CLEAR(field) \ + (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) + #if defined(__cplusplus) } #endif diff --git a/third_party/uapi/xe_hp_sdv/drm/drm_mode.h b/third_party/uapi/prelim/drm/drm_mode.h similarity index 78% rename from third_party/uapi/xe_hp_sdv/drm/drm_mode.h rename to third_party/uapi/prelim/drm/drm_mode.h index 735c8cfdaa..0507188659 100644 --- a/third_party/uapi/xe_hp_sdv/drm/drm_mode.h +++ b/third_party/uapi/prelim/drm/drm_mode.h @@ -218,6 +218,27 @@ extern "C" { #define DRM_MODE_CONTENT_PROTECTION_DESIRED 1 #define DRM_MODE_CONTENT_PROTECTION_ENABLED 2 +/** + * struct drm_mode_modeinfo - Display mode information. + * @clock: pixel clock in kHz + * @hdisplay: horizontal display size + * @hsync_start: horizontal sync start + * @hsync_end: horizontal sync end + * @htotal: horizontal total size + * @hskew: horizontal skew + * @vdisplay: vertical display size + * @vsync_start: vertical sync start + * @vsync_end: vertical sync end + * @vtotal: vertical total size + * @vscan: vertical scan + * @vrefresh: approximate vertical refresh rate in Hz + * @flags: bitmask of misc. flags, see DRM_MODE_FLAG_* defines + * @type: bitmask of type flags, see DRM_MODE_TYPE_* defines + * @name: string describing the mode resolution + * + * This is the user-space API display mode information structure. For the + * kernel version see struct drm_display_mode. + */ struct drm_mode_modeinfo { __u32 clock; __u16 hdisplay; @@ -332,14 +353,19 @@ struct drm_mode_get_encoder { /* This is for connectors with multiple signal types. */ /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ enum drm_mode_subconnector { - DRM_MODE_SUBCONNECTOR_Automatic = 0, - DRM_MODE_SUBCONNECTOR_Unknown = 0, - DRM_MODE_SUBCONNECTOR_DVID = 3, - DRM_MODE_SUBCONNECTOR_DVIA = 4, - DRM_MODE_SUBCONNECTOR_Composite = 5, - DRM_MODE_SUBCONNECTOR_SVIDEO = 6, - DRM_MODE_SUBCONNECTOR_Component = 8, - DRM_MODE_SUBCONNECTOR_SCART = 9, + DRM_MODE_SUBCONNECTOR_Automatic = 0, /* DVI-I, TV */ + DRM_MODE_SUBCONNECTOR_Unknown = 0, /* DVI-I, TV, DP */ + DRM_MODE_SUBCONNECTOR_VGA = 1, /* DP */ + DRM_MODE_SUBCONNECTOR_DVID = 3, /* DVI-I DP */ + DRM_MODE_SUBCONNECTOR_DVIA = 4, /* DVI-I */ + DRM_MODE_SUBCONNECTOR_Composite = 5, /* TV */ + DRM_MODE_SUBCONNECTOR_SVIDEO = 6, /* TV */ + DRM_MODE_SUBCONNECTOR_Component = 8, /* TV */ + DRM_MODE_SUBCONNECTOR_SCART = 9, /* TV */ + DRM_MODE_SUBCONNECTOR_DisplayPort = 10, /* DP */ + DRM_MODE_SUBCONNECTOR_HDMIA = 11, /* DP */ + DRM_MODE_SUBCONNECTOR_Native = 15, /* DP */ + DRM_MODE_SUBCONNECTOR_Wireless = 18, /* DP */ }; #define DRM_MODE_CONNECTOR_Unknown 0 @@ -363,27 +389,92 @@ enum drm_mode_subconnector { #define DRM_MODE_CONNECTOR_WRITEBACK 18 #define DRM_MODE_CONNECTOR_SPI 19 +/** + * struct drm_mode_get_connector - Get connector metadata. + * + * User-space can perform a GETCONNECTOR ioctl to retrieve information about a + * connector. User-space is expected to retrieve encoders, modes and properties + * by performing this ioctl at least twice: the first time to retrieve the + * number of elements, the second time to retrieve the elements themselves. + * + * To retrieve the number of elements, set @count_props and @count_encoders to + * zero, set @count_modes to 1, and set @modes_ptr to a temporary struct + * drm_mode_modeinfo element. + * + * To retrieve the elements, allocate arrays for @encoders_ptr, @modes_ptr, + * @props_ptr and @prop_values_ptr, then set @count_modes, @count_props and + * @count_encoders to their capacity. + * + * Performing the ioctl only twice may be racy: the number of elements may have + * changed with a hotplug event in-between the two ioctls. User-space is + * expected to retry the last ioctl until the number of elements stabilizes. + * The kernel won't fill any array which doesn't have the expected length. + * + * **Force-probing a connector** + * + * If the @count_modes field is set to zero, the kernel will perform a forced + * probe on the connector to refresh the connector status, modes and EDID. + * A forced-probe can be slow, might cause flickering and the ioctl will block. + * + * User-space needs to force-probe connectors to ensure their metadata is + * up-to-date at startup and after receiving a hot-plug event. User-space + * may perform a forced-probe when the user explicitly requests it. User-space + * shouldn't perform a forced-probe in other situations. + */ struct drm_mode_get_connector { - + /** @encoders_ptr: Pointer to ``__u32`` array of object IDs. */ __u64 encoders_ptr; + /** @modes_ptr: Pointer to struct drm_mode_modeinfo array. */ __u64 modes_ptr; + /** @props_ptr: Pointer to ``__u32`` array of property IDs. */ __u64 props_ptr; + /** @prop_values_ptr: Pointer to ``__u64`` array of property values. */ __u64 prop_values_ptr; + /** @count_modes: Number of modes. */ __u32 count_modes; + /** @count_props: Number of properties. */ __u32 count_props; + /** @count_encoders: Number of encoders. */ __u32 count_encoders; - __u32 encoder_id; /**< Current Encoder */ - __u32 connector_id; /**< Id */ + /** @encoder_id: Object ID of the current encoder. */ + __u32 encoder_id; + /** @connector_id: Object ID of the connector. */ + __u32 connector_id; + /** + * @connector_type: Type of the connector. + * + * See DRM_MODE_CONNECTOR_* defines. + */ __u32 connector_type; + /** + * @connector_type_id: Type-specific connector number. + * + * This is not an object ID. This is a per-type connector number. Each + * (type, type_id) combination is unique across all connectors of a DRM + * device. + */ __u32 connector_type_id; + /** + * @connection: Status of the connector. + * + * See enum drm_connector_status. + */ __u32 connection; - __u32 mm_width; /**< width in millimeters */ - __u32 mm_height; /**< height in millimeters */ + /** @mm_width: Width of the connected sink in millimeters. */ + __u32 mm_width; + /** @mm_height: Height of the connected sink in millimeters. */ + __u32 mm_height; + /** + * @subpixel: Subpixel order of the connected sink. + * + * See enum subpixel_order. + */ __u32 subpixel; + /** @pad: Padding, must be zero. */ __u32 pad; }; @@ -497,7 +588,7 @@ struct drm_mode_fb_cmd2 { * In case of planar formats, this ioctl allows up to 4 * buffer objects with offsets and pitches per plane. * The pitch and offset order is dictated by the fourcc, - * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: + * e.g. NV12 (https://fourcc.org/yuv.php#NV12) is described as: * * YUV 4:2:0 image with a plane of 8 bit Y samples * followed by an interleaved U/V plane containing @@ -726,6 +817,64 @@ struct hdr_output_metadata { }; }; +/* + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means the LUT + * can be used for either purpose, but not simultaneously. To expose + * modes that support gamma and degamma simultaneously the gamma mode + * must declare distinct DRM_MODE_LUT_GAMMA and DRM_MODE_LUT_DEGAMMA + * ranges. + */ +/* LUT is for gamma (after CTM) */ +#define DRM_MODE_LUT_GAMMA BIT(0) +/* LUT is for degamma (before CTM) */ +#define DRM_MODE_LUT_DEGAMMA BIT(1) +/* linearly interpolate between the points */ +#define DRM_MODE_LUT_INTERPOLATE BIT(2) +/* + * the last value of the previous range is the + * first value of the current range. + */ +#define DRM_MODE_LUT_REUSE_LAST BIT(3) +/* the curve must be non-decreasing */ +#define DRM_MODE_LUT_NON_DECREASING BIT(4) +/* the curve is reflected across origin for negative inputs */ +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5) +/* the same curve (red) is used for blue and green channels as well */ +#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6) + +struct drm_color_lut_range { + /* DRM_MODE_LUT_* */ + __u32 flags; + /* number of points on the curve */ + __u16 count; + /* input/output bits per component */ + __u8 input_bpc, output_bpc; + /* input start/end values */ + __s32 start, end; + /* output min/max values */ + __s32 min, max; +}; + +enum lut_type { + LUT_TYPE_DEGAMMA = 0, + LUT_TYPE_GAMMA = 1, +}; + +/* + * Creating 64 bit palette entries for better data + * precision. This will be required for HDR and + * similar color processing usecases. + */ +struct drm_color_lut_ext { + /* + * Data is U32.32 fixed point format. + */ + __u64 red; + __u64 green; + __u64 blue; + __u64 reserved; +}; + #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 @@ -900,25 +1049,30 @@ struct drm_format_modifier { /** * struct drm_mode_create_blob - Create New block property - * @data: Pointer to data to copy. - * @length: Length of data to copy. - * @blob_id: new property ID. + * * Create a new 'blob' data property, copying length bytes from data pointer, * and returning new blob ID. */ struct drm_mode_create_blob { - /** Pointer to data to copy. */ + /** @data: Pointer to data to copy. */ __u64 data; - /** Length of data to copy. */ + /** @length: Length of data to copy. */ __u32 length; - /** Return: new property ID. */ + /** @blob_id: Return: new property ID. */ __u32 blob_id; }; /** * struct drm_mode_destroy_blob - Destroy user blob * @blob_id: blob_id to destroy + * * Destroy a user-created blob property. + * + * User-space can release blobs as soon as they do not need to refer to them by + * their blob object ID. For instance, if you are using a MODE_ID blob in an + * atomic commit and you will not make another commit re-using the same ID, you + * can destroy the blob as soon as the commit has been issued, without waiting + * for it to complete. */ struct drm_mode_destroy_blob { __u32 blob_id; @@ -926,36 +1080,36 @@ struct drm_mode_destroy_blob { /** * struct drm_mode_create_lease - Create lease - * @object_ids: Pointer to array of object ids. - * @object_count: Number of object ids. - * @flags: flags for new FD. - * @lessee_id: unique identifier for lessee. - * @fd: file descriptor to new drm_master file. + * * Lease mode resources, creating another drm_master. + * + * The @object_ids array must reference at least one CRTC, one connector and + * one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled. Alternatively, + * the lease can be completely empty. */ struct drm_mode_create_lease { - /** Pointer to array of object ids (__u32) */ + /** @object_ids: Pointer to array of object ids (__u32) */ __u64 object_ids; - /** Number of object ids */ + /** @object_count: Number of object ids */ __u32 object_count; - /** flags for new FD (O_CLOEXEC, etc) */ + /** @flags: flags for new FD (O_CLOEXEC, etc) */ __u32 flags; - /** Return: unique identifier for lessee. */ + /** @lessee_id: Return: unique identifier for lessee. */ __u32 lessee_id; - /** Return: file descriptor to new drm_master file */ + /** @fd: Return: file descriptor to new drm_master file */ __u32 fd; }; /** * struct drm_mode_list_lessees - List lessees - * @count_lessees: Number of lessees. - * @pad: pad. - * @lessees_ptr: Pointer to lessess. - * List lesses from a drm_master + * + * List lesses from a drm_master. */ struct drm_mode_list_lessees { - /** Number of lessees. + /** + * @count_lessees: Number of lessees. + * * On input, provides length of the array. * On output, provides total number. No * more than the input number will be written @@ -963,23 +1117,26 @@ struct drm_mode_list_lessees { * the size and then the data. */ __u32 count_lessees; + /** @pad: Padding. */ __u32 pad; - /** Pointer to lessees. - * pointer to __u64 array of lessee ids + /** + * @lessees_ptr: Pointer to lessees. + * + * Pointer to __u64 array of lessee ids */ __u64 lessees_ptr; }; /** * struct drm_mode_get_lease - Get Lease - * @count_objects: Number of leased objects. - * @pad: pad. - * @objects_ptr: Pointer to objects. - * Get leased objects + * + * Get leased objects. */ struct drm_mode_get_lease { - /** Number of leased objects. + /** + * @count_objects: Number of leased objects. + * * On input, provides length of the array. * On output, provides total number. No * more than the input number will be written @@ -987,22 +1144,22 @@ struct drm_mode_get_lease { * the size and then the data. */ __u32 count_objects; + /** @pad: Padding. */ __u32 pad; - /** Pointer to objects. - * pointer to __u32 array of object ids + /** + * @objects_ptr: Pointer to objects. + * + * Pointer to __u32 array of object ids. */ __u64 objects_ptr; }; /** * struct drm_mode_revoke_lease - Revoke lease - * @lessee_id: Unique ID of lessee. - * Revoke lease */ struct drm_mode_revoke_lease { - /** Unique ID of lessee - */ + /** @lessee_id: Unique ID of lessee */ __u32 lessee_id; }; diff --git a/third_party/uapi/xe_hp_sdv/drm/i915_drm.h b/third_party/uapi/prelim/drm/i915_drm.h similarity index 75% rename from third_party/uapi/xe_hp_sdv/drm/i915_drm.h rename to third_party/uapi/prelim/drm/i915_drm.h index 467fcd6b84..179cc4f90e 100644 --- a/third_party/uapi/xe_hp_sdv/drm/i915_drm.h +++ b/third_party/uapi/prelim/drm/i915_drm.h @@ -24,16 +24,20 @@ * */ -#ifndef _UAPI_I915_DRM_H_ -#define _UAPI_I915_DRM_H_ +#ifndef _I915_DRM_H_ +#define _I915_DRM_H_ -#define __user #include "drm.h" #if defined(__cplusplus) extern "C" { #endif +/* + * Internal/downstream declarations should be added to i915_drm_prelim.h, + * not here in i915_drm.h. + */ + /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints. */ @@ -76,7 +80,7 @@ extern "C" { * redefine the interface more easily than an ever growing struct of * increasing complexity, and for large parts of that interface to be * entirely optional. The downside is more pointer chasing; chasing across - * the __user boundary with pointers encapsulated inside u64. + * the boundary with pointers encapsulated inside u64. * * Example chaining: * @@ -155,22 +159,71 @@ enum i915_mocs_table_index { I915_MOCS_CACHED, }; -/* +/** + * enum drm_i915_gem_engine_class - uapi engine type enumeration + * * Different engines serve different roles, and there may be more than one - * engine serving each role. enum drm_i915_gem_engine_class provides a - * classification of the role of the engine, which may be used when requesting - * operations to be performed on a certain subset of engines, or for providing - * information about that group. + * engine serving each role. This enum provides a classification of the role + * of the engine, which may be used when requesting operations to be performed + * on a certain subset of engines, or for providing information about that + * group. */ enum drm_i915_gem_engine_class { + /** + * @I915_ENGINE_CLASS_RENDER: + * + * Render engines support instructions used for 3D, Compute (GPGPU), + * and programmable media workloads. These instructions fetch data and + * dispatch individual work items to threads that operate in parallel. + * The threads run small programs (called "kernels" or "shaders") on + * the GPU's execution units (EUs). + */ I915_ENGINE_CLASS_RENDER = 0, + + /** + * @I915_ENGINE_CLASS_COPY: + * + * Copy engines (also referred to as "blitters") support instructions + * that move blocks of data from one location in memory to another, + * or that fill a specified location of memory with fixed data. + * Copy engines can perform pre-defined logical or bitwise operations + * on the source, destination, or pattern data. + */ I915_ENGINE_CLASS_COPY = 1, + + /** + * @I915_ENGINE_CLASS_VIDEO: + * + * Video engines (also referred to as "bit stream decode" (BSD) or + * "vdbox") support instructions that perform fixed-function media + * decode and encode. + */ I915_ENGINE_CLASS_VIDEO = 2, + + /** + * @I915_ENGINE_CLASS_VIDEO_ENHANCE: + * + * Video enhancement engines (also referred to as "vebox") support + * instructions related to image enhancement. + */ I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, + + /** + * @I915_ENGINE_CLASS_COMPUTE: + * + * Compute engines support a subset of the instructions available + * on render engines: compute engines support Compute (GPGPU) and + * programmable media workloads, but do not support the 3D pipeline. + */ I915_ENGINE_CLASS_COMPUTE = 4, - /* should be kept compact */ + /* Values in this enum should be kept compact. */ + /** + * @I915_ENGINE_CLASS_INVALID: + * + * Placeholder value to represent an invalid engine class assignment. + */ I915_ENGINE_CLASS_INVALID = -1 }; @@ -219,13 +272,11 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_ENGINE_SEMA(class, instance) \ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) -#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) - -#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) -#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) -#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) -#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) -#define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4) +#define I915_PMU_ACTUAL_FREQUENCY __PRELIM_I915_PMU_ACTUAL_FREQUENCY(0) +#define I915_PMU_REQUESTED_FREQUENCY __PRELIM_I915_PMU_REQUESTED_FREQUENCY(0) +#define I915_PMU_INTERRUPTS __PRELIM_I915_PMU_INTERRUPTS(0) +#define I915_PMU_RC6_RESIDENCY __PRELIM_I915_PMU_RC6_RESIDENCY(0) +#define I915_PMU_SOFTWARE_GT_AWAKE_TIME __PRELIM_I915_PMU_SOFTWARE_GT_AWAKE_TIME(0) #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY @@ -408,7 +459,6 @@ typedef struct _drm_i915_sarea { #define DRM_I915_QUERY 0x39 #define DRM_I915_GEM_VM_CREATE 0x3a #define DRM_I915_GEM_VM_DESTROY 0x3b -#define DRM_I915_GEM_CREATE_EXT 0x3c /* Must be kept compact -- no holes */ #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) @@ -441,7 +491,6 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) -#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext) #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) @@ -483,25 +532,25 @@ typedef struct drm_i915_batchbuffer { int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ + struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ } drm_i915_batchbuffer_t; /* As above, but pass a pointer to userspace buffer which can be * validated by the kernel prior to sending to hardware. */ typedef struct _drm_i915_cmdbuffer { - char __user *buf; /* pointer to userspace command buffer */ + char *buf; /* pointer to userspace command buffer */ int sz; /* nr bytes in buf */ int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ + struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ } drm_i915_cmdbuffer_t; /* Userspace can request & wait on irq's: */ typedef struct drm_i915_irq_emit { - int __user *irq_seq; + int *irq_seq; } drm_i915_irq_emit_t; typedef struct drm_i915_irq_wait { @@ -574,15 +623,6 @@ typedef struct drm_i915_irq_wait { #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) -/* - * Indicates the 2k user priority levels are statically mapped into 3 buckets as - * follows: - * - * -1k to -1 Low priority - * 0 Normal priority - * 1 to 1k Highest priority - */ -#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5) #define I915_PARAM_HUC_STATUS 42 @@ -685,9 +725,6 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55 -/* Query if the kernel supports the I915_USERPTR_PROBE flag. */ -#define I915_PARAM_HAS_USERPTR_PROBE 56 - /* Must be kept compact -- no holes and well documented */ typedef struct drm_i915_getparam { @@ -696,7 +733,7 @@ typedef struct drm_i915_getparam { * WARNING: Using pointers instead of fixed-size u64 means we need to write * compat32 code. Don't repeat this mistake. */ - int __user *value; + int *value; } drm_i915_getparam_t; /* Ioctl to set kernel params: @@ -720,7 +757,7 @@ typedef struct drm_i915_mem_alloc { int region; int alignment; int size; - int __user *region_offset; /* offset from start of fb or agp */ + int *region_offset; /* offset from start of fb or agp */ } drm_i915_mem_alloc_t; typedef struct drm_i915_mem_free { @@ -863,113 +900,45 @@ struct drm_i915_gem_mmap_gtt { __u64 offset; }; -/** - * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object. - * - * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl, - * and is used to retrieve the fake offset to mmap an object specified by &handle. - * - * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+. - * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave - * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`. - */ struct drm_i915_gem_mmap_offset { - /** @handle: Handle for the object being mapped. */ + /** Handle for the object being mapped. */ __u32 handle; - /** @pad: Must be zero */ __u32 pad; /** - * @offset: The fake offset to use for subsequent mmap call + * Fake offset to use for subsequent mmap call * * This is a fixed-size type for 32/64 compatibility. */ __u64 offset; /** - * @flags: Flags for extended behaviour. + * Flags for extended behaviour. * - * It is mandatory that one of the `MMAP_OFFSET` types - * should be included: - * - * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) - * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. - * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. - * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. - * - * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid - * type. On devices without local memory, this caching mode is invalid. - * - * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will - * be used, depending on the object placement on creation. WB will be used - * when the object can only exist in system memory, WC otherwise. + * It is mandatory that one of the MMAP_OFFSET types + * (GTT, WC, WB, UC, etc) should be included. */ __u64 flags; +#define I915_MMAP_OFFSET_GTT 0 +#define I915_MMAP_OFFSET_WC 1 +#define I915_MMAP_OFFSET_WB 2 +#define I915_MMAP_OFFSET_UC 3 -#define I915_MMAP_OFFSET_GTT 0 -#define I915_MMAP_OFFSET_WC 1 -#define I915_MMAP_OFFSET_WB 2 -#define I915_MMAP_OFFSET_UC 3 -#define I915_MMAP_OFFSET_FIXED 4 - - /** - * @extensions: Zero-terminated chain of extensions. + /* + * Zero-terminated chain of extensions. * * No current extensions defined; mbz. */ __u64 extensions; }; -/** - * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in - * preparation for accessing the pages via some CPU domain. - * - * Specifying a new write or read domain will flush the object out of the - * previous domain(if required), before then updating the objects domain - * tracking with the new domain. - * - * Note this might involve waiting for the object first if it is still active on - * the GPU. - * - * Supported values for @read_domains and @write_domain: - * - * - I915_GEM_DOMAIN_WC: Uncached write-combined domain - * - I915_GEM_DOMAIN_CPU: CPU cache domain - * - I915_GEM_DOMAIN_GTT: Mappable aperture domain - * - * All other domains are rejected. - * - * Note that for discrete, starting from DG1, this is no longer supported, and - * is instead rejected. On such platforms the CPU domain is effectively static, - * where we also only support a single &drm_i915_gem_mmap_offset cache mode, - * which can't be set explicitly and instead depends on the object placements, - * as per the below. - * - * Implicit caching rules, starting from DG1: - * - * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) - * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and - * mapped as write-combined only. - * - * - Everything else is always allocated and mapped as write-back, with the - * guarantee that everything is also coherent with the GPU. - * - * Note that this is likely to change in the future again, where we might need - * more flexibility on future devices, so making this all explicit as part of a - * new &drm_i915_gem_create_ext extension is probable. - */ struct drm_i915_gem_set_domain { - /** @handle: Handle for the object. */ + /** Handle for the object */ __u32 handle; - /** @read_domains: New read domains. */ + /** New read domains */ __u32 read_domains; - /** - * @write_domain: New write domain. - * - * Note that having something in the write domain implies it's in the - * read domain, and only that read domain. - */ + /** New write domain */ __u32 write_domain; }; @@ -1242,7 +1211,8 @@ struct drm_i915_gem_execbuffer2 { * single struct i915_user_extension and num_cliprects is 0. */ __u64 cliprects_ptr; -#define I915_EXEC_RING_MASK (0x3f) + +#define I915_EXEC_RING_MASK (0x3f) /* legacy for small systems */ #define I915_EXEC_DEFAULT (0<<0) #define I915_EXEC_RENDER (1<<0) #define I915_EXEC_BSD (2<<0) @@ -1430,11 +1400,12 @@ struct drm_i915_gem_busy { * reading from the object simultaneously. * * The value of each engine class is the same as specified in the - * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e. + * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e. * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc. - * Some hardware may have parallel execution engines, e.g. multiple - * media engines, which are mapped to the same class identifier and so - * are not separately reported for busyness. + * reported as active itself. Some hardware may have parallel + * execution engines, e.g. multiple media engines, which are + * mapped to the same class identifier and so are not separately + * reported for busyness. * * Caveat emptor: * Only the boolean result of this query is reliable; that is whether @@ -1445,85 +1416,55 @@ struct drm_i915_gem_busy { }; /** - * struct drm_i915_gem_caching - Set or get the caching for given object - * handle. + * I915_CACHING_NONE * - * Allow userspace to control the GTT caching bits for a given object when the - * object is later mapped through the ppGTT(or GGTT on older platforms lacking - * ppGTT support, or if the object is used for scanout). Note that this might - * require unbinding the object from the GTT first, if its current caching value - * doesn't match. - * - * Note that this all changes on discrete platforms, starting from DG1, the - * set/get caching is no longer supported, and is now rejected. Instead the CPU - * caching attributes(WB vs WC) will become an immutable creation time property - * for the object, along with the GTT caching level. For now we don't expose any - * new uAPI for this, instead on DG1 this is all implicit, although this largely - * shouldn't matter since DG1 is coherent by default(without any way of - * controlling it). - * - * Implicit caching rules, starting from DG1: - * - * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) - * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and - * mapped as write-combined only. - * - * - Everything else is always allocated and mapped as write-back, with the - * guarantee that everything is also coherent with the GPU. - * - * Note that this is likely to change in the future again, where we might need - * more flexibility on future devices, so making this all explicit as part of a - * new &drm_i915_gem_create_ext extension is probable. - * - * Side note: Part of the reason for this is that changing the at-allocation-time CPU - * caching attributes for the pages might be required(and is expensive) if we - * need to then CPU map the pages later with different caching attributes. This - * inconsistent caching behaviour, while supported on x86, is not universally - * supported on other architectures. So for simplicity we opt for setting - * everything at creation time, whilst also making it immutable, on discrete - * platforms. + * GPU access is not coherent with cpu caches. Default for machines without an + * LLC. */ +#define I915_CACHING_NONE 0 +/** + * I915_CACHING_CACHED + * + * GPU access is coherent with cpu caches and furthermore the data is cached in + * last-level caches shared between cpu cores and the gpu GT. Default on + * machines with HAS_LLC. + */ +#define I915_CACHING_CACHED 1 +/** + * I915_CACHING_DISPLAY + * + * Special GPU caching mode which is coherent with the scanout engines. + * Transparently falls back to I915_CACHING_NONE on platforms where no special + * cache mode (like write-through or gfdt flushing) is available. The kernel + * automatically sets this mode when using a buffer as a scanout target. + * Userspace can manually set this mode to avoid a costly stall and clflush in + * the hotpath of drawing the first frame. + */ +#define I915_CACHING_DISPLAY 2 + struct drm_i915_gem_caching { /** - * @handle: Handle of the buffer to set/get the caching level. - */ + * Handle of the buffer to set/get the caching level of. */ __u32 handle; /** - * @caching: The GTT caching level to apply or possible return value. + * Cacheing level to apply or return value * - * The supported @caching values: - * - * I915_CACHING_NONE: - * - * GPU access is not coherent with CPU caches. Default for machines - * without an LLC. This means manual flushing might be needed, if we - * want GPU access to be coherent. - * - * I915_CACHING_CACHED: - * - * GPU access is coherent with CPU caches and furthermore the data is - * cached in last-level caches shared between CPU cores and the GPU GT. - * - * I915_CACHING_DISPLAY: - * - * Special GPU caching mode which is coherent with the scanout engines. - * Transparently falls back to I915_CACHING_NONE on platforms where no - * special cache mode (like write-through or gfdt flushing) is - * available. The kernel automatically sets this mode when using a - * buffer as a scanout target. Userspace can manually set this mode to - * avoid a costly stall and clflush in the hotpath of drawing the first - * frame. - */ -#define I915_CACHING_NONE 0 -#define I915_CACHING_CACHED 1 -#define I915_CACHING_DISPLAY 2 + * bits0-15 are for generic caching control (i.e. the above defined + * values). bits16-31 are reserved for platform-specific variations + * (e.g. l3$ caching on gen7). */ __u32 caching; }; #define I915_TILING_NONE 0 #define I915_TILING_X 1 #define I915_TILING_Y 2 +/* + * Do not add new tiling types here. The I915_TILING_* values are for + * de-tiling fence registers that no longer exist on modern platforms. Although + * the hardware may support new types of tiling in general (e.g., Tile4), we + * do not need to add them to the uapi that is specific to now-defunct ioctls. + */ #define I915_TILING_LAST I915_TILING_Y #define I915_BIT_6_SWIZZLE_NONE 0 @@ -1756,10 +1697,6 @@ struct drm_i915_gem_context_param { __u32 size; __u64 param; #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 -/* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance - * someone somewhere has attempted to use it, never re-use this context - * param number. - */ #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 @@ -1826,6 +1763,7 @@ struct drm_i915_gem_context_param { * Extensions: * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE) * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND) + * prelim_i915_context_engines_parallel_submit (PRELIM_I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT) */ #define I915_CONTEXT_PARAM_ENGINES 0xa @@ -1844,8 +1782,24 @@ struct drm_i915_gem_context_param { */ #define I915_CONTEXT_PARAM_PERSISTENCE 0xb -/* This API has been removed. On the off chance someone somewhere has - * attempted to use it, never re-use this context param number. +/* + * I915_CONTEXT_PARAM_RINGSIZE: + * + * Sets the size of the CS ringbuffer to use for logical ring contexts. This + * applies a limit of how many batches can be queued to HW before the caller + * is blocked due to lack of space for more commands. + * + * Only reliably possible to be set prior to first use, i.e. during + * construction. At any later point, the current execution must be flushed as + * the ring can only be changed while the context is idle. Note, the ringsize + * can be specified as a constructor property, see + * I915_CONTEXT_CREATE_EXT_SETPARAM, but can also be set later if required. + * + * Only applies to the current set of engine and lost when those engines + * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES). + * + * Must be between 4 - 512 KiB, in intervals of page size [4 KiB]. + * Default is 16 KiB. */ #define I915_CONTEXT_PARAM_RINGSIZE 0xc /* Must be kept compact -- no holes and well documented */ @@ -1912,69 +1866,6 @@ struct drm_i915_gem_context_param_sseu { __u32 rsvd; }; -/** - * DOC: Virtual Engine uAPI - * - * Virtual engine is a concept where userspace is able to configure a set of - * physical engines, submit a batch buffer, and let the driver execute it on any - * engine from the set as it sees fit. - * - * This is primarily useful on parts which have multiple instances of a same - * class engine, like for example GT3+ Skylake parts with their two VCS engines. - * - * For instance userspace can enumerate all engines of a certain class using the - * previously described `Engine Discovery uAPI`_. After that userspace can - * create a GEM context with a placeholder slot for the virtual engine (using - * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class - * and instance respectively) and finally using the - * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in - * the same reserved slot. - * - * Example of creating a virtual engine and submitting a batch buffer to it: - * - * .. code-block:: C - * - * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { - * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, - * .engine_index = 0, // Place this virtual engine into engine map slot 0 - * .num_siblings = 2, - * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, - * { I915_ENGINE_CLASS_VIDEO, 1 }, }, - * }; - * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { - * .engines = { { I915_ENGINE_CLASS_INVALID, - * I915_ENGINE_CLASS_INVALID_NONE } }, - * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension - * }; - * struct drm_i915_gem_context_create_ext_setparam p_engines = { - * .base = { - * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, - * }, - * .param = { - * .param = I915_CONTEXT_PARAM_ENGINES, - * .value = to_user_pointer(&engines), - * .size = sizeof(engines), - * }, - * }; - * struct drm_i915_gem_context_create_ext create = { - * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, - * .extensions = to_user_pointer(&p_engines); - * }; - * - * ctx_id = gem_context_create_ext(drm_fd, &create); - * - * // Now we have created a GEM context with its engine map containing a - * // single virtual engine. Submissions to this slot can go either to - * // vcs0 or vcs1, depending on the load balancing algorithm used inside - * // the driver. The load balancing is dynamic from one batch buffer to - * // another and transparent to userspace. - * - * ... - * execbuf.rsvd1 = ctx_id; - * execbuf.flags = 0; // Submits to index 0 which is the virtual engine - * gem_execbuf(drm_fd, &execbuf); - */ - /* * i915_context_engines_load_balance: * @@ -2051,61 +1942,6 @@ struct i915_context_engines_bond { struct i915_engine_class_instance engines[N__]; \ } __attribute__((packed)) name__ -/** - * DOC: Context Engine Map uAPI - * - * Context engine map is a new way of addressing engines when submitting batch- - * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` - * inside the flags field of `struct drm_i915_gem_execbuffer2`. - * - * To use it created GEM contexts need to be configured with a list of engines - * the user is intending to submit to. This is accomplished using the - * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct - * i915_context_param_engines`. - * - * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the - * configured map. - * - * Example of creating such context and submitting against it: - * - * .. code-block:: C - * - * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { - * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, - * { I915_ENGINE_CLASS_COPY, 0 } } - * }; - * struct drm_i915_gem_context_create_ext_setparam p_engines = { - * .base = { - * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, - * }, - * .param = { - * .param = I915_CONTEXT_PARAM_ENGINES, - * .value = to_user_pointer(&engines), - * .size = sizeof(engines), - * }, - * }; - * struct drm_i915_gem_context_create_ext create = { - * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, - * .extensions = to_user_pointer(&p_engines); - * }; - * - * ctx_id = gem_context_create_ext(drm_fd, &create); - * - * // We have now created a GEM context with two engines in the map: - * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines - * // will not be accessible from this context. - * - * ... - * execbuf.rsvd1 = ctx_id; - * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context - * gem_execbuf(drm_fd, &execbuf); - * - * ... - * execbuf.rsvd1 = ctx_id; - * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context - * gem_execbuf(drm_fd, &execbuf); - */ - struct i915_context_param_engines { __u64 extensions; /* linked chain of extension blocks, 0 terminates */ #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ @@ -2124,11 +1960,6 @@ struct drm_i915_gem_context_create_ext_setparam { struct drm_i915_gem_context_param param; }; -/* This API has been removed. On the off chance someone somewhere has - * attempted to use it, never re-use this extension number. - */ -#define I915_CONTEXT_CREATE_EXT_CLONE 1 - struct drm_i915_gem_context_destroy { __u32 ctx_id; __u32 pad; @@ -2147,7 +1978,7 @@ struct drm_i915_gem_context_destroy { * No flags are defined, with all bits reserved and must be zero. * * An extension chain maybe provided, starting with @extensions, and terminated - * by the @next_extension being 0. Currently, no extensions are defined. + * by the @next_extension being 0. Currently, mem region extension is defined. * * DRM_I915_GEM_VM_DESTROY - * @@ -2186,6 +2017,12 @@ struct drm_i915_reg_read { struct drm_i915_reset_stats { __u32 ctx_id; __u32 flags; + /* + * contexts marked as using protected content are invalidated when the + * protected content session dies. Submission of invalidated contexts + * is rejected with -EACCES. + */ +#define I915_CONTEXT_INVALIDATED 0x1 /* All resets since boot/module reload, for all contexts */ __u32 reset_count; @@ -2199,69 +2036,14 @@ struct drm_i915_reset_stats { __u32 pad; }; -/** - * struct drm_i915_gem_userptr - Create GEM object from user allocated memory. - * - * Userptr objects have several restrictions on what ioctls can be used with the - * object handle. - */ struct drm_i915_gem_userptr { - /** - * @user_ptr: The pointer to the allocated memory. - * - * Needs to be aligned to PAGE_SIZE. - */ __u64 user_ptr; - - /** - * @user_size: - * - * The size in bytes for the allocated memory. This will also become the - * object size. - * - * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, - * or larger. - */ __u64 user_size; - - /** - * @flags: - * - * Supported flags: - * - * I915_USERPTR_READ_ONLY: - * - * Mark the object as readonly, this also means GPU access can only be - * readonly. This is only supported on HW which supports readonly access - * through the GTT. If the HW can't support readonly access, an error is - * returned. - * - * I915_USERPTR_PROBE: - * - * Probe the provided @user_ptr range and validate that the @user_ptr is - * indeed pointing to normal memory and that the range is also valid. - * For example if some garbage address is given to the kernel, then this - * should complain. - * - * Returns -EFAULT if the probe failed. - * - * Note that this doesn't populate the backing pages, and also doesn't - * guarantee that the object will remain valid when the object is - * eventually used. - * - * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE - * returns a non-zero value. - * - * I915_USERPTR_UNSYNCHRONIZED: - * - * NOT USED. Setting this flag will result in an error. - */ __u32 flags; #define I915_USERPTR_READ_ONLY 0x1 -#define I915_USERPTR_PROBE 0x2 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 /** - * @handle: Returned handle for the object. + * Returned handle for the object. * * Object handles are nonzero. */ @@ -2410,7 +2192,7 @@ struct drm_i915_perf_open_param { * Change metrics_set captured by a stream. * * If the stream is bound to a specific context, the configuration change - * will performed inline with that context such that it takes effect before + * will performed __inline__ with that context such that it takes effect before * the next execbuf submission. * * Returns the previously bound metrics set id, or a negative error code. @@ -2500,8 +2282,6 @@ struct drm_i915_query_item { #define DRM_I915_QUERY_TOPOLOGY_INFO 1 #define DRM_I915_QUERY_ENGINE_INFO 2 #define DRM_I915_QUERY_PERF_CONFIG 3 -#define DRM_I915_QUERY_MEMORY_REGIONS 4 -#define DRM_I915_QUERY_HWCONFIG_TABLE 5 /* Must be kept compact -- no holes and well documented */ /** @@ -2517,14 +2297,13 @@ struct drm_i915_query_item { /** * @flags: * - * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0. - * * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the - * following: + * following : + * - DRM_I915_QUERY_PERF_CONFIG_LIST + * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID + * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID * - * - DRM_I915_QUERY_PERF_CONFIG_LIST - * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID - * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID + * For all other query_id values, flags must be 0. */ __u32 flags; #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 @@ -2645,80 +2424,12 @@ struct drm_i915_query_topology_info { __u8 data[]; }; -/** - * DOC: Engine Discovery uAPI - * - * Engine discovery uAPI is a way of enumerating physical engines present in a - * GPU associated with an open i915 DRM file descriptor. This supersedes the old - * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like - * `I915_PARAM_HAS_BLT`. - * - * The need for this interface came starting with Icelake and newer GPUs, which - * started to establish a pattern of having multiple engines of a same class, - * where not all instances were always completely functionally equivalent. - * - * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the - * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. - * - * Example for getting the list of engines: - * - * .. code-block:: C - * - * struct drm_i915_query_engine_info *info; - * struct drm_i915_query_item item = { - * .query_id = DRM_I915_QUERY_ENGINE_INFO; - * }; - * struct drm_i915_query query = { - * .num_items = 1, - * .items_ptr = (uintptr_t)&item, - * }; - * int err, i; - * - * // First query the size of the blob we need, this needs to be large - * // enough to hold our array of engines. The kernel will fill out the - * // item.length for us, which is the number of bytes we need. - * // - * // Alternatively a large buffer can be allocated straight away enabling - * // querying in one pass, in which case item.length should contain the - * // length of the provided buffer. - * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); - * if (err) ... - * - * info = calloc(1, item.length); - * // Now that we allocated the required number of bytes, we call the ioctl - * // again, this time with the data_ptr pointing to our newly allocated - * // blob, which the kernel can then populate with info on all engines. - * item.data_ptr = (uintptr_t)&info, - * - * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); - * if (err) ... - * - * // We can now access each engine in the array - * for (i = 0; i < info->num_engines; i++) { - * struct drm_i915_engine_info einfo = info->engines[i]; - * u16 class = einfo.engine.class; - * u16 instance = einfo.engine.instance; - * .... - * } - * - * free(info); - * - * Each of the enumerated engines, apart from being defined by its class and - * instance (see `struct i915_engine_class_instance`), also can have flags and - * capabilities defined as documented in i915_drm.h. - * - * For instance video engines which support HEVC encoding will have the - * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. - * - * Engine discovery only fully comes to its own when combined with the new way - * of addressing engines when submitting batch buffers using contexts with - * engine maps configured. - */ - /** * struct drm_i915_engine_info * * Describes one engine and it's capabilities as known to the driver. + * + * FIXME: revert to upstream version after UMD switch to PRELIM version */ struct drm_i915_engine_info { /** @engine: Engine class and instance. */ @@ -2806,243 +2517,13 @@ struct drm_i915_query_perf_config { __u8 data[]; }; -/** - * enum drm_i915_gem_memory_class - Supported memory classes - */ -enum drm_i915_gem_memory_class { - /** @I915_MEMORY_CLASS_SYSTEM: System memory */ - I915_MEMORY_CLASS_SYSTEM = 0, - /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */ - I915_MEMORY_CLASS_DEVICE, -}; +#include "i915_drm_prelim.h" -/** - * struct drm_i915_gem_memory_class_instance - Identify particular memory region - */ -struct drm_i915_gem_memory_class_instance { - /** @memory_class: See enum drm_i915_gem_memory_class */ - __u16 memory_class; - - /** @memory_instance: Which instance */ - __u16 memory_instance; -}; - -/** - * struct drm_i915_memory_region_info - Describes one region as known to the - * driver. - * - * Note that we reserve some stuff here for potential future work. As an example - * we might want expose the capabilities for a given region, which could include - * things like if the region is CPU mappable/accessible, what are the supported - * mapping types etc. - * - * Note that to extend struct drm_i915_memory_region_info and struct - * drm_i915_query_memory_regions in the future the plan is to do the following: - * - * .. code-block:: C - * - * struct drm_i915_memory_region_info { - * struct drm_i915_gem_memory_class_instance region; - * union { - * __u32 rsvd0; - * __u32 new_thing1; - * }; - * ... - * union { - * __u64 rsvd1[8]; - * struct { - * __u64 new_thing2; - * __u64 new_thing3; - * ... - * }; - * }; - * }; - * - * With this things should remain source compatible between versions for - * userspace, even as we add new fields. - * - * Note this is using both struct drm_i915_query_item and struct drm_i915_query. - * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS - * at &drm_i915_query_item.query_id. - */ -struct drm_i915_memory_region_info { - /** @region: The class:instance pair encoding */ - struct drm_i915_gem_memory_class_instance region; - - /** @rsvd0: MBZ */ - __u32 rsvd0; - - /** @probed_size: Memory probed by the driver (-1 = unknown) */ - __u64 probed_size; - - /** @unallocated_size: Estimate of memory remaining (-1 = unknown) */ - __u64 unallocated_size; - - /** @rsvd1: MBZ */ - __u64 rsvd1[8]; -}; - -/** - * struct drm_i915_query_memory_regions - * - * The region info query enumerates all regions known to the driver by filling - * in an array of struct drm_i915_memory_region_info structures. - * - * Example for getting the list of supported regions: - * - * .. code-block:: C - * - * struct drm_i915_query_memory_regions *info; - * struct drm_i915_query_item item = { - * .query_id = DRM_I915_QUERY_MEMORY_REGIONS; - * }; - * struct drm_i915_query query = { - * .num_items = 1, - * .items_ptr = (uintptr_t)&item, - * }; - * int err, i; - * - * // First query the size of the blob we need, this needs to be large - * // enough to hold our array of regions. The kernel will fill out the - * // item.length for us, which is the number of bytes we need. - * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); - * if (err) ... - * - * info = calloc(1, item.length); - * // Now that we allocated the required number of bytes, we call the ioctl - * // again, this time with the data_ptr pointing to our newly allocated - * // blob, which the kernel can then populate with the all the region info. - * item.data_ptr = (uintptr_t)&info, - * - * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); - * if (err) ... - * - * // We can now access each region in the array - * for (i = 0; i < info->num_regions; i++) { - * struct drm_i915_memory_region_info mr = info->regions[i]; - * u16 class = mr.region.class; - * u16 instance = mr.region.instance; - * - * .... - * } - * - * free(info); - */ -struct drm_i915_query_memory_regions { - /** @num_regions: Number of supported regions */ - __u32 num_regions; - - /** @rsvd: MBZ */ - __u32 rsvd[3]; - - /** @regions: Info about each supported region */ - struct drm_i915_memory_region_info regions[]; -}; - -/** - * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added - * extension support using struct i915_user_extension. - * - * Note that in the future we want to have our buffer flags here, at least for - * the stuff that is immutable. Previously we would have two ioctls, one to - * create the object with gem_create, and another to apply various parameters, - * however this creates some ambiguity for the params which are considered - * immutable. Also in general we're phasing out the various SET/GET ioctls. - */ -struct drm_i915_gem_create_ext { - /** - * @size: Requested size for the object. - * - * The (page-aligned) allocated size for the object will be returned. - * - * Note that for some devices we have might have further minimum - * page-size restrictions(larger than 4K), like for device local-memory. - * However in general the final size here should always reflect any - * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS - * extension to place the object in device local-memory. - */ - __u64 size; - /** - * @handle: Returned handle for the object. - * - * Object handles are nonzero. - */ - __u32 handle; - /** @flags: MBZ */ - __u32 flags; - /** - * @extensions: The chain of extensions to apply to this object. - * - * This will be useful in the future when we need to support several - * different extensions, and we need to apply more than one when - * creating the object. See struct i915_user_extension. - * - * If we don't supply any extensions then we get the same old gem_create - * behaviour. - * - * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see - * struct drm_i915_gem_create_ext_memory_regions. - */ -#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 - __u64 extensions; -}; - -/** - * struct drm_i915_gem_create_ext_memory_regions - The - * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension. - * - * Set the object with the desired set of placements/regions in priority - * order. Each entry must be unique and supported by the device. - * - * This is provided as an array of struct drm_i915_gem_memory_class_instance, or - * an equivalent layout of class:instance pair encodings. See struct - * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to - * query the supported regions for a device. - * - * As an example, on discrete devices, if we wish to set the placement as - * device local-memory we can do something like: - * - * .. code-block:: C - * - * struct drm_i915_gem_memory_class_instance region_lmem = { - * .memory_class = I915_MEMORY_CLASS_DEVICE, - * .memory_instance = 0, - * }; - * struct drm_i915_gem_create_ext_memory_regions regions = { - * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, - * .regions = (uintptr_t)®ion_lmem, - * .num_regions = 1, - * }; - * struct drm_i915_gem_create_ext create_ext = { - * .size = 16 * PAGE_SIZE, - * .extensions = (uintptr_t)®ions, - * }; - * - * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); - * if (err) ... - * - * At which point we get the object handle in &drm_i915_gem_create_ext.handle, - * along with the final object size in &drm_i915_gem_create_ext.size, which - * should account for any rounding up, if required. - */ -struct drm_i915_gem_create_ext_memory_regions { - /** @base: Extension link. See struct i915_user_extension. */ - struct i915_user_extension base; - - /** @pad: MBZ */ - __u32 pad; - /** @num_regions: Number of elements in the @regions array. */ - __u32 num_regions; - /** - * @regions: The regions/placements array. - * - * An array of struct drm_i915_gem_memory_class_instance. - */ - __u64 regions; -}; +/* ID of the protected content session managed by i915 when PXP is active */ +#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf #if defined(__cplusplus) } #endif -#endif /* _UAPI_I915_DRM_H_ */ +#endif /* _I915_DRM_H_ */ diff --git a/third_party/uapi/prelim/drm/i915_drm_prelim.h b/third_party/uapi/prelim/drm/i915_drm_prelim.h new file mode 100644 index 0000000000..4b4b394f7c --- /dev/null +++ b/third_party/uapi/prelim/drm/i915_drm_prelim.h @@ -0,0 +1,1742 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ + +#ifndef __I915_DRM_PRELIM_H__ +#define __I915_DRM_PRELIM_H__ + +#include "drm.h" + +/* + * Modifications to structs/values defined here are subject to + * backwards-compatibility constraints. + * + * Internal/downstream declarations must be added here, not to + * i915_drm.h. The values in i915_drm_prelim.h must also be kept + * synchronized with values in i915_drm.h. + */ + +struct prelim_i915_uevent { +/* + * PRELIM_I915_RESET_FAILED_UEVENT - Event is generated when engine or GPU + * resets fail and also when GPU is declared wedged. The value + * supplied with the event is always 1. Event is also generated when + * resets are disabled by module parameter and an attempt to reset + * either engine or GPU is made. + */ +#define PRELIM_I915_RESET_FAILED_UEVENT "RESET_FAILED" + +/* + * PRELIM_I915_MEMORY_HEALTH_UEVENT - Generated when driver receives a memory + * degradation error from the GPU FW. The event serves as notification to + * an Admin to reboot the system as soon as possible, due to the fact that + * device is no longer RUNTIME recoverable again. This event will always + * have a value of 1, which indicates that uncorrectable error has been + * detected, and that runtime memory sparing is not feasible without system + * reboot - for recovery of failed BANK. + */ +#define PRELIM_I915_MEMORY_HEALTH_UEVENT "MEMORY_HEALTH" +}; + +struct prelim_i915_user_extension { +#define PRELIM_I915_USER_EXT (1 << 16) +#define PRELIM_I915_USER_EXT_MASK(x) (x & 0xffff) +}; + +struct prelim_drm_i915_gem_context_create_ext_clone { +#define PRELIM_I915_CONTEXT_CREATE_EXT_CLONE (PRELIM_I915_USER_EXT | 1) + struct i915_user_extension base; + __u32 clone_id; + __u32 flags; +#define PRELIM_I915_CONTEXT_CLONE_ENGINES (1u << 0) +#define PRELIM_I915_CONTEXT_CLONE_FLAGS (1u << 1) +#define PRELIM_I915_CONTEXT_CLONE_SCHEDATTR (1u << 2) +#define PRELIM_I915_CONTEXT_CLONE_SSEU (1u << 3) +#define PRELIM_I915_CONTEXT_CLONE_TIMELINE (1u << 4) +#define PRELIM_I915_CONTEXT_CLONE_VM (1u << 5) +#define PRELIM_I915_CONTEXT_CLONE_UNKNOWN -(PRELIM_I915_CONTEXT_CLONE_VM << 1) + __u64 rsvd; +}; + +/* + * PRELIM UAPI VERSION - /sys/<...>/drm/card/prelim_uapi_version + * MAJOR - to be incremented right after a major public Production branch + * release containing PRELIM uAPIs + * PROD_DG1_201210.0 released so starting with major = 2, although + * it didn't have the proper prelim api infrastructure yet. + * MINOR - Reset to 0 when MAJOR is bumped. + * Bumped as needed when some kind of API incompatibility is identified. + * This patch, which introduces this, should be the only patch in + * the pile that is changing this number. + */ +#define PRELIM_UAPI_MAJOR 2 +#define PRELIM_UAPI_MINOR 0 + +/* + * Top 8 bits of every non-engine counter are GT id. + * FIXME: __PRELIM_I915_PMU_GT_SHIFT will be changed to 56 + */ +#define __PRELIM_I915_PMU_GT_SHIFT (60) + +#define ___PRELIM_I915_PMU_OTHER(gt, x) \ + (((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \ + ((__u64)(gt) << __PRELIM_I915_PMU_GT_SHIFT)) + +#define __I915_PMU_OTHER(x) ___PRELIM_I915_PMU_OTHER(0, x) + +#define __PRELIM_I915_PMU_ACTUAL_FREQUENCY(gt) ___PRELIM_I915_PMU_OTHER(gt, 0) +#define __PRELIM_I915_PMU_REQUESTED_FREQUENCY(gt) ___PRELIM_I915_PMU_OTHER(gt, 1) +#define __PRELIM_I915_PMU_INTERRUPTS(gt) ___PRELIM_I915_PMU_OTHER(gt, 2) +#define __PRELIM_I915_PMU_RC6_RESIDENCY(gt) ___PRELIM_I915_PMU_OTHER(gt, 3) +#define __PRELIM_I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt) ___PRELIM_I915_PMU_OTHER(gt, 4) +#define __PRELIM_I915_PMU_ENGINE_RESET_COUNT(gt) ___PRELIM_I915_PMU_OTHER(gt, 5) +#define __PRELIM_I915_PMU_EU_ATTENTION_COUNT(gt) ___PRELIM_I915_PMU_OTHER(gt, 6) +#define __PRELIM_I915_PMU_RENDER_GROUP_BUSY(gt) ___PRELIM_I915_PMU_OTHER(gt, 7) +#define __PRELIM_I915_PMU_COPY_GROUP_BUSY(gt) ___PRELIM_I915_PMU_OTHER(gt, 8) +#define __PRELIM_I915_PMU_MEDIA_GROUP_BUSY(gt) ___PRELIM_I915_PMU_OTHER(gt, 9) +#define __PRELIM_I915_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___PRELIM_I915_PMU_OTHER(gt, 10) + + +#define __PRELIM_I915_PMU_HW_ERROR_EVENT_ID_OFFSET (__I915_PMU_OTHER(0) + 1000) + +#define PRELIM_I915_PMU_ENGINE_RESET_COUNT __PRELIM_I915_PMU_ENGINE_RESET_COUNT(0) +#define PRELIM_I915_PMU_EU_ATTENTION_COUNT __PRELIM_I915_PMU_EU_ATTENTION_COUNT(0) +#define PRELIM_I915_PMU_RENDER_GROUP_BUSY __PRELIM_I915_PMU_RENDER_GROUP_BUSY(0) +#define PRELIM_I915_PMU_COPY_GROUP_BUSY __PRELIM_I915_PMU_COPY_GROUP_BUSY(0) +#define PRELIM_I915_PMU_MEDIA_GROUP_BUSY __PRELIM_I915_PMU_MEDIA_GROUP_BUSY(0) +#define PRELIM_I915_PMU_ANY_ENGINE_GROUP_BUSY __PRELIM_I915_PMU_ANY_ENGINE_GROUP_BUSY(0) + +/* + * HW error counters. + */ +#define PRELIM_I915_PMU_GT_ERROR_CORRECTABLE_L3_SNG (0) +#define PRELIM_I915_PMU_GT_ERROR_CORRECTABLE_GUC (1) +#define PRELIM_I915_PMU_GT_ERROR_CORRECTABLE_SAMPLER (2) +#define PRELIM_I915_PMU_GT_ERROR_CORRECTABLE_SLM (3) +#define PRELIM_I915_PMU_GT_ERROR_CORRECTABLE_EU_IC (4) +#define PRELIM_I915_PMU_GT_ERROR_CORRECTABLE_EU_GRF (5) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_ARR_BIST (6) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_L3_DOUB (7) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_L3_ECC_CHK (8) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_GUC (9) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_IDI_PAR (10) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_SQIDI (11) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_SAMPLER (12) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_SLM (13) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_EU_IC (14) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_EU_GRF (15) +#define PRELIM_I915_PMU_SGUNIT_ERROR_CORRECTABLE (16) +#define PRELIM_I915_PMU_SGUNIT_ERROR_NONFATAL (17) +#define PRELIM_I915_PMU_SGUNIT_ERROR_FATAL (18) +#define PRELIM_I915_PMU_SOC_ERROR_CORRECTABLE_PSF_CSC_0 (19) +#define PRELIM_I915_PMU_SOC_ERROR_CORRECTABLE_PSF_CSC_1 (20) +#define PRELIM_I915_PMU_SOC_ERROR_NONFATAL_PSF_CSC_0 (21) +#define PRELIM_I915_PMU_SOC_ERROR_NONFATAL_PSF_CSC_1 (22) +#define PRELIM_I915_PMU_SOC_ERROR_NONFATAL_PSF_CSC_2 (23) +#define PRELIM_I915_PMU_SOC_ERROR_FATAL_PSF_CSC_0 (24) +#define PRELIM_I915_PMU_SOC_ERROR_FATAL_PSF_CSC_1 (25) +#define PRELIM_I915_PMU_SOC_ERROR_FATAL_PSF_CSC_2 (26) +#define PRELIM_I915_PMU_SOC_ERROR_CORRECTABLE_PUNIT (27) +#define PRELIM_I915_PMU_SOC_ERROR_CORRECTABLE_MDFI_EAST (28) +#define PRELIM_I915_PMU_SOC_ERROR_CORRECTABLE_MDFI_WEST (29) +#define PRELIM_I915_PMU_SOC_ERROR_CORRECTABLE_MDFI_SOUTH (30) +#define PRELIM_I915_PMU_SOC_ERROR_NONFATAL_PUNIT (31) +#define PRELIM_I915_PMU_SOC_ERROR_NONFATAL_MDFI_EAST (32) +#define PRELIM_I915_PMU_SOC_ERROR_NONFATAL_MDFI_WEST (33) +#define PRELIM_I915_PMU_SOC_ERROR_NONFATAL_MDFI_SOUTH (34) +#define PRELIM_I915_PMU_SOC_ERROR_FATAL_PUNIT (35) +#define PRELIM_I915_PMU_SOC_ERROR_FATAL_MDFI_EAST (36) +#define PRELIM_I915_PMU_SOC_ERROR_FATAL_MDFI_WEST (37) +#define PRELIM_I915_PMU_SOC_ERROR_FATAL_MDFI_SOUTH (38) + +#define PRELIM_I915_PMU_SOC_ERROR_CORRECTABLE_FBR(ss, n) \ + (PRELIM_I915_PMU_SOC_ERROR_FATAL_MDFI_SOUTH + 0x1 + (ss) * 0x4 + (n)) + +#define PRELIM_I915_PMU_SOC_ERROR_NONFATAL_FBR(ss, n) \ + (PRELIM_I915_PMU_SOC_ERROR_CORRECTABLE_FBR(1, 5) + (ss) * 0x4 + (n)) + +#define PRELIM_I915_PMU_SOC_ERROR_FATAL_FBR(ss, n) \ + (PRELIM_I915_PMU_SOC_ERROR_NONFATAL_FBR(1, 5) + (ss) * 0x4 + (n)) + +#define PRELIM_I915_PMU_SOC_ERROR_CORRECTABLE_HBM(ss, n)\ + (PRELIM_I915_PMU_SOC_ERROR_FATAL_FBR(1, 5) + (ss) * 0x10 + (n)) + +#define PRELIM_I915_PMU_SOC_ERROR_NONFATAL_HBM(ss, n)\ + (PRELIM_I915_PMU_SOC_ERROR_CORRECTABLE_HBM(1, 16) + (ss) * 0x10 + (n)) + +#define PRELIM_I915_PMU_SOC_ERROR_FATAL_HBM(ss, n)\ + (PRELIM_I915_PMU_SOC_ERROR_NONFATAL_HBM(1, 16) + (ss) * 0x10 + (n)) + +/* 161 is the last ID used by SOC errors */ +#define PRELIM_I915_PMU_GT_ERROR_FATAL_FPU (162) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_TLB (163) +#define PRELIM_I915_PMU_GT_ERROR_FATAL_L3_FABRIC (164) + +#define PRELIM_I915_PMU_HW_ERROR(gt, id) \ + ((__PRELIM_I915_PMU_HW_ERROR_EVENT_ID_OFFSET + (id)) | \ + ((__u64)(gt) << __PRELIM_I915_PMU_GT_SHIFT)) + +/* Per GT driver error counters */ +#define __PRELIM_I915_PMU_GT_DRIVER_ERROR_EVENT_ID_OFFSET (__I915_PMU_OTHER(0) + 2000) + +#define PRELIM_I915_PMU_GT_DRIVER_ERROR_GGTT (0) +#define PRELIM_I915_PMU_GT_DRIVER_ERROR_ENGINE_OTHER (1) +#define PRELIM_I915_PMU_GT_DRIVER_ERROR_GUC_COMMUNICATION (2) +#define PRELIM_I915_PMU_GT_DRIVER_ERROR_RPS (3) +#define PRELIM_I915_PMU_GT_DRIVER_ERROR_GT_OTHER (4) +#define PRELIM_I915_PMU_GT_DRIVER_ERROR_INTERRUPT (5) + +#define PRELIM_I915_PMU_GT_DRIVER_ERROR(gt, id) \ + ((__PRELIM_I915_PMU_GT_DRIVER_ERROR_EVENT_ID_OFFSET + (id)) | \ + ((__u64)(gt) << __PRELIM_I915_PMU_GT_SHIFT)) + +/* Global driver error counters */ +#define __PRELIM_I915_PMU_DRIVER_ERROR_EVENT_ID_OFFSET (__I915_PMU_OTHER(0) + 3000) +#define PRELIM_I915_PMU_DRIVER_ERROR_OBJECT_MIGRATION (0) +#define PRELIM_I915_PMU_DRIVER_ERROR(id) (__PRELIM_I915_PMU_DRIVER_ERROR_EVENT_ID_OFFSET + (id)) + +/* PRELIM ioctl's */ + +/* PRELIM ioctl numbers go down from 0x5f */ +#define PRELIM_DRM_I915_RESERVED_FOR_VERSION 0x5f +/* 0x5e is free, please use if needed */ +#define PRELIM_DRM_I915_GEM_VM_BIND 0x5d +#define PRELIM_DRM_I915_GEM_VM_UNBIND 0x5c +#define PRELIM_DRM_I915_GEM_VM_ADVISE 0x5b +#define PRELIM_DRM_I915_GEM_WAIT_USER_FENCE 0x5a +#define PRELIM_DRM_I915_GEM_VM_PREFETCH 0x59 +#define PRELIM_DRM_I915_UUID_REGISTER 0x58 +#define PRELIM_DRM_I915_UUID_UNREGISTER 0x57 +#define PRELIM_DRM_I915_DEBUGGER_OPEN 0x56 +#define PRELIM_DRM_I915_GEM_CLOS_RESERVE 0x55 +#define PRELIM_DRM_I915_GEM_CLOS_FREE 0x54 +#define PRELIM_DRM_I915_GEM_CACHE_RESERVE 0x53 +#define PRELIM_DRM_I915_GEM_VM_GETPARAM DRM_I915_GEM_CONTEXT_GETPARAM +#define PRELIM_DRM_I915_GEM_VM_SETPARAM DRM_I915_GEM_CONTEXT_SETPARAM +#define PRELIM_DRM_I915_GEM_OBJECT_SETPARAM DRM_I915_GEM_CONTEXT_SETPARAM +#define PRELIM_DRM_I915_PXP_OPS 0x52 + + +#define PRELIM_DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct prelim_drm_i915_gem_create_ext) +#define PRELIM_DRM_IOCTL_I915_GEM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_GEM_VM_BIND, struct prelim_drm_i915_gem_vm_bind) +#define PRELIM_DRM_IOCTL_I915_GEM_VM_UNBIND DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_GEM_VM_UNBIND, struct prelim_drm_i915_gem_vm_bind) +#define PRELIM_DRM_IOCTL_I915_GEM_VM_ADVISE DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_GEM_VM_ADVISE, struct prelim_drm_i915_gem_vm_advise) +#define PRELIM_DRM_IOCTL_I915_GEM_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_GEM_WAIT_USER_FENCE, struct prelim_drm_i915_gem_wait_user_fence) +#define PRELIM_DRM_IOCTL_I915_GEM_VM_PREFETCH DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_GEM_VM_PREFETCH, struct prelim_drm_i915_gem_vm_prefetch) +#define PRELIM_DRM_IOCTL_I915_UUID_REGISTER DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_UUID_REGISTER, struct prelim_drm_i915_uuid_control) +#define PRELIM_DRM_IOCTL_I915_UUID_UNREGISTER DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_UUID_UNREGISTER, struct prelim_drm_i915_uuid_control) +#define PRELIM_DRM_IOCTL_I915_DEBUGGER_OPEN DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_DEBUGGER_OPEN, struct prelim_drm_i915_debugger_open_param) +#define PRELIM_DRM_IOCTL_I915_GEM_CLOS_RESERVE DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_GEM_CLOS_RESERVE, struct prelim_drm_i915_gem_clos_reserve) +#define PRELIM_DRM_IOCTL_I915_GEM_CLOS_FREE DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_GEM_CLOS_FREE, struct prelim_drm_i915_gem_clos_free) +#define PRELIM_DRM_IOCTL_I915_GEM_CACHE_RESERVE DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_GEM_CACHE_RESERVE, struct prelim_drm_i915_gem_cache_reserve) +#define PRELIM_DRM_IOCTL_I915_GEM_VM_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_GEM_VM_GETPARAM, struct prelim_drm_i915_gem_vm_param) +#define PRELIM_DRM_IOCTL_I915_GEM_VM_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_GEM_VM_SETPARAM, struct prelim_drm_i915_gem_vm_param) +#define PRELIM_DRM_IOCTL_I915_GEM_OBJECT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_GEM_OBJECT_SETPARAM, struct prelim_drm_i915_gem_object_param) +#define PRELIM_DRM_IOCTL_I915_PXP_OPS DRM_IOWR(DRM_COMMAND_BASE + PRELIM_DRM_I915_PXP_OPS, struct prelim_drm_i915_pxp_ops) + +/* End PRELIM ioctl's */ + +/* getparam */ +#define PRELIM_I915_PARAM (1 << 16) +/* + * Querying I915_PARAM_EXECBUF2_MAX_ENGINE will return the number of context + * map engines addressable via the low bits of execbuf2 flags, or in the + * cases where the parameter is not supported (-EINVAL), legacy maximum of + * 64 engines should be assumed. + */ +#define PRELIM_I915_PARAM_EXECBUF2_MAX_ENGINE (PRELIM_I915_PARAM | 1) + +/* Total local memory in bytes */ +#define PRELIM_I915_PARAM_LMEM_TOTAL_BYTES (PRELIM_I915_PARAM | 2) + +/* Available local memory in bytes */ +#define PRELIM_I915_PARAM_LMEM_AVAIL_BYTES (PRELIM_I915_PARAM | 3) + +/* Shared Virtual Memory (SVM) support capability */ +#define PRELIM_I915_PARAM_HAS_SVM (PRELIM_I915_PARAM | 4) + +/* + * Frequency of the timestamps in OA reports. This used to be the same as the CS + * timestamp frequency, but differs on some platforms. + */ +#define PRELIM_I915_PARAM_OA_TIMESTAMP_FREQUENCY (PRELIM_I915_PARAM | 5) + +/* VM_BIND feature availability */ +#define PRELIM_I915_PARAM_HAS_VM_BIND (PRELIM_I915_PARAM | 6) + +/* Recoverable pagefault support */ +#define PRELIM_I915_PARAM_HAS_PAGE_FAULT (PRELIM_I915_PARAM | 7) +/* End getparam */ + +struct prelim_drm_i915_gem_create_ext { + + /** + * Requested size for the object. + * + * The (page-aligned) allocated size for the object will be returned. + */ + __u64 size; + /** + * Returned handle for the object. + * + * Object handles are nonzero. + */ + __u32 handle; + __u32 pad; +#define PRELIM_I915_GEM_CREATE_EXT_SETPARAM (PRELIM_I915_USER_EXT | 1) +#define PRELIM_I915_GEM_CREATE_EXT_PROTECTED_CONTENT (PRELIM_I915_USER_EXT | 2) +#define PRELIM_I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \ + (~(PRELIM_I915_GEM_CREATE_EXT_SETPARAM | PRELIM_I915_GEM_CREATE_EXT_PROTECTED_CONTENT)) + __u64 extensions; +}; + +struct prelim_drm_i915_gem_object_param { + /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */ + __u32 handle; + + /* Data pointer size */ + __u32 size; + +/* + * PRELIM_I915_OBJECT_PARAM: + * + * Select object namespace for the param. + */ +#define PRELIM_I915_OBJECT_PARAM (1ull << 48) + +/* + * PRELIM_I915_PARAM_MEMORY_REGIONS: + * + * Set the data pointer with the desired set of placements in priority + * order(each entry must be unique and supported by the device), as an array of + * prelim_drm_i915_gem_memory_class_instance, or an equivalent layout of class:instance + * pair encodings. See PRELIM_DRM_I915_QUERY_MEMORY_REGIONS for how to query the + * supported regions. + * + * Note that this requires the PRELIM_I915_OBJECT_PARAM namespace: + * .param = PRELIM_I915_OBJECT_PARAM | PRELIM_I915_PARAM_MEMORY_REGIONS + */ +#define PRELIM_I915_PARAM_MEMORY_REGIONS ((1 << 16) | 0x1) + __u64 param; + + /* Data value or pointer */ + __u64 data; +}; + +struct prelim_drm_i915_gem_create_ext_setparam { + struct i915_user_extension base; + struct prelim_drm_i915_gem_object_param param; +}; + +/** + * struct drm_i915_gem_create_ext_protected_content - The + * I915_OBJECT_PARAM_PROTECTED_CONTENT extension. + * + * If this extension is provided, buffer contents are expected to be + * protected by PXP encryption and requires decryption for scan out + * and processing. This is only possible on platforms that have PXP enabled, + * on all other scenarios ysing this extension will cause the ioctl to fail + * and return -ENODEV. The flags parameter is reserved for future expansion and + * must currently be set to zero. + * + * The buffer contents are considered invalid after a PXP session teardown. + * + * The encryption is guaranteed to be processed correctly only if the object + * is submitted with a context created using the + * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks + * at submission time on the validity of the objects involved, which can lead to + * the following errors being returned from the execbuf ioctl: + * + * -ENODEV: PXP session not currently active + * -ENOEXEC: buffer has become invalid after a teardown event + */ +struct prelim_drm_i915_gem_create_ext_protected_content { + struct i915_user_extension base; + __u32 flags; +}; + +/* + * struct pxp_set_session_status_params - Params to reserved, set or destroy + * the session from the PXP state machine. + */ +struct prelim_drm_i915_pxp_set_session_status_params { + __u32 pxp_tag; /* in/out, session identifier tag */ + __u32 session_type; /* in, session type */ + __u32 session_mode; /* in, session mode */ +#define PRELIM_DRM_I915_PXP_MODE_LM 0 +#define PRELIM_DRM_I915_PXP_MODE_HM 1 +#define PRELIM_DRM_I915_PXP_MODE_SM 2 + + __u32 req_session_state; /* in, new session state */ + /* Request KMD to allocate session id and move it to INIT */ +#define PRELIM_DRM_I915_PXP_REQ_SESSION_ID_INIT 0 + /* Inform KMD that UMD has completed the initialization */ +#define PRELIM_DRM_I915_PXP_REQ_SESSION_IN_PLAY 1 + /* Request KMD to terminate the session */ +#define PRELIM_DRM_I915_PXP_REQ_SESSION_TERMINATE 2 +} __attribute__((packed)); + +/* + * struct pxp_tee_io_message_params - Params to send/receive message to/from TEE. + */ +struct prelim_drm_i915_pxp_tee_io_message_params { + __u64 msg_in; /* in - pointer to buffer containing input message */ + __u32 msg_in_size; /* in - input message size */ + __u64 msg_out; /* in - pointer to buffer to store the output message */ + __u32 msg_out_buf_size; /* in - provided output message buffer size */ + __u32 msg_out_ret_size; /* out- output message actual size returned from TEE */ +} __attribute__((packed)); + +/* + * struct drm_i915_pxp_query_tag - Params to query the PXP tag of specified + * session id and whether the session is alive from PXP state machine. + */ +struct prelim_drm_i915_pxp_query_tag { + __u32 session_is_alive; + + /* + * in - Session ID, out pxp tag. + * Tag format: + * bits 0-6: session id + * bit 7: rsvd + * bits 8-15: instance id + * bit 16: session enabled + * bit 17: mode hm + * bit 18: rsvd + * bit 19: mode sm + * bits 20-31: rsvd + */ + __u32 pxp_tag; +#define PRELIM_DRM_I915_PXP_TAG_SESSION_ID_MASK (0x7f) +#define PRELIM_DRM_I915_PXP_TAG_INSTANCE_ID_MASK (0xff << 8) +#define PRELIM_DRM_I915_PXP_TAG_SESSION_ENABLED (0x1 << 16) +#define PRELIM_DRM_I915_PXP_TAG_SESSION_HM (0x1 << 17) +#define PRELIM_DRM_I915_PXP_TAG_SESSION_SM (0x1 << 19) +} __attribute__((packed)); + +/* + * DRM_I915_PXP_OPS - + * + * PXP is an i915 componment, that helps user space to establish the hardware + * protected session and manage the status of each alive software session, + * as well as the life cycle of each session. + * + * This ioctl is to allow user space driver to create, set, and destroy each + * session. It also provides the communication chanel to TEE (Trusted + * Execution Environment) for the protected hardware session creation. + */ + +struct prelim_drm_i915_pxp_ops { + __u32 action; /* in - specified action of this operation */ +#define PRELIM_DRM_I915_PXP_ACTION_SET_SESSION_STATUS 0 +#define PRELIM_DRM_I915_PXP_ACTION_TEE_IO_MESSAGE 1 +#define PRELIM_DRM_I915_PXP_ACTION_QUERY_PXP_TAG 2 + + __u32 status; /* out - status output for this operation */ +#define PRELIM_DRM_I915_PXP_OP_STATUS_SUCCESS 0 +#define PRELIM_DRM_I915_PXP_OP_STATUS_RETRY_REQUIRED 1 +#define PRELIM_DRM_I915_PXP_OP_STATUS_SESSION_NOT_AVAILABLE 2 +#define PRELIM_DRM_I915_PXP_OP_STATUS_ERROR_UNKNOWN 3 + + __u64 params; /* in/out - pointer to data matching the action */ +} __attribute__((packed)); + +#define PRELIM_PERF_VERSION (1000) + +/** + * Returns OA buffer properties to be used with mmap. + * + * This ioctl is available in perf revision 1000. + */ +#define PRELIM_I915_PERF_IOCTL_GET_OA_BUFFER_INFO _IOWR('i', 0x80, struct prelim_drm_i915_perf_oa_buffer_info) + +/** + * OA buffer size and offset. + * + * OA output buffer + * type: 0 + * flags: mbz + * + * After querying the info, pass (size,offset) to mmap(), + * + * mmap(0, info.size, PROT_READ, MAP_PRIVATE, perf_fd, info.offset). + * + * Note that only a private (not shared between processes, or across fork()) + * read-only mmapping is allowed. + * + * Userspace must treat the incoming data as tainted, but it conforms to the OA + * format as specified by user config. The buffer provides reports that have + * OA counters - A, B and C. + */ +struct prelim_drm_i915_perf_oa_buffer_info { + __u32 type; /* in */ + __u32 flags; /* in */ + __u64 size; /* out */ + __u64 offset; /* out */ + __u64 rsvd; /* mbz */ +}; + +enum prelim_drm_i915_eu_stall_property_id { + /** + * This field specifies the Per DSS Memory Buffer Size. + * Valid values are 128 KB, 256 KB, and 512 KB. + */ + PRELIM_DRM_I915_EU_STALL_PROP_BUF_SZ = 1001, + + /** + * This field specifies the sampling rate per tile + * in multiples of 251 cycles. Valid values are 1 to 7. + * If the value is 1, sampling interval is 251 cycles. + * If the value is 7, sampling interval is 7 x 251 cycles. + */ + PRELIM_DRM_I915_EU_STALL_PROP_SAMPLE_RATE, + + /** + * This field specifies the EU stall data poll period + * in nanoseconds. Minimum allowed value is 100 ms. + * A default value is used by the driver if this field + * is not specified. + */ + PRELIM_DRM_I915_EU_STALL_PROP_POLL_PERIOD, + + PRELIM_DRM_I915_EU_STALL_PROP_ENGINE_CLASS, + + PRELIM_DRM_I915_EU_STALL_PROP_ENGINE_INSTANCE, + + PRELIM_DRM_I915_EU_STALL_PROP_MAX +}; + +/* + * Info that the driver adds to each entry in the EU stall counters data. + */ +struct prelim_drm_i915_stall_cntr_info { + __u16 subslice; + __u16 flags; +/* EU stall data line dropped due to memory buffer being full */ +#define PRELIM_I915_EUSTALL_FLAG_OVERFLOW_DROP (1 << 8) +}; + +struct prelim_drm_i915_perf_open_param { + /* PRELIM flags */ +#define PRELIM_I915_PERF_FLAG_FD_EU_STALL (1 << 16) +}; + +struct prelim_drm_i915_gem_memory_class_instance { + __u16 memory_class; /* see enum prelim_drm_i915_gem_memory_class */ + __u16 memory_instance; +}; + +struct prelim_drm_i915_query_item { +#define PRELIM_DRM_I915_QUERY (1 << 16) +#define PRELIM_DRM_I915_QUERY_MASK(x) (x & 0xffff) +/* Keep lower 16 bits same as previous values */ +#define PRELIM_DRM_I915_QUERY_MEMORY_REGIONS (PRELIM_DRM_I915_QUERY | 4) +#define PRELIM_DRM_I915_QUERY_DISTANCE_INFO (PRELIM_DRM_I915_QUERY | 5) + /** + * Query HWConfig Table: Copies a device information table to the + * query's item.data_ptr directly if the allocated length is big enough + * For details about table format and content see intel_hwconfig_types.h + */ +#define PRELIM_DRM_I915_QUERY_HWCONFIG_TABLE (PRELIM_DRM_I915_QUERY | 6) +#define PRELIM_DRM_I915_QUERY_GEOMETRY_SLICES (PRELIM_DRM_I915_QUERY | 7) +#define PRELIM_DRM_I915_QUERY_COMPUTE_SLICES (PRELIM_DRM_I915_QUERY | 8) + /** + * Query Command Streamer timestamp register. + */ +#define PRELIM_DRM_I915_QUERY_CS_CYCLES (PRELIM_DRM_I915_QUERY | 9) + +#define PRELIM_DRM_I915_QUERY_FABRIC_INFO (PRELIM_DRM_I915_QUERY | 11) + +#define PRELIM_DRM_I915_QUERY_HW_IP_VERSION (PRELIM_DRM_I915_QUERY | 12) + +#define PRELIM_DRM_I915_QUERY_ENGINE_INFO (PRELIM_DRM_I915_QUERY | 13) +#define PRELIM_DRM_I915_QUERY_L3_BANK_COUNT (PRELIM_DRM_I915_QUERY | 14) +}; + +/* + * Number of BB in execbuf2 IOCTL - 1, used to submit more than BB in a single + * execbuf2 IOCTL. + * + * Return -EINVAL if more than 1 BB (value 0) is specified if + * PRELIM_I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT hasn't been called on the gem + * context first. Also returns -EINVAL if gem context has been setup with + * I915_PARALLEL_BB_PREEMPT_BOUNDARY and the number BBs not equal to the total + * number hardware contexts in the gem context. + */ +#define PRELIM_I915_EXEC_NUMBER_BB_LSB (48) +#define PRELIM_I915_EXEC_NUMBER_BB_MASK (0x3full << PRELIM_I915_EXEC_NUMBER_BB_LSB) +#define PRELIM_I915_EXEC_NUMBER_BB_MSB (54) +#define PRELIM_I915_EXEC_NUMBER_BB_MASK_MSB (1ull << PRELIM_I915_EXEC_NUMBER_BB_MSB) + +/* + * In XEHPSDV total number of engines can be more than the maximum supported + * engines by I915_EXEC_RING_MASK. + * PRELIM_I915_EXEC_ENGINE_MASK expands the total number of engines from 64 to 256. + * + * To use PRELIM_I915_EXEC_ENGINE_MASK, userspace needs to query + * I915_PARAM_EXECBUF2_MAX_ENGINE. On getting valid value, userspace needs + * to set PRELIM_I915_EXEC_ENGINE_MASK_SELECT to enable PRELIM_I915_EXEC_ENGINE_MASK. + * + * Bitfield associated with legacy I915_EXEC_CONSTANTS_MASK which was + * restricted previously, will be utilized by PRELIM_I915_EXEC_ENGINE_MASK. + * + * PRELIM_I915_EXEC_ENGINE_MASK only applies to contexts with engine map set up. + */ +#define PRELIM_I915_EXEC_ENGINE_MASK (0xff) +#define PRELIM_I915_EXEC_ENGINE_MASK_SELECT (1ull << 55) + +#define __PRELIM_I915_EXEC_UNKNOWN_FLAGS (~(GENMASK_ULL(55, 48) | ~__I915_EXEC_UNKNOWN_FLAGS)) + +/* + * Indicates the 2k user priority levels are statically mapped into 3 buckets as + * follows: + * + * -1k to -1 Low priority + * 0 Normal priority + * 1 to 1k Highest priority + */ +#define PRELIM_I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 31) + +enum prelim_drm_i915_gem_engine_class { +#define PRELIM_I915_ENGINE_CLASS (1 << 8) +#define PRELIM_I915_ENGINE_CLASS_MASK(x) (x & 0xff) + + PRELIM_I915_ENGINE_CLASS_COMPUTE = 4, +}; + +/* + * prelim_i915_context_engines_parallel_submit: + * + * Setup a gem context to allow multiple BBs to be submitted in a single execbuf + * IOCTL. Those BBs will then be scheduled to run on the GPU in parallel. + * + * All hardware contexts in the engine set are configured for parallel + * submission (i.e. once this gem context is configured for parallel submission, + * all the hardware contexts, regardless if a BB is available on each individual + * context, will be submitted to the GPU in parallel). A user can submit BBs to + * subset (or superset) of the hardware contexts, in a single execbuf IOCTL, but + * it is not recommended as it may reserve physical engines with nothing to run + * on them. Highly recommended to configure the gem context with N hardware + * contexts then always submit N BBs in a single IOCTL. + * + * Their are two currently defined ways to control the placement of the + * hardware contexts on physical engines: default behavior (no flags) and + * PRELIM_I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the + * future as new hardware / use cases arise. Details of how to use this + * interface below above the flags. + * + * Returns -EINVAL if hardware context placement configuration invalid or if the + * placement configuration isn't supported on the platform / submission + * interface. + */ +struct prelim_i915_context_engines_parallel_submit { + struct i915_user_extension base; + +/* + * Default placement behvavior (currently unsupported): + * + * Rather than restricting parallel submission to a single class with a + * logically contiguous placement (PRELIM_I915_PARALLEL_IMPLICT_BONDS), add a mode that + * enables parallel submission across multiple engine classes. In this case each + * context's logical engine mask indicates where that context can placed + * compared to the flag, PRELIM_I915_PARALLEL_IMPLICT_BONDS, where only the first + * context's logical mask controls the placement. It is implied in this mode + * that all contexts have mutual exclusive placement (e.g. if one context is + * running VCS0 no other contexts can run on VCS0). + * + * Example 1 pseudo code: + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID, INVALID) + * set_load_balance(engine_index=0, num_siblings=4, engines=VCS0,VCS1,VCS2,VCS3) + * set_load_balance(engine_index=1, num_siblings=4, engines=RCS0,RCS1,RCS2,RCS3) + * set_parallel() + * + * Results in the following valid placements: + * VCS0, RCS0 + * VCS0, RCS1 + * VCS0, RCS2 + * VCS0, RCS3 + * VCS1, RCS0 + * VCS1, RCS1 + * VCS1, RCS2 + * VCS1, RCS3 + * VCS2, RCS0 + * VCS2, RCS1 + * VCS2, RCS2 + * VCS2, RCS3 + * VCS3, RCS0 + * VCS3, RCS1 + * VCS3, RCS2 + * VCS3, RCS3 + * + * Example 2 pseudo code: + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID, INVALID) + * set_load_balance(engine_index=0, num_siblings=3, engines=VCS0,VCS1,VCS2) + * set_load_balance(engine_index=1, num_siblings=3, engines=VCS0,VCS1,VCS2) + * set_parallel() + * + * Results in the following valid placements: + * VCS0, VCS1 + * VCS0, VCS2 + * VCS1, VCS0 + * VCS1, VCS2 + * VCS2, VCS0 + * VCS2, VCS1 + * + * This enables a use case where all engines are created equally, we don't care + * where they are scheduled, we just want a certain number of resources, for + * those resources to be scheduled in parallel, and possibly across multiple + * engine classes. + * + * This mode is not supported with GuC submission gen12 or any prior platforms, + * but could be supported in execlists mode. Future GuC platforms may support + * this. + */ + +/* + * PRELIM_I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context. + * Each context must have the same number sibling and bonds are implictly create + * of the siblings. + * + * All of the below examples are in logical space. + * + * Example 1 pseudo code: + * set_engines(VCS0, VCS1) + * set_parallel(flags=PRELIM_I915_PARALLEL_IMPLICT_BONDS) + * + * Results in the following valid placements: + * VCS0, VCS1 + * + * Example 2 pseudo code: + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID, INVALID) + * set_load_balance(engine_index=0, num_siblings=4, engines=VCS0,VCS2,VCS4,VCS6) + * set_load_balance(engine_index=1, num_siblings=4, engines=VCS1,VCS3,VCS5,VCS7) + * set_parallel(flags=PRELIM_I915_PARALLEL_IMPLICT_BONDS) + * + * Results in the following valid placements: + * VCS0, VCS1 + * VCS2, VCS3 + * VCS4, VCS5 + * VCS6, VCS7 + * + * Example 3 pseudo code: + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID, INVALID, INVALID, INVALID) + * set_load_balance(engine_index=0, num_siblings=2, engines=VCS0,VCS4) + * set_load_balance(engine_index=1, num_siblings=2, engines=VCS1,VCS5) + * set_load_balance(engine_index=2, num_siblings=2, engines=VCS2,VCS6) + * set_load_balance(engine_index=3, num_siblings=2, engines=VCS3,VCS7) + * set_parallel(flags=PRELIM_I915_PARALLEL_IMPLICT_BONDS) + * + * Results in the following valid placements: + * VCS0, VCS1, VCS2, VCS3 + * VCS4, VCS5, VCS6, VCS7 + * + * This enables a use case where all engines are not equal and certain placement + * rules are required (i.e. split-frame requires all contexts to be placed in a + * logically contiguous order on the VCS engines on gen11/gen12 platforms). This + * use case (logically contiguous placement, within a single engine class) is + * supported when using GuC submission. Execlist mode could support all possible + * bonding configurations. + */ +#define PRELIM_I915_PARALLEL_IMPLICT_BONDS (1ull << 63) +/* + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption + * points on all hardware contexts between each BB. An example use case of this + * feature is split-frame on gen11 or gen12 hardware. When using this feature a + * BB must be submitted on each hardware context in the parallel gem context. + * The execbuf2 IOCTL enforces the user adheres to policy. + */ +#define PRELIM_I915_PARALLEL_BATCH_PREEMPT_BOUNDARY (1ull << 62) +#define __PRELIM_I915_PARALLEL_UNKNOWN_FLAGS (~GENMASK_ULL(63, 62)) + __u64 flags; /* all undefined flags must be zero */ + __u64 mbz64[4]; /* reserved for future use; must be zero */ +} __attribute__ ((packed)); + +/** + * struct prelim_drm_i915_context_engines_parallel2_submit - Configure engine + * for parallel submission. + * + * Setup a slot in the context engine map to allow multiple BBs to be submitted + * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU + * in parallel. Multiple hardware contexts are created internally in the i915 + * run these BBs. Once a slot is configured for N BBs only N BBs can be + * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user + * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how + * many BBs there are based on the slot's configuration. The N BBs are the last + * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set. + * + * The default placement behavior is to create implicit bonds between each + * context if each context maps to more than 1 physical engine (e.g. context is + * a virtual engine). Also we only allow contexts of same engine class and these + * contexts must be in logically contiguous order. Examples of the placement + * behavior described below. Lastly, the default is to not allow BBs to + * preempted mid BB rather insert coordinated preemption on all hardware + * contexts between each set of BBs. Flags may be added in the future to change + * both of these default behaviors. + * + * Returns -EINVAL if hardware context placement configuration is invalid or if + * the placement configuration isn't supported on the platform / submission + * interface. + * Returns -ENODEV if extension isn't supported on the platform / submission + * inteface. + * + * .. code-block:: + * + * Example 1 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=1, + * engines=CS[0],CS[1]) + * + * Results in the following valid placement: + * CS[0], CS[1] + * + * Example 2 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=2, + * engines=CS[0],CS[2],CS[1],CS[3]) + * + * Results in the following valid placements: + * CS[0], CS[1] + * CS[2], CS[3] + * + * This can also be thought of as 2 virtual engines described by 2-D array + * in the engines the field with bonds placed between each index of the + * virtual engines. e.g. CS[0] is bonded to CS[1], CS[2] is bonded to + * CS[3]. + * VE[0] = CS[0], CS[2] + * VE[1] = CS[1], CS[3] + * + * Example 3 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=2, + * engines=CS[0],CS[1],CS[1],CS[3]) + * + * Results in the following valid and invalid placements: + * CS[0], CS[1] + * CS[1], CS[3] - Not logical contiguous, return -EINVAL + */ +struct prelim_drm_i915_context_engines_parallel2_submit { + /** + * @base: base user extension. + */ + struct i915_user_extension base; + + /** + * @engine_index: slot for parallel engine + */ + __u16 engine_index; + + /** + * @width: number of contexts per parallel engine + */ + __u16 width; + + /** + * @num_siblings: number of siblings per context + */ + __u16 num_siblings; + + /** + * @mbz16: reserved for future use; must be zero + */ + __u16 mbz16; + + /** + * @flags: all undefined flags must be zero, currently not defined flags + */ + __u64 flags; + + /** + * @mbz64: reserved for future use; must be zero + */ + __u64 mbz64[3]; + + /** + * @engines: 2-d array of engine instances to configure parallel engine + * + * length = width (i) * num_siblings (j) + * index = j + i * num_siblings + */ + struct i915_engine_class_instance engines[0]; +} __attribute__ ((packed)); + +struct prelim_i915_context_param_engines { +#define PRELIM_I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT (PRELIM_I915_USER_EXT | 2) /* see prelim_i915_context_engines_parallel_submit */ +#define PRELIM_I915_CONTEXT_ENGINES_EXT_PARALLEL2_SUBMIT (PRELIM_I915_USER_EXT | 3) /* see prelim_i915_context_engines_parallel2_submit */ +}; + +/* PRELIM OA formats */ +enum prelim_drm_i915_oa_format { + PRELIM_I915_OA_FORMAT_START = 128, + + /* XEHPSDV */ + PRELIM_I915_OAR_FORMAT_A32u40_A4u32_B8_C8 = PRELIM_I915_OA_FORMAT_START, + PRELIM_I915_OA_FORMAT_A24u40_A14u32_B8_C8, + PRELIM_I915_OAM_FORMAT_A2u64_B8_C8, + + /* DG2 */ + PRELIM_I915_OAR_FORMAT_A36u64_B8_C8, + PRELIM_I915_OAC_FORMAT_A24u64_B8_C8, + PRELIM_I915_OA_FORMAT_A38u64_R2u64_B8_C8, + PRELIM_I915_OAM_FORMAT_A2u64_R2u64_B8_C8, + + PRELIM_I915_OA_FORMAT_MAX /* non-ABI */ +}; + +enum prelim_drm_i915_perf_record_type { +#define PRELIM_DRM_I915_PERF_RECORD (1 << 16) + /* + * MMIO trigger queue is full. + * This record type is available in perf revision 1003. + */ + PRELIM_DRM_I915_PERF_RECORD_OA_MMIO_TRG_Q_FULL = (PRELIM_DRM_I915_PERF_RECORD | 1), +}; + +/* + * Access Counter programming + * + * The programmable access counters enable hardware to detect and report + * frequently accessed pages. The report generated by hardware can be used by + * software for influencing page migration and data placement decisions. + * + * Once the count reaches the value set by trigger, HW generates trigger + * interrupt. DRM driver then starts the page migration from SMEM to + * LMEM so the upcoming access to the same page(s) from GPU will access LMEM + * to achive better performance. + * + * Due to the HW capacity limitation, an access counter can be de-allocated on + * the fly. If the counter getting de-allocated has reached at least notify + * it is reported to SW via interrupt. The driver interrupt handling is TBD. + * + * The use case is to let the upper layer SW such as Open CL to make the + * decision to program all the configurations and the DRM driver will handle + * the interrupts generated by HW. + * + * NOTE: if ac_notify is set to 0, access counter notification reporting is disabled + * if ac_trigger is set to 0, access counter triggering is disabled. + * + * Only allowed in i915_gem_context_create_ioctl extension + */ +struct prelim_drm_i915_gem_context_param_acc { + __u16 trigger; + __u16 notify; + __u8 granularity; +#define PRELIM_I915_CONTEXT_ACG_128K 0 +#define PRELIM_I915_CONTEXT_ACG_2M 1 +#define PRELIM_I915_CONTEXT_ACG_16M 2 +#define PRELIM_I915_CONTEXT_ACG_64M 3 + __u8 pad1; + __u16 pad2; +}; + +struct prelim_drm_i915_gem_context_param { +/* + * I915_CONTEXT_PARAM_DEBUG_FLAGS + * + * Set or clear debug flags associated with this context. + * The flags works with 32 bit masking to enable/disable individual + * flags. For example to set debug flag of bit position 0, the + * value needs to be 0x0000000100000001, and to clear flag of + * bit position 0, the value needs to be 0x0000000100000000. + * + */ +#define PRELIM_I915_CONTEXT_PARAM (1 << 16) +#define PRELIM_I915_CONTEXT_PARAM_DEBUG_FLAGS (PRELIM_I915_CONTEXT_PARAM | 0xfd) + +/* + * Notify driver that SIP is provided with the pipeline setup. + * Driver raises exception on hang resolution and waits for pipeline's + * sip to signal attention before capturing state of user objects + * associated with the context. + * + */ +#define PRELIM_I915_CONTEXT_PARAM_DEBUG_FLAG_SIP (1ull << 0) + +/* + * PRELIM_I915_CONTEXT_PARAM_ACC: + * + * To be able to change the access counter thresholds and configurations. + * + * By default: access counter feature is disabled. + */ +#define PRELIM_I915_CONTEXT_PARAM_ACC (PRELIM_I915_CONTEXT_PARAM | 0xd) +}; + +/* + * I915_CONTEXT_PARAM_PROTECTED_CONTENT: + * + * Mark that the context makes use of protected content, which will result + * in the context being invalidated when the protected content session is. + * This flag can only be set at context creation time and, when set to true, + * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE + * to false. This flag can't be set to true in conjunction with setting the + * I915_CONTEXT_PARAM_BANNABLE flag to false. + * + * Given the numerous restriction on this flag, there are several unique + * failure cases: + * + * -ENODEV: feature not available + * -EEXIST: trying to modify an existing context + * -EPERM: trying to mark a recoverable or not bannable context as protected + * -EACCES: submitting an invalidated context for execution + */ +#define PRELIM_I915_CONTEXT_PARAM_PROTECTED_CONTENT (PRELIM_I915_CONTEXT_PARAM | 0xe) + +struct prelim_drm_i915_gem_context_create_ext { +#define PRELIM_I915_CONTEXT_CREATE_FLAGS_ULLS (1u << 31) +#define PRELIM_I915_CONTEXT_CREATE_FLAGS_UNKNOWN \ + (~(PRELIM_I915_CONTEXT_CREATE_FLAGS_ULLS | ~I915_CONTEXT_CREATE_FLAGS_UNKNOWN)) +}; + +/* + * PRELIM_I915_CONTEXT_PARAM_RUNALONE: + * + * Enable runalone mode on a context, disabled by default. + */ +#define PRELIM_I915_CONTEXT_PARAM_RUNALONE (PRELIM_I915_CONTEXT_PARAM | 0xf) + +/* Downstream PRELIM properties */ +enum prelim_drm_i915_perf_property_id { + PRELIM_DRM_I915_PERF_PROP = (1 << 16), + + /** + * Specify a global OA buffer size to be allocated in bytes. The size + * specified must be supported by HW (before XEHPSDV supported sizes are + * powers of 2 ranging from 128Kb to 16Mb. With XEHPSDV max supported size + * is 128Mb). + * + * This property is available in perf revision 1001. + */ + PRELIM_DRM_I915_PERF_PROP_OA_BUFFER_SIZE = (PRELIM_DRM_I915_PERF_PROP | 1), + + /** + * Specify the engine class defined in @enum drm_i915_gem_engine_class. + * This defaults to I915_ENGINE_CLASS_RENDER or + * I915_ENGINE_CLASS_COMPUTE based on the platform. + * + * This property is available in perf revision 1002 + * + * Perf revision 1004 supports I915_ENGINE_CLASS_VIDEO and + * I915_ENGINE_CLASS_VIDEO_ENHANCE. + */ + PRELIM_DRM_I915_PERF_PROP_OA_ENGINE_CLASS = (PRELIM_DRM_I915_PERF_PROP | 2), + + /** + * Specify the engine instance. Defaults to 0. + * + * This property is available in perf revision 1002. + */ + PRELIM_DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE = (PRELIM_DRM_I915_PERF_PROP | 3), + + PRELIM_DRM_I915_PERF_PROP_LAST, + + PRELIM_DRM_I915_PERF_PROP_MAX = DRM_I915_PERF_PROP_MAX - 1 + \ + (PRELIM_DRM_I915_PERF_PROP_LAST & 0xffff) +}; + +struct prelim_drm_i915_uuid_control { + char uuid[36]; /* String formatted like + * "%08x-%04x-%04x-%04x-%012x" + */ + + __u32 uuid_class; /* Predefined UUID class or handle to + * the previously registered UUID Class + */ + + __u32 flags; /* MBZ */ + + __u64 ptr; /* Pointer to CPU memory payload associated + * with the UUID Resource. + * For uuid_class I915_UUID_CLASS_STRING + * it must point to valid string buffer. + * Otherwise must point to page aligned buffer + * or be NULL. + */ + + __u64 size; /* Length of the payload in bytes */ + +#define PRELIM_I915_UUID_CLASS_STRING ((__u32)-1) +/* + * d9900de4-be09-56ab-84a5-dfc280f52ee5 = + * sha1(“I915_UUID_CLASS_STRING”)[0..35] + */ +#define PRELIM_I915_UUID_CLASS_MAX_RESERVED ((__u32)-1024) + + __u32 handle; /* Output: Registered handle ID */ + + __u64 extensions; /* MBZ */ +}; + +/* + * struct prelim_drm_i915_vm_bind_ext_uuid + * + * Used for registering metadata that will be attached to the vm + */ +struct prelim_drm_i915_vm_bind_ext_uuid { +#define PRELIM_I915_VM_BIND_EXT_UUID (PRELIM_I915_USER_EXT | 1) + struct i915_user_extension base; + __u32 uuid_handle; /* Handle to the registered UUID resource. */ +}; + +/** + * Do a debug event read for a debugger connection. + * + * This ioctl is available in debug version 1. + */ +#define PRELIM_I915_DEBUG_IOCTL_READ_EVENT _IO('j', 0x0) +#define PRELIM_I915_DEBUG_IOCTL_READ_UUID _IOWR('j', 0x1, struct prelim_drm_i915_debug_read_uuid) +#define PRELIM_I915_DEBUG_IOCTL_VM_OPEN _IOW('j', 0x2, struct prelim_drm_i915_debug_vm_open) +#define PRELIM_I915_DEBUG_IOCTL_EU_CONTROL _IOWR('j', 0x3, struct prelim_drm_i915_debug_eu_control) +#define PRELIM_I915_DEBUG_IOCTL_ACK_EVENT _IOW('j', 0x4, struct prelim_drm_i915_debug_event_ack) + +struct prelim_drm_i915_debug_event { + __u32 type; +#define PRELIM_DRM_I915_DEBUG_EVENT_NONE 0 +#define PRELIM_DRM_I915_DEBUG_EVENT_READ 1 +#define PRELIM_DRM_I915_DEBUG_EVENT_CLIENT 2 +#define PRELIM_DRM_I915_DEBUG_EVENT_CONTEXT 3 +#define PRELIM_DRM_I915_DEBUG_EVENT_UUID 4 +#define PRELIM_DRM_I915_DEBUG_EVENT_VM 5 +#define PRELIM_DRM_I915_DEBUG_EVENT_VM_BIND 6 +#define PRELIM_DRM_I915_DEBUG_EVENT_CONTEXT_PARAM 7 +#define PRELIM_DRM_I915_DEBUG_EVENT_EU_ATTENTION 8 +#define PRELIM_DRM_I915_DEBUG_EVENT_ENGINES 9 +#define PRELIM_DRM_I915_DEBUG_EVENT_MAX_EVENT PRELIM_DRM_I915_DEBUG_EVENT_ENGINES + + __u32 flags; +#define PRELIM_DRM_I915_DEBUG_EVENT_CREATE (1 << 31) +#define PRELIM_DRM_I915_DEBUG_EVENT_DESTROY (1 << 30) +#define PRELIM_DRM_I915_DEBUG_EVENT_STATE_CHANGE (1 << 29) +#define PRELIM_DRM_I915_DEBUG_EVENT_NEED_ACK (1 << 28) + __u64 seqno; + __u64 size; +} __attribute__((packed)); + +struct prelim_drm_i915_debug_event_client { + struct prelim_drm_i915_debug_event base; /* .flags = CREATE/DESTROY */ + + __u64 handle; /* This is unique per debug connection */ +} __attribute__((packed)); + +struct prelim_drm_i915_debug_event_context { + struct prelim_drm_i915_debug_event base; + + __u64 client_handle; + __u64 handle; +} __attribute__((packed)); + +struct prelim_drm_i915_debugger_open_param { + __u64 pid; /* input: Target process ID */ + __u32 flags; +#define PRELIM_DRM_I915_DEBUG_FLAG_FD_NONBLOCK (1u << 31) + + __u32 version; + __u64 events; /* input: event types to subscribe to */ + __u64 extensions; /* MBZ */ +}; + +struct prelim_drm_i915_debug_event_uuid { + struct prelim_drm_i915_debug_event base; + __u64 client_handle; + + __u64 handle; + __u64 class_handle; /* Can be filtered based on pre-defined classes */ + __u64 payload_size; +} __attribute__((packed)); + +struct prelim_drm_i915_debug_event_vm { + struct prelim_drm_i915_debug_event base; + __u64 client_handle; + + __u64 handle; +} __attribute__((packed)); + +struct prelim_drm_i915_debug_event_vm_bind { + struct prelim_drm_i915_debug_event base; + __u64 client_handle; + + __u64 vm_handle; + __u64 va_start; + __u64 va_length; + __u32 num_uuids; + __u32 flags; + __u64 uuids[0]; +} __attribute__((packed)); + +struct prelim_drm_i915_debug_event_eu_attention { + struct prelim_drm_i915_debug_event base; + __u64 client_handle; + __u64 ctx_handle; + __u64 lrc_handle; + + __u32 flags; + + struct i915_engine_class_instance ci; + + __u32 bitmask_size; + + /** + * Bitmask of thread attentions starting from natural + * hardware order of slice=0,subslice=0,eu=0, 8 attention + * bits per eu. + * + * NOTE: For dual subslice GENs, the bitmask is for + * lockstepped EUs and not for logical EUs. This makes + * the bitmask includu only half of logical EU count + * provided by topology query as we only control the + * 'pair' instead of individual EUs. + */ + + __u8 bitmask[0]; +} __attribute__((packed)); + +struct prelim_drm_i915_debug_read_uuid { + __u64 client_handle; + __u64 handle; + __u32 flags; /* MBZ */ + char uuid[36]; /* output */ + __u64 payload_ptr; + __u64 payload_size; +} __attribute__((packed)); + +struct prelim_drm_i915_debug_event_context_param { + struct prelim_drm_i915_debug_event base; + __u64 client_handle; + __u64 ctx_handle; + struct drm_i915_gem_context_param param; +} __attribute__((packed)); + +struct prelim_drm_i915_debug_engine_info { + struct i915_engine_class_instance engine; + __u64 lrc_handle; +} __attribute__((packed)); + +struct prelim_drm_i915_debug_event_engines { + struct prelim_drm_i915_debug_event base; + __u64 client_handle; + __u64 ctx_handle; + __u64 num_engines; + struct prelim_drm_i915_debug_engine_info engines[0]; +} __attribute__((packed)); + +struct prelim_drm_i915_debug_vm_open { + __u64 client_handle; + __u64 handle; /* input: The target address space (ppGTT) */ + __u64 flags; +#define PRELIM_I915_DEBUG_VM_OPEN_READ_ONLY O_RDONLY +#define PRELIM_I915_DEBUG_VM_OPEN_WRITE_ONLY O_WRONLY +#define PRELIM_I915_DEBUG_VM_OPEN_READ_WRITE O_RDWR +}; + +struct prelim_drm_i915_debug_eu_control { + __u64 client_handle; + __u32 cmd; +#define PRELIM_I915_DEBUG_EU_THREADS_CMD_INTERRUPT_ALL 0 +#define PRELIM_I915_DEBUG_EU_THREADS_CMD_STOPPED 1 +#define PRELIM_I915_DEBUG_EU_THREADS_CMD_RESUME 2 +#define PRELIM_I915_DEBUG_EU_THREADS_CMD_INTERRUPT 3 + __u32 flags; + __u64 seqno; + + struct i915_engine_class_instance ci; + __u32 bitmask_size; + + /** + * Bitmask of thread attentions starting from natural + * hardware order of slice=0,subslice=0,eu=0, 8 attention bits + * per eu. + * + * NOTE: For dual subslice GENs, the bitmask is for + * lockstepped EUs and not for logical EUs. This makes + * the bitmask includu only half of logical EU count + * provided by topology query as we only control the + * 'pair' instead of individual EUs. + */ + __u64 bitmask_ptr; +} __attribute__((packed)); + +struct prelim_drm_i915_debug_event_ack { + __u32 type; + __u32 flags; /* MBZ */ + __u64 seqno; +} __attribute__((packed)); + +enum prelim_drm_i915_gem_memory_class { + PRELIM_I915_MEMORY_CLASS_SYSTEM = 0, + PRELIM_I915_MEMORY_CLASS_DEVICE, + PRELIM_I915_MEMORY_CLASS_NONE = -1 +}; + +/** + * struct prelim_drm_i915_memory_region_info + * + * Describes one region as known to the driver. + */ +struct prelim_drm_i915_memory_region_info { + /** class:instance pair encoding */ + struct prelim_drm_i915_gem_memory_class_instance region; + + /** MBZ */ + __u32 rsvd0; + + /** MBZ */ + __u64 caps; + + /** MBZ */ + __u64 flags; + + /** Memory probed by the driver (-1 = unknown) */ + __u64 probed_size; + + /** Estimate of memory remaining (-1 = unknown) */ + __u64 unallocated_size; + + /** MBZ */ + __u64 rsvd1[8]; +}; + +/** + * struct prelim_drm_i915_query_memory_regions + * + * Region info query enumerates all regions known to the driver by filling in + * an array of struct prelim_drm_i915_memory_region_info structures. + */ +struct prelim_drm_i915_query_memory_regions { + /** Number of supported regions */ + __u32 num_regions; + + /** MBZ */ + __u32 rsvd[3]; + + /* Info about each supported region */ + struct prelim_drm_i915_memory_region_info regions[]; +}; + +/** + * struct prelim_drm_i915_query_distance_info + * + * Distance info query returns the distance of given (class, instance) + * engine to the memory region id passed by the user. If the distance + * is -1 it means region is unreachable. + */ +struct prelim_drm_i915_query_distance_info { + /** Engine for which distance is queried */ + struct i915_engine_class_instance engine; + + /** Memory region to be used */ + struct prelim_drm_i915_gem_memory_class_instance region; + + /** Distance to region from engine */ + __s32 distance; + + /** Must be zero */ + __u32 rsvd[3]; +}; + +/** + * struct prelim_drm_i915_query_cs_cycles + * + * The query returns the command streamer cycles and the frequency that can be + * used to calculate the command streamer timestamp. In addition the query + * returns the cpu timestamp that indicates when the command streamer cycle + * count was captured. + */ +struct prelim_drm_i915_query_cs_cycles { + /** Engine for which command streamer cycles is queried. */ + struct i915_engine_class_instance engine; + + /** Must be zero. */ + __u32 flags; + + /** + * Command streamer cycles as read from the command streamer + * register at 0x358 offset. + */ + __u64 cs_cycles; + + /** Frequency of the cs cycles in Hz. */ + __u64 cs_frequency; + + /** CPU timestamp in nanoseconds. */ + __u64 cpu_timestamp; + + /** + * Reference clock id for CPU timestamp. For definition, see + * clock_gettime(2) and perf_event_open(2). Supported clock ids are + * CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, + * CLOCK_TAI. + */ + __s32 clockid; + + /** Must be zero. */ + __u32 rsvd; +}; + +/** + * prelim_struct drm_i915_query_hw_ip_version + * + * Hardware IP version (i.e., architecture generation) associated with a + * specific engine. + */ +struct prelim_drm_i915_query_hw_ip_version { + /** Engine to query HW IP version for */ + struct i915_engine_class_instance engine; + + __u8 flags; /* MBZ */ + + /** Architecture version */ + __u8 arch; + + /** Architecture release id */ + __u8 release; + + /** Stepping (e.g., A0, A1, B0, etc.) */ + __u8 stepping; +}; + +/** + * struct prelim_drm_i915_query_fabric_info + * + * With the given fabric id, query fabric info wrt the device. + * Higher bandwidth is better. 0 means no fabric. + * Latency is averaged latency (from all paths) + * + * fabric_id can be obtained from + * /sys/class/drm/cardx/device/iaf.y/iaf_fabric_id + * Bandwidth is in Gigabits per second (max value of 8 * 4 * 90) + * 8 possible ports + * 4 lanes max per port + * 90 gigabits per lane + * Latency is in tenths of path length. 10 == 1 fabric link between src and dst + * POR is max 1 link (zero hops). + */ +struct prelim_drm_i915_query_fabric_info { + __u32 fabric_id; + __u16 bandwidth; + __u16 latency; +}; + +/** + * struct prelim_drm_i915_engine_info + * + * Describes one engine and it's capabilities as known to the driver. + */ +struct prelim_drm_i915_engine_info { + /** Engine class and instance. */ + struct i915_engine_class_instance engine; + + /** + * SW defined id that identifies the OA unit associated with this + * engine. A value of U32_MAX means engine is not supported by OA. All + * other values are valid and can be used to group engines into the + * associated OA unit. + */ + __u32 oa_unit_id; + + /** Engine flags. */ + __u64 flags; +#define PRELIM_I915_ENGINE_INFO_HAS_KNOWN_CAPABILITIES (1ull << 63) +#define PRELIM_I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1ull << 62) +#define PRELIM_I915_ENGINE_INFO_HAS_OA_UNIT_ID (1ull << 61) + + /** Capabilities of this engine. */ + __u64 capabilities; +#define PRELIM_I915_RENDER_CLASS_CAPABILITY_3D (1ull << 63) +#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) +#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) +#define PRELIM_I915_VIDEO_CLASS_CAPABILITY_VDENC (1ull << 63) +#define I915_VIDEO_CLASS_CAPABILITY_VDENC (1 << 2) +#define PRELIM_I915_COPY_CLASS_CAP_BLOCK_COPY (1ull << 63) + /* + * The following are capabilties of the copy engines, while all engines + * are functionally same, but engines with cap PRELIM_I915_COPY_CLASS_CAP_SATURATE_LINK + * can saturate pcie and scaleup links faster than engines with + * PRELIM_I915_COPY_CLASS_CAP_SATURATE_PCIE. Engines having the capability of + * PRELIM_I915_COPY_CLASS_CAP_SATURATE_LMEM can operate at HBM speeds. + */ +#define PRELIM_I915_COPY_CLASS_CAP_SATURATE_PCIE (1ull << 62) +#define PRELIM_I915_COPY_CLASS_CAP_SATURATE_LINK (1ull << 61) +#define PRELIM_I915_COPY_CLASS_CAP_SATURATE_LMEM (1ull << 60) + + /** All known capabilities for this engine class. */ + __u64 known_capabilities; + + /** Logical engine instance */ + __u16 logical_instance; + + /** Reserved fields. */ + __u16 rsvd1[3]; + __u64 rsvd2[2]; +}; + +/** + * struct drm_i915_query_engine_info + * + * Engine info query enumerates all engines known to the driver by filling in + * an array of struct drm_i915_engine_info structures. + */ +struct prelim_drm_i915_query_engine_info { + /** Number of struct drm_i915_engine_info structs following. */ + __u32 num_engines; + + /** MBZ */ + __u32 rsvd[3]; + + /** Marker for drm_i915_engine_info structures. */ + struct prelim_drm_i915_engine_info engines[]; +}; + +/** + * struct prelim_drm_i915_gem_vm_bind + * + * VA to object/buffer mapping to [un]bind. + * + * NOTE: + * A vm_bind will hold a reference on the BO which is released + * during corresponding vm_unbind or while closing the VM. + * Hence closing the BO alone will not ensure BO is released. + */ +struct prelim_drm_i915_gem_vm_bind { + /** vm to [un]bind **/ + __u32 vm_id; + + /** BO handle or file descriptor. Set 'fd' to -1 for system pages **/ + union { + __u32 handle; + __s32 fd; + }; + + /** VA start to [un]bind **/ + __u64 start; + + /** Offset in object to [un]bind **/ + __u64 offset; + + /** VA length to [un]bind **/ + __u64 length; + + /** Flags **/ + __u64 flags; +#define PRELIM_I915_GEM_VM_BIND_IMMEDIATE (1ull << 63) +#define PRELIM_I915_GEM_VM_BIND_READONLY (1ull << 62) +#define PRELIM_I915_GEM_VM_BIND_CAPTURE (1ull << 61) +#define PRELIM_I915_GEM_VM_BIND_MAKE_RESIDENT (1ull << 60) +#define PRELIM_I915_GEM_VM_BIND_FD (1ull << 59) + + __u64 extensions; +}; + +/** + * struct prelim_drm_i915_gem_vm_advise + * + * Set attribute (hint) for an address range or whole buffer object. + * + * To apply attribute to whole buffer object, specify: handle + * To apply attribute to address range, specify: vm_id, start, and length. + */ +struct prelim_drm_i915_gem_vm_advise { + /** vm that contains address range (specified with start, length) */ + __u32 vm_id; + + /** BO handle to apply hint */ + __u32 handle; + + /** VA start of address range to apply hint */ + __u64 start; + + /** Length of range to apply attribute */ + __u64 length; + + /** + * Attributes to apply to address range or buffer object + * + * ATOMIC_SYSTEM + * inform that atomic access is enabled for both CPU and GPU. + * For some platforms, this may be required for correctness + * and this hint will influence migration policy. + * ATOMIC_DEVICE + * inform that atomic access is enabled for GPU devices. For + * some platforms, this may be required for correctness and + * this hint will influence migration policy. + * ATOMIC_NONE + * clears above ATOMIC_SYSTEM / ATOMIC_DEVICE hint. + * PREFERRED_LOCATION + * sets the preferred memory class and instance for this object's + * backing store. This is a hint only and not guaranteed to be + * honored. It is an error to choose a memory region that was not + * part of the original set of placements for the GEM object. + * If choosing a preferred location that is in conflict with the + * use of ATOMIC_SYSTEM or ATOMIC_DEVICE, the atomic hint will + * always be honored first. + * To clear the current preferred location, specify memory class + * as I915_MEMORY_CLASS_NONE. + */ + __u32 attribute; +#define PRELIM_I915_VM_ADVISE (1 << 16) +#define PRELIM_I915_VM_ADVISE_ATOMIC_NONE (PRELIM_I915_VM_ADVISE | 0) +#define PRELIM_I915_VM_ADVISE_ATOMIC_SYSTEM (PRELIM_I915_VM_ADVISE | 1) +#define PRELIM_I915_VM_ADVISE_ATOMIC_DEVICE (PRELIM_I915_VM_ADVISE | 2) +#define PRELIM_I915_VM_ADVISE_PREFERRED_LOCATION (PRELIM_I915_VM_ADVISE | 3) + + /** Preferred location (memory region) for object backing */ + struct prelim_drm_i915_gem_memory_class_instance region; + + __u32 rsvd[2]; +}; + +/** + * struct prelim_drm_i915_gem_wait_user_fence + * + * Wait on user fence. User fence can be woken up either by, + * 1. GPU context indicated by 'ctx_id', or, + * 2. Kerrnel driver async worker upon PRELIM_I915_UFENCE_WAIT_SOFT. + * 'ctx_id' is ignored when this flag is set. + * + * Wakeup when below condition is true. + * (*addr & MASK) OP (VALUE & MASK) + * + */ +struct prelim_drm_i915_gem_wait_user_fence { + __u64 extensions; + __u64 addr; + __u32 ctx_id; + __u16 op; +#define PRELIM_I915_UFENCE (1 << 8) +#define PRELIM_I915_UFENCE_WAIT_EQ (PRELIM_I915_UFENCE | 0) +#define PRELIM_I915_UFENCE_WAIT_NEQ (PRELIM_I915_UFENCE | 1) +#define PRELIM_I915_UFENCE_WAIT_GT (PRELIM_I915_UFENCE | 2) +#define PRELIM_I915_UFENCE_WAIT_GTE (PRELIM_I915_UFENCE | 3) +#define PRELIM_I915_UFENCE_WAIT_LT (PRELIM_I915_UFENCE | 4) +#define PRELIM_I915_UFENCE_WAIT_LTE (PRELIM_I915_UFENCE | 5) +#define PRELIM_I915_UFENCE_WAIT_BEFORE (PRELIM_I915_UFENCE | 6) +#define PRELIM_I915_UFENCE_WAIT_AFTER (PRELIM_I915_UFENCE | 7) + __u16 flags; +#define PRELIM_I915_UFENCE_WAIT_SOFT (1 << 15) +#define PRELIM_I915_UFENCE_WAIT_ABSTIME (1 << 14) + __u64 value; + __u64 mask; +#define PRELIM_I915_UFENCE_WAIT_U8 0xffu +#define PRELIM_I915_UFENCE_WAIT_U16 0xffffu +#define PRELIM_I915_UFENCE_WAIT_U32 0xfffffffful +#define PRELIM_I915_UFENCE_WAIT_U64 0xffffffffffffffffull + __s64 timeout; +}; + +struct prelim_drm_i915_vm_bind_ext_sync_fence { +#define PRELIM_I915_VM_BIND_EXT_SYNC_FENCE (PRELIM_I915_USER_EXT | 0) + struct i915_user_extension base; + __u64 addr; + __u64 val; +}; + +struct prelim_drm_i915_gem_vm_region_ext { +#define PRELIM_I915_GEM_VM_CONTROL_EXT_REGION (PRELIM_I915_USER_EXT | 0) + struct i915_user_extension base; + /* memory region: to find gt to create vm on */ + struct prelim_drm_i915_gem_memory_class_instance region; + __u32 pad; +}; + +struct prelim_drm_i915_gem_vm_control { +#define PRELIM_I915_VM_CREATE_FLAGS_DISABLE_SCRATCH (1 << 16) +#define PRELIM_I915_VM_CREATE_FLAGS_ENABLE_PAGE_FAULT (1 << 17) +#define PRELIM_I915_VM_CREATE_FLAGS_UNKNOWN (~(GENMASK(17, 16))) +}; + +struct prelim_drm_i915_vm_bind_ext_set_pat { +#define PRELIM_I915_VM_BIND_EXT_SET_PAT (PRELIM_I915_USER_EXT | 2) + struct i915_user_extension base; + __u64 pat_index; +}; + +/** + * struct prelim_drm_i915_gem_clos_reserve + * + * Allows clients to request reservation of one free CLOS, to use in subsequent + * Cache Reservations. + * + */ +struct prelim_drm_i915_gem_clos_reserve { + __u16 clos_index; + __u16 pad16; +}; + +/** + * struct prelim_drm_i915_gem_clos_free + * + * Free off a previously reserved CLOS set. Any corresponding Cache Reservations + * that are active for the CLOS are automatically dropped and returned to the + * Shared set. + * + * The clos_index indicates the CLOS set which is being released and must + * correspond to a CLOS index previously reserved. + * + */ +struct prelim_drm_i915_gem_clos_free { + __u16 clos_index; + __u16 pad16; +}; + +/** + * struct prelim_drm_i915_gem_cache_reserve + * + * Allows clients to request, or release, reservation of one or more cache ways, + * within a previously reserved CLOS set. + * + * If num_ways = 0, i915 will drop any existing Reservation for the specified + * clos_index and cache_level. The requested clos_index and cache_level Waymasks + * will then track the Shared set once again. + * + * Otherwise, the requested number of Ways will be removed from the Shared set + * for the requested cache level, and assigned to the Cache and CLOS specified + * by cache_level/clos_index. + * + */ +struct prelim_drm_i915_gem_cache_reserve { + __u16 clos_index; + __u16 cache_level; // e.g. 3 for L3 + __u16 num_ways; + __u16 pad16; +}; + +/** + * struct prelim_drm_i915_gem_vm_prefetch + * + * Prefetch an address range to a memory region. + */ +struct prelim_drm_i915_gem_vm_prefetch { + /** Memory region to prefetch to **/ + __u32 region; + + /** Reserved **/ + __u32 rsvd; + + /** VA start to prefetch **/ + __u64 start; + + /** VA length to prefetch **/ + __u64 length; +}; + +struct prelim_drm_i915_gem_vm_param { + __u32 vm_id; + __u32 rsvd; + +#define PRELIM_I915_VM_PARAM (1ull << 63) +#define PRELIM_I915_GEM_VM_PARAM_SVM (1 << 16) + __u64 param; + + __u64 value; +}; + +#endif /* __I915_DRM_PRELIM_H__ */ diff --git a/third_party/uapi/prelim/drm/intel_hwconfig_types.h b/third_party/uapi/prelim/drm/intel_hwconfig_types.h new file mode 100644 index 0000000000..bb2abb53e9 --- /dev/null +++ b/third_party/uapi/prelim/drm/intel_hwconfig_types.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ + +#ifndef _INTEL_HWCONFIG_TYPES_H_ +#define _INTEL_HWCONFIG_TYPES_H_ + +/** + * enum intel_hwconfig - Global definition of hwconfig table attributes + * + * Intel devices provide a KLV (Key/Length/Value) table containing + * the static hardware configuration for that platform. + * This enum defines the current attribute keys for this KLV. + */ +enum intel_hwconfig { + INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1, + INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */ + INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */ + INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */ + INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */ + INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */ + INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */ + INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */ + INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */ + INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */ + INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */ + INTEL_HWCONFIG_CACHE_TYPES, /* 12 */ + INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */ + INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */ + INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */ + INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */ + INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */ + INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */ + INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */ + INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */ + INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */ + INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */ + INTEL_HWCONFIG_MAX_RCS, /* 23 */ + INTEL_HWCONFIG_MAX_CCS, /* 24 */ + INTEL_HWCONFIG_MAX_VCS, /* 25 */ + INTEL_HWCONFIG_MAX_VECS, /* 26 */ + INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */ + INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */ + INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */ + INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */ + INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */ + INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */ + INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */ + INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */ + INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */ + INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */ + INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */ + INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */ + INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */ + INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */ + INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */ + INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */ + INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */ + INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */ + INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */ + INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */ + INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */ + INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */ + INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */ + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */ + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */ + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */ + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */ + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */ + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */ + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */ + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */ + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */ + INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */ + INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */ + INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */ + INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */ + INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */ + INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */ + INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */ + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */ + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */ + INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */ + INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */ + INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */ + INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */ + INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */ + INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */ + __INTEL_HWCONFIG_LIMIT +}; + +enum { + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0, + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5, +}; + +#define INTEL_HWCONFIG_CACHE_TYPE_L3 BIT(0) +#define INTEL_HWCONFIG_CACHE_TYPE_LLC BIT(1) +#define INTEL_HWCONFIG_CACHE_TYPE_EDRAM BIT(2) + +#endif /* _INTEL_HWCONFIG_TYPES_H_ */