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Add PhysicalAddressAllocator to PageTables

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- Allocator is responsible for physical pages allocation

Change-Id: I3a9034c87292484da8f4f0eb1d1e0cc5122a4d8a
This commit is contained in:
Hoppe, Mateusz
2018-09-11 14:45:43 +02:00
committed by sys_ocldev
parent 8df30ceac1
commit 610eda5ad1
17 changed files with 366 additions and 178 deletions
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3
runtime/command_stream/aub_command_stream_receiver_hw.h
View File

@@ -101,8 +101,9 @@ class AUBCommandStreamReceiverHw : public CommandStreamReceiverHw<GfxFamily> {
uint32_t aubDeviceId;
bool standalone;
PhysicalAddressAllocator physicalAddressAllocator;
std::unique_ptr<TypeSelector<PML4, PDPE, sizeof(void *) == 8>::type> ppgtt;
PDPE ggtt;
std::unique_ptr<PDPE> ggtt;
// remap CPU VA -> GGTT VA
AddressMapper gttRemap;

26
runtime/command_stream/aub_command_stream_receiver_hw.inl
View File

@@ -44,7 +44,8 @@ AUBCommandStreamReceiverHw<GfxFamily>::AUBCommandStreamReceiverHw(const Hardware
stream(std::make_unique<AUBCommandStreamReceiver::AubFileStream>()),
subCaptureManager(std::make_unique<AubSubCaptureManager>(fileName)),
standalone(standalone),
ppgtt(std::make_unique<TypeSelector<PML4, PDPE, sizeof(void *) == 8>::type>()) {
ppgtt(std::make_unique<TypeSelector<PML4, PDPE, sizeof(void *) == 8>::type>(&physicalAddressAllocator)),
ggtt(std::make_unique<PDPE>(&physicalAddressAllocator)) {
this->dispatchMode = DispatchMode::BatchedDispatch;
if (DebugManager.flags.CsrDispatchMode.get()) {
this->dispatchMode = (DispatchMode)DebugManager.flags.CsrDispatchMode.get();
@@ -138,7 +139,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::initializeEngine(EngineType engineTy
const size_t alignHWSP = 0x1000;
engineInfo.pGlobalHWStatusPage = alignedMalloc(sizeHWSP, alignHWSP);
engineInfo.ggttHWSP = gttRemap.map(engineInfo.pGlobalHWStatusPage, sizeHWSP);
auto physHWSP = ggtt.map(engineInfo.ggttHWSP, sizeHWSP);
auto physHWSP = ggtt->map(engineInfo.ggttHWSP, sizeHWSP, PageTableHelper::memoryBankNotSpecified);
// Write our GHWSP
{
@@ -169,7 +170,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::initializeEngine(EngineType engineTy
const size_t alignRingBuffer = 0x1000;
engineInfo.pRingBuffer = alignedMalloc(engineInfo.sizeRingBuffer, alignRingBuffer);
engineInfo.ggttRingBuffer = gttRemap.map(engineInfo.pRingBuffer, engineInfo.sizeRingBuffer);
auto physRingBuffer = ggtt.map(engineInfo.ggttRingBuffer, engineInfo.sizeRingBuffer);
auto physRingBuffer = ggtt->map(engineInfo.ggttRingBuffer, engineInfo.sizeRingBuffer, PageTableHelper::memoryBankNotSpecified);
{
std::ostringstream str;
@@ -197,7 +198,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::initializeEngine(EngineType engineTy
// Write our LRCA
{
engineInfo.ggttLRCA = gttRemap.map(engineInfo.pLRCA, sizeLRCA);
auto lrcAddressPhys = ggtt.map(engineInfo.ggttLRCA, sizeLRCA);
auto lrcAddressPhys = ggtt->map(engineInfo.ggttLRCA, sizeLRCA, PageTableHelper::memoryBankNotSpecified);
{
std::ostringstream str;
@@ -292,7 +293,7 @@ FlushStamp AUBCommandStreamReceiverHw<GfxFamily>::flush(BatchBuffer &batchBuffer
stream->addComment(str.str().c_str());
}
auto physBatchBuffer = ppgtt->map(static_cast<uintptr_t>(batchBufferGpuAddress), sizeBatchBuffer);
auto physBatchBuffer = ppgtt->map(static_cast<uintptr_t>(batchBufferGpuAddress), sizeBatchBuffer, PageTableHelper::getMemoryBankIndex(*batchBuffer.commandBufferAllocation));
AUB::reserveAddressPPGTT(*stream, static_cast<uintptr_t>(batchBufferGpuAddress), sizeBatchBuffer, physBatchBuffer,
getPPGTTAdditionalBits(batchBuffer.commandBufferAllocation));
@@ -343,7 +344,7 @@ FlushStamp AUBCommandStreamReceiverHw<GfxFamily>::flush(BatchBuffer &batchBuffer
auto sizeToWrap = engineInfo.sizeRingBuffer - engineInfo.tailRingBuffer;
memset(pTail, 0, sizeToWrap);
// write remaining ring
auto physDumpStart = ggtt.map(ggttTail, sizeToWrap);
auto physDumpStart = ggtt->map(ggttTail, sizeToWrap, PageTableHelper::memoryBankNotSpecified);
AUB::addMemoryWrite(
*stream,
physDumpStart,
@@ -393,7 +394,7 @@ FlushStamp AUBCommandStreamReceiverHw<GfxFamily>::flush(BatchBuffer &batchBuffer
stream->addComment(str.str().c_str());
}
auto physDumpStart = ggtt.map(ggttDumpStart, dumpLength);
auto physDumpStart = ggtt->map(ggttDumpStart, dumpLength, PageTableHelper::memoryBankNotSpecified);
AUB::addMemoryWrite(
*stream,
physDumpStart,
@@ -409,7 +410,7 @@ FlushStamp AUBCommandStreamReceiverHw<GfxFamily>::flush(BatchBuffer &batchBuffer
stream->addComment(str.str().c_str());
}
auto physLRCA = ggtt.map(engineInfo.ggttLRCA, sizeof(engineInfo.tailRingBuffer));
auto physLRCA = ggtt->map(engineInfo.ggttLRCA, sizeof(engineInfo.tailRingBuffer), PageTableHelper::memoryBankNotSpecified);
AUB::addMemoryWrite(
*stream,
physLRCA + 0x101c,
@@ -469,12 +470,12 @@ bool AUBCommandStreamReceiverHw<GfxFamily>::addPatchInfoComments() {
if (patchInfoData.sourceAllocation) {
allocationsMap.insert(std::pair<uint64_t, uint64_t>(patchInfoData.sourceAllocation,
ppgtt->map(static_cast<uintptr_t>(patchInfoData.sourceAllocation), 1)));
ppgtt->map(static_cast<uintptr_t>(patchInfoData.sourceAllocation), 1, PageTableHelper::memoryBankNotSpecified)));
}
if (patchInfoData.targetAllocation) {
allocationsMap.insert(std::pair<uint64_t, uintptr_t>(patchInfoData.targetAllocation,
ppgtt->map(static_cast<uintptr_t>(patchInfoData.targetAllocation), 1)));
ppgtt->map(static_cast<uintptr_t>(patchInfoData.targetAllocation), 1, PageTableHelper::memoryBankNotSpecified)));
}
}
bool result = stream->addComment(str.str().c_str());
@@ -560,7 +561,8 @@ bool AUBCommandStreamReceiverHw<GfxFamily>::writeMemory(GraphicsAllocation &gfxA
PageWalker walker = [&](uint64_t physAddress, size_t size, size_t offset) {
AUB::reserveAddressGGTTAndWriteMmeory(*stream, static_cast<uintptr_t>(gpuAddress), cpuAddress, physAddress, size, offset, getPPGTTAdditionalBits(&gfxAllocation));
};
ppgtt->pageWalk(static_cast<uintptr_t>(gpuAddress), size, 0, walker);
ppgtt->pageWalk(static_cast<uintptr_t>(gpuAddress), size, 0, walker, PageTableHelper::getMemoryBankIndex(gfxAllocation));
if (gfxAllocation.isLocked()) {
this->getMemoryManager()->unlockResource(&gfxAllocation);
@@ -665,7 +667,7 @@ void AUBCommandStreamReceiverHw<GfxFamily>::addGUCStartMessage(uint64_t batchBuf
miBatchBufferStart->setBatchBufferStartAddressGraphicsaddress472(AUB::ptrToPPGTT(buffer.get()));
miBatchBufferStart->setAddressSpaceIndicator(MI_BATCH_BUFFER_START::ADDRESS_SPACE_INDICATOR_PPGTT);
auto physBufferAddres = ppgtt->map(reinterpret_cast<uintptr_t>(buffer.get()), bufferSize);
auto physBufferAddres = ppgtt->map(reinterpret_cast<uintptr_t>(buffer.get()), bufferSize, PageTableHelper::memoryBankNotSpecified);
AUB::reserveAddressPPGTT(*stream, reinterpret_cast<uintptr_t>(buffer.get()), bufferSize, physBufferAddres, getPPGTTAdditionalBits(linearStream.getGraphicsAllocation()));
AUB::addMemoryWrite(

5
runtime/command_stream/tbx_command_stream_receiver_hw.h
View File

@@ -93,8 +93,9 @@ class TbxCommandStreamReceiverHw : public CommandStreamReceiverHw<GfxFamily> {
uint32_t aubDeviceId;
bool streamInitialized = false;
TypeSelector<PML4, PDPE, sizeof(void *) == 8>::type ppgtt;
PDPE ggtt;
PhysicalAddressAllocator physicalAddressAllocator;
std::unique_ptr<TypeSelector<PML4, PDPE, sizeof(void *) == 8>::type> ppgtt;
std::unique_ptr<PDPE> ggtt;
// remap CPU VA -> GGTT VA
AddressMapper gttRemap;

23
runtime/command_stream/tbx_command_stream_receiver_hw.inl
View File

@@ -35,7 +35,9 @@ namespace OCLRT {
template <typename GfxFamily>
TbxCommandStreamReceiverHw<GfxFamily>::TbxCommandStreamReceiverHw(const HardwareInfo &hwInfoIn,
ExecutionEnvironment &executionEnvironment)
: BaseClass(hwInfoIn, executionEnvironment) {
: BaseClass(hwInfoIn, executionEnvironment),
ppgtt(std::make_unique<TypeSelector<PML4, PDPE, sizeof(void *) == 8>::type>(&physicalAddressAllocator)),
ggtt(std::make_unique<PDPE>(&physicalAddressAllocator)) {
for (auto &engineInfo : engineInfoTable) {
engineInfo.pLRCA = nullptr;
engineInfo.ggttLRCA = 0u;
@@ -109,7 +111,7 @@ void TbxCommandStreamReceiverHw<GfxFamily>::initializeEngine(EngineType engineTy
const size_t alignHWSP = 0x1000;
engineInfo.pGlobalHWStatusPage = alignedMalloc(sizeHWSP, alignHWSP);
engineInfo.ggttHWSP = gttRemap.map(engineInfo.pGlobalHWStatusPage, sizeHWSP);
auto physHWSP = ggtt.map(engineInfo.ggttHWSP, sizeHWSP);
auto physHWSP = ggtt->map(engineInfo.ggttHWSP, sizeHWSP, PageTableHelper::memoryBankNotSpecified);
// Write our GHWSP
AubGTTData data = {0};
@@ -134,7 +136,7 @@ void TbxCommandStreamReceiverHw<GfxFamily>::initializeEngine(EngineType engineTy
const size_t alignRCS = 0x1000;
engineInfo.pRCS = alignedMalloc(engineInfo.sizeRCS, alignRCS);
engineInfo.ggttRCS = gttRemap.map(engineInfo.pRCS, engineInfo.sizeRCS);
auto physRCS = ggtt.map(engineInfo.ggttRCS, engineInfo.sizeRCS);
auto physRCS = ggtt->map(engineInfo.ggttRCS, engineInfo.sizeRCS, PageTableHelper::memoryBankNotSpecified);
AubGTTData data = {0};
getGTTData(reinterpret_cast<void *>(physRCS), data);
@@ -156,7 +158,7 @@ void TbxCommandStreamReceiverHw<GfxFamily>::initializeEngine(EngineType engineTy
// Write our LRCA
{
engineInfo.ggttLRCA = gttRemap.map(engineInfo.pLRCA, sizeLRCA);
auto lrcAddressPhys = ggtt.map(engineInfo.ggttLRCA, sizeLRCA);
auto lrcAddressPhys = ggtt->map(engineInfo.ggttLRCA, sizeLRCA, PageTableHelper::memoryBankNotSpecified);
AubGTTData data = {0};
getGTTData(reinterpret_cast<void *>(lrcAddressPhys), data);
@@ -206,7 +208,7 @@ FlushStamp TbxCommandStreamReceiverHw<GfxFamily>::flush(BatchBuffer &batchBuffer
DEBUG_BREAK_IF(currentOffset < batchBuffer.startOffset);
auto sizeBatchBuffer = currentOffset - batchBuffer.startOffset;
{
auto physBatchBuffer = ppgtt.map(reinterpret_cast<uintptr_t>(pBatchBuffer), sizeBatchBuffer);
auto physBatchBuffer = ppgtt->map(reinterpret_cast<uintptr_t>(pBatchBuffer), sizeBatchBuffer, PageTableHelper::getMemoryBankIndex(*batchBuffer.commandBufferAllocation));
AUB::reserveAddressPPGTT(stream, reinterpret_cast<uintptr_t>(pBatchBuffer), sizeBatchBuffer, physBatchBuffer, getPPGTTAdditionalBits(batchBuffer.commandBufferAllocation));
AUB::addMemoryWrite(
@@ -240,7 +242,7 @@ FlushStamp TbxCommandStreamReceiverHw<GfxFamily>::flush(BatchBuffer &batchBuffer
auto sizeToWrap = engineInfo.sizeRCS - engineInfo.tailRCS;
memset(pTail, 0, sizeToWrap);
// write remaining ring
auto physDumpStart = ggtt.map(ggttTail, sizeToWrap);
auto physDumpStart = ggtt->map(ggttTail, sizeToWrap, PageTableHelper::memoryBankNotSpecified);
AUB::addMemoryWrite(
stream,
physDumpStart,
@@ -280,7 +282,7 @@ FlushStamp TbxCommandStreamReceiverHw<GfxFamily>::flush(BatchBuffer &batchBuffer
auto dumpLength = engineInfo.tailRCS - previousTail;
// write RCS
auto physDumpStart = ggtt.map(ggttDumpStart, dumpLength);
auto physDumpStart = ggtt->map(ggttDumpStart, dumpLength, PageTableHelper::memoryBankNotSpecified);
AUB::addMemoryWrite(
stream,
physDumpStart,
@@ -290,7 +292,7 @@ FlushStamp TbxCommandStreamReceiverHw<GfxFamily>::flush(BatchBuffer &batchBuffer
AubMemDump::DataTypeHintValues::TraceCommandBuffer);
// update the RCS mmio tail in the LRCA
auto physLRCA = ggtt.map(engineInfo.ggttLRCA, sizeof(engineInfo.tailRCS));
auto physLRCA = ggtt->map(engineInfo.ggttLRCA, sizeof(engineInfo.tailRCS), PageTableHelper::memoryBankNotSpecified);
AUB::addMemoryWrite(
stream,
physLRCA + 0x101c,
@@ -359,8 +361,8 @@ bool TbxCommandStreamReceiverHw<GfxFamily>::writeMemory(GraphicsAllocation &gfxA
PageWalker walker = [&](uint64_t physAddress, size_t size, size_t offset) {
AUB::reserveAddressGGTTAndWriteMmeory(stream, static_cast<uintptr_t>(gpuAddress), cpuAddress, physAddress, size, offset, getPPGTTAdditionalBits(&gfxAllocation));
};
ppgtt.pageWalk(static_cast<uintptr_t>(gpuAddress), size, 0, walker);
ppgtt->pageWalk(static_cast<uintptr_t>(gpuAddress), size, 0, walker, PageTableHelper::getMemoryBankIndex(gfxAllocation));
return true;
}
@@ -386,8 +388,7 @@ void TbxCommandStreamReceiverHw<GfxFamily>::makeCoherent(GraphicsAllocation &gfx
DEBUG_BREAK_IF(offset > length);
stream.readMemory(physAddress, ptrOffset(cpuAddress, offset), size);
};
ppgtt.pageWalk(static_cast<uintptr_t>(gpuAddress), length, 0, walker);
ppgtt->pageWalk(static_cast<uintptr_t>(gpuAddress), length, 0, walker, PageTableHelper::getMemoryBankIndex(gfxAllocation));
}
}

1
runtime/memory_manager/CMakeLists.txt
View File

@@ -40,6 +40,7 @@ set(RUNTIME_SRCS_MEMORY_MANAGER
${CMAKE_CURRENT_SOURCE_DIR}/page_table.cpp
${CMAKE_CURRENT_SOURCE_DIR}/page_table.h
${CMAKE_CURRENT_SOURCE_DIR}/page_table.inl
${CMAKE_CURRENT_SOURCE_DIR}/physical_address_allocator.h
${CMAKE_CURRENT_SOURCE_DIR}/residency.h
${CMAKE_CURRENT_SOURCE_DIR}/residency.cpp
${CMAKE_CURRENT_SOURCE_DIR}/residency_container.h

15
runtime/memory_manager/page_table.cpp
View File

@@ -25,10 +25,7 @@
namespace OCLRT {
const uint32_t PTE::initialPage = 1;
std::atomic<uint32_t> PTE::nextPage(PTE::initialPage);
uintptr_t PTE::map(uintptr_t vm, size_t size) {
uintptr_t PTE::map(uintptr_t vm, size_t size, uint32_t memoryBank) {
const size_t shift = 12;
const uint32_t mask = (1 << bits) - 1;
size_t indexStart = (vm >> shift) & mask;
@@ -37,15 +34,15 @@ uintptr_t PTE::map(uintptr_t vm, size_t size) {
for (size_t index = indexStart; index <= indexEnd; index++) {
if (entries[index] == 0x0) {
uint64_t tmp = nextPage.fetch_add(1);
entries[index] = reinterpret_cast<void *>(tmp * pageSize | 0x1);
uint64_t tmp = allocator->reservePage(memoryBank);
entries[index] = reinterpret_cast<void *>(tmp | 0x1);
}
res = std::min(reinterpret_cast<uintptr_t>(entries[index]) & 0xfffffffeu, res);
}
return (res & ~0x1) + (vm & (pageSize - 1));
}
void PTE::pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker) {
void PTE::pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker, uint32_t memoryBank) {
static const uint32_t bits = 9;
const size_t shift = 12;
const uint32_t mask = (1 << bits) - 1;
@@ -56,8 +53,8 @@ void PTE::pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWal
for (size_t index = indexStart; index <= indexEnd; index++) {
if (entries[index] == 0x0) {
uint64_t tmp = nextPage.fetch_add(1);
entries[index] = reinterpret_cast<void *>(tmp * pageSize | 0x1);
uint64_t tmp = allocator->reservePage(memoryBank);
entries[index] = reinterpret_cast<void *>(tmp | 0x1);
}
res = reinterpret_cast<uintptr_t>(entries[index]) & 0xfffffffeu;

55
runtime/memory_manager/page_table.h
View File

@@ -22,6 +22,7 @@
#pragma once
#include "runtime/helpers/basic_math.h"
#include "runtime/memory_manager/physical_address_allocator.h"
#include <array>
#include <atomic>
@@ -32,17 +33,32 @@
namespace OCLRT {
class GraphicsAllocation;
class PageTableHelper {
public:
static uint32_t getMemoryBankIndex(GraphicsAllocation &allocation) {
return memoryBankNotSpecified;
}
static const uint32_t memoryBankNotSpecified = 0;
};
typedef std::function<void(uint64_t addr, size_t size, size_t offset)> PageWalker;
template <class T, uint32_t level, uint32_t bits = 9>
class PageTable {
public:
PageTable() {
PageTable(PhysicalAddressAllocator *physicalAddressAllocator) : allocator(physicalAddressAllocator) {
entries.fill(nullptr);
};
virtual ~PageTable();
virtual uintptr_t map(uintptr_t vm, size_t size);
virtual void pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker);
virtual ~PageTable() {
for (auto &e : entries)
delete e;
}
virtual uintptr_t map(uintptr_t vm, size_t size, uint32_t memoryBank);
virtual void pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker, uint32_t memoryBank);
static const size_t pageSize = 1 << 12;
static size_t getBits() {
@@ -51,26 +67,45 @@ class PageTable {
protected:
std::array<T *, 1 << bits> entries;
PhysicalAddressAllocator *allocator = nullptr;
};
template <>
inline PageTable<void, 0, 9>::~PageTable() {
}
class PTE : public PageTable<void, 0u> {
public:
uintptr_t map(uintptr_t vm, size_t size) override;
void pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker) override;
PTE(PhysicalAddressAllocator *physicalAddressAllocator) : PageTable<void, 0u>(physicalAddressAllocator) {}
uintptr_t map(uintptr_t vm, size_t size, uint32_t memoryBank) override;
void pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker, uint32_t memoryBank) override;
static const uint32_t level = 0;
static const uint32_t bits = 9;
static const uint32_t initialPage;
};
protected:
static std::atomic<uint32_t> nextPage;
};
class PDE : public PageTable<class PTE, 1> {
public:
PDE(PhysicalAddressAllocator *physicalAddressAllocator) : PageTable<class PTE, 1>(physicalAddressAllocator) {
}
};
class PDP : public PageTable<class PDE, 2> {
public:
PDP(PhysicalAddressAllocator *physicalAddressAllocator) : PageTable<class PDE, 2>(physicalAddressAllocator) {
}
};
class PML4 : public PageTable<class PDP, 3> {
public:
PML4(PhysicalAddressAllocator *physicalAddressAllocator) : PageTable<class PDP, 3>(physicalAddressAllocator) {
}
};
class PDPE : public PageTable<class PDE, 2, 2> {
public:
PDPE(PhysicalAddressAllocator *physicalAddressAllocator) : PageTable<class PDE, 2, 2>(physicalAddressAllocator) {
}
};
} // namespace OCLRT

27
runtime/memory_manager/page_table.inl
View File

@@ -23,7 +23,7 @@
namespace OCLRT {
template <>
inline uintptr_t PageTable<void, 0, 9>::map(uintptr_t vm, size_t size) {
inline uintptr_t PageTable<void, 0, 9>::map(uintptr_t vm, size_t size, uint32_t memoryBank) {
return 0;
}
@@ -33,15 +33,11 @@ inline size_t PageTable<void, 0, 9>::getBits() {
}
template <>
inline void PageTable<void, 0, 9>::pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker) {
}
template <>
inline PageTable<void, 0, 9>::~PageTable() {
inline void PageTable<void, 0, 9>::pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker, uint32_t memoryBank) {
}
template <class T, uint32_t level, uint32_t bits>
inline uintptr_t PageTable<T, level, bits>::map(uintptr_t vm, size_t size) {
inline uintptr_t PageTable<T, level, bits>::map(uintptr_t vm, size_t size, uint32_t memoryBank) {
const size_t shift = T::getBits() + 12;
const uintptr_t mask = (1 << bits) - 1;
size_t indexStart = (vm >> shift) & mask;
@@ -57,15 +53,15 @@ inline uintptr_t PageTable<T, level, bits>::map(uintptr_t vm, size_t size) {
vmEnd = std::min(vmEnd, maskedVm + size - 1);
if (entries[index] == nullptr) {
entries[index] = new T;
entries[index] = new T(allocator);
}
res = std::min((entries[index])->map(vmStart, vmEnd - vmStart + 1), res);
res = std::min((entries[index])->map(vmStart, vmEnd - vmStart + 1, memoryBank), res);
}
return res;
}
template <class T, uint32_t level, uint32_t bits>
inline void PageTable<T, level, bits>::pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker) {
inline void PageTable<T, level, bits>::pageWalk(uintptr_t vm, size_t size, size_t offset, PageWalker &pageWalker, uint32_t memoryBank) {
const size_t shift = T::getBits() + 12;
const uintptr_t mask = (1 << bits) - 1;
size_t indexStart = (vm >> shift) & mask;
@@ -80,18 +76,11 @@ inline void PageTable<T, level, bits>::pageWalk(uintptr_t vm, size_t size, size_
vmEnd = std::min(vmEnd, maskedVm + size - 1);
if (entries[index] == nullptr) {
entries[index] = new T;
entries[index] = new T(allocator);
}
entries[index]->pageWalk(vmStart, vmEnd - vmStart + 1, offset, pageWalker);
entries[index]->pageWalk(vmStart, vmEnd - vmStart + 1, offset, pageWalker, memoryBank);
offset += (vmEnd - vmStart + 1);
}
}
template <class T, uint32_t level, uint32_t bits>
inline PageTable<T, level, bits>::~PageTable() {
for (auto &e : entries)
delete e;
}
} // namespace OCLRT

46
runtime/memory_manager/physical_address_allocator.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* Copyright (c) 2018, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include "runtime/memory_manager/memory_constants.h"
#include <atomic>
namespace OCLRT {
class PhysicalAddressAllocator {
public:
PhysicalAddressAllocator() {
nextPageAddress.store(initialPageAddress);
};
~PhysicalAddressAllocator() = default;
uint64_t reservePage(uint32_t memoryBank) {
auto address = nextPageAddress.fetch_add(MemoryConstants::pageSize);
return address;
}
protected:
std::atomic<uint64_t> nextPageAddress;
const uint64_t initialPageAddress = 0x1000;
};
} // namespace OCLRT