Change event memory layout for multi tile capable platforms

Related-To: NEO-6811

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
This commit is contained in:
Zbigniew Zdanowicz
2022-04-04 19:07:08 +00:00
committed by Compute-Runtime-Automation
parent 9e1bd1005b
commit 616dd55789
23 changed files with 340 additions and 108 deletions

View File

@@ -38,20 +38,20 @@ class CommandEncodeStatesFixture : public DeviceFixture {
const void *pThreadGroupDimensions,
bool requiresUncachedMocs) {
EncodeDispatchKernelArgs args{
0, //eventAddress
device, //device
dispatchInterface, //dispatchInterface
pThreadGroupDimensions, //pThreadGroupDimensions
PreemptionMode::Disabled, //preemptionMode
1, //partitionCount
false, //isIndirect
false, //isPredicate
false, //isTimestampEvent
false, //L3FlushEnable
requiresUncachedMocs, //requiresUncachedMocs
false, //useGlobalAtomics
false, //isInternal
false //isCooperative
0, // eventAddress
device, // device
dispatchInterface, // dispatchInterface
pThreadGroupDimensions, // pThreadGroupDimensions
PreemptionMode::Disabled, // preemptionMode
1, // partitionCount
false, // isIndirect
false, // isPredicate
false, // isTimestampEvent
false, // L3FlushEnable
requiresUncachedMocs, // requiresUncachedMocs
false, // useGlobalAtomics
false, // isInternal
false // isCooperative
};
return args;