mirror of
https://github.com/intel/compute-runtime.git
synced 2026-01-04 15:53:45 +08:00
fix: correct sequence of estimates to get correct size for start command
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
This commit is contained in:
committed by
Compute-Runtime-Automation
parent
974e8ae63f
commit
6453a5ec31
@@ -329,8 +329,6 @@ CompletionStamp CommandStreamReceiverHw<GfxFamily>::flushImmediateTask(
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handleImmediateFlushStateBaseAddressState(dispatchFlags, flushData, device);
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handleImmediateFlushOneTimeContextInitState(dispatchFlags, flushData, device);
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handleImmediateFlushJumpToImmediate(flushData);
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bool stateCacheFlushRequired = device.getBindlessHeapsHelper() ? device.getBindlessHeapsHelper()->getStateDirtyForContext(getOsContext().getContextId()) : false;
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if (stateCacheFlushRequired) {
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flushData.estimatedSize += MemorySynchronizationCommands<GfxFamily>::getSizeForFullCacheFlush();
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@@ -340,6 +338,9 @@ CompletionStamp CommandStreamReceiverHw<GfxFamily>::flushImmediateTask(
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flushData.estimatedSize += MemorySynchronizationCommands<GfxFamily>::getSizeForInstructionCacheFlush();
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}
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// this must be the last call after all estimate size operations
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handleImmediateFlushJumpToImmediate(flushData);
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auto &csrCommandStream = getCS(flushData.estimatedSize);
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flushData.csrStartOffset = csrCommandStream.getUsed();
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2022-2023 Intel Corporation
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* Copyright (C) 2022-2024 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -17,7 +17,7 @@ void CommandStreamReceiverFixture::setUp() {
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DeviceFixture::setUp();
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commandStream.replaceBuffer(cmdBuffer, bufferSize);
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auto graphicsAllocation = new MockGraphicsAllocation(cmdBuffer, bufferSize);
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auto graphicsAllocation = new MockGraphicsAllocation(cmdBuffer, cmdBufferGpuAddress, bufferSize);
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commandStream.replaceGraphicsAllocation(graphicsAllocation);
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dsh.replaceBuffer(dshBuffer, bufferSize);
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2022-2023 Intel Corporation
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* Copyright (C) 2022-2024 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -17,6 +17,7 @@ struct CommandStreamReceiverFixture : public NEO::DeviceFixture {
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void setUp();
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void tearDown();
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static constexpr uint64_t cmdBufferGpuAddress = 0x10000;
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static constexpr size_t bufferSize = 1024;
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uint8_t cmdBuffer[bufferSize];
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uint8_t dshBuffer[bufferSize];
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@@ -5111,8 +5111,6 @@ HWTEST_F(CommandStreamReceiverHwTest, GivenDirtyFlagForContextInBindlessHelperWh
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bindlessHeapsHelperPtr->stateCacheDirtyForContext.set(commandStreamReceiver.getOsContext().getContextId());
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this->requiredStreamProperties.stateComputeMode.setPropertiesAll(false, GrfConfig::defaultGrfNumber, ThreadArbitrationPolicy::AgeBased, NEO::PreemptionMode::ThreadGroup);
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commandStreamReceiver.flushImmediateTask(commandStream, commandStream.getUsed(), immediateFlushTaskFlags, *pDevice);
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HardwareParse hwParserCsr;
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@@ -5128,6 +5126,51 @@ HWTEST_F(CommandStreamReceiverHwTest, GivenDirtyFlagForContextInBindlessHelperWh
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EXPECT_FALSE(bindlessHeapsHelperPtr->getStateDirtyForContext(commandStreamReceiver.getOsContext().getContextId()));
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}
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HWTEST_F(CommandStreamReceiverHwTest, GivenContextInitializedAndDirtyFlagForContextInBindlessHelperWhenFlushImmediateTaskCalledThenStateCacheInvalidateIsSentBeforeBbStartJumpingToImmediateBuffer) {
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using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL;
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using MI_BATCH_BUFFER_START = typename FamilyType::MI_BATCH_BUFFER_START;
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auto &commandStreamReceiver = pDevice->getUltCommandStreamReceiver<FamilyType>();
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// 1st flush, dispatch all required n-p state commands
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commandStreamReceiver.flushImmediateTask(commandStream, commandStream.getUsed(), immediateFlushTaskFlags, *pDevice);
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auto usedAfterFirstFlush = commandStreamReceiver.commandStream.getUsed();
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auto bindlessHeapsHelper = std::make_unique<MockBindlesHeapsHelper>(pDevice, pDevice->getNumGenericSubDevices() > 1);
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MockBindlesHeapsHelper *bindlessHeapsHelperPtr = bindlessHeapsHelper.get();
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pDevice->getExecutionEnvironment()->rootDeviceEnvironments[pDevice->getRootDeviceIndex()]->bindlessHeapsHelper.reset(bindlessHeapsHelper.release());
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bindlessHeapsHelperPtr->stateCacheDirtyForContext.set(commandStreamReceiver.getOsContext().getContextId());
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// only state cache flush is dispatched in dynamic preamble
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auto immediateBufferStartOffset = commandStream.getUsed();
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commandStreamReceiver.flushImmediateTask(commandStream, immediateBufferStartOffset, immediateFlushTaskFlags, *pDevice);
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HardwareParse hwParserCsr;
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hwParserCsr.parseCommands<FamilyType>(commandStreamReceiver.commandStream, usedAfterFirstFlush);
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auto cmdPtrIt = hwParserCsr.cmdList.begin();
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ASSERT_NE(hwParserCsr.cmdList.end(), cmdPtrIt);
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auto pipeControl = genCmdCast<PIPE_CONTROL *>(*cmdPtrIt);
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ASSERT_NE(nullptr, pipeControl);
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EXPECT_TRUE(pipeControl->getCommandStreamerStallEnable());
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EXPECT_TRUE(pipeControl->getStateCacheInvalidationEnable());
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EXPECT_TRUE(pipeControl->getTextureCacheInvalidationEnable());
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EXPECT_TRUE(pipeControl->getRenderTargetCacheFlushEnable());
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EXPECT_FALSE(bindlessHeapsHelperPtr->getStateDirtyForContext(commandStreamReceiver.getOsContext().getContextId()));
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cmdPtrIt++;
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ASSERT_NE(hwParserCsr.cmdList.end(), cmdPtrIt);
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auto bbStart = genCmdCast<MI_BATCH_BUFFER_START *>(*cmdPtrIt);
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ASSERT_NE(nullptr, bbStart);
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EXPECT_EQ(cmdBufferGpuAddress + immediateBufferStartOffset, bbStart->getBatchBufferStartAddress());
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}
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HWTEST_F(CommandStreamReceiverHwTest, givenRequiresInstructionCacheFlushWhenFlushImmediateThenInstructionCacheInvalidateEnableIsSent) {
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using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL;
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@@ -5137,8 +5180,6 @@ HWTEST_F(CommandStreamReceiverHwTest, givenRequiresInstructionCacheFlushWhenFlus
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}
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commandStreamReceiver.registerInstructionCacheFlush();
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this->requiredStreamProperties.stateComputeMode.setPropertiesAll(false, GrfConfig::defaultGrfNumber, ThreadArbitrationPolicy::AgeBased, NEO::PreemptionMode::ThreadGroup);
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commandStreamReceiver.flushImmediateTask(commandStream, commandStream.getUsed(), immediateFlushTaskFlags, *pDevice);
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HardwareParse hwParserCsr;
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@@ -5150,6 +5191,46 @@ HWTEST_F(CommandStreamReceiverHwTest, givenRequiresInstructionCacheFlushWhenFlus
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EXPECT_FALSE(commandStreamReceiver.requiresInstructionCacheFlush);
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}
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HWTEST_F(CommandStreamReceiverHwTest, givenContextInitializedAndRequiresInstructionCacheFlushWhenFlushImmediateThenInstructionCacheInvalidateEnableIsSentBeforeBbStartJumpingToImmediateBuffer) {
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using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL;
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using MI_BATCH_BUFFER_START = typename FamilyType::MI_BATCH_BUFFER_START;
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auto &commandStreamReceiver = pDevice->getUltCommandStreamReceiver<FamilyType>();
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if (commandStreamReceiver.heaplessStateInitialized) {
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GTEST_SKIP();
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}
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// 1st flush, dispatch all required n-p state commands
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commandStreamReceiver.flushImmediateTask(commandStream, commandStream.getUsed(), immediateFlushTaskFlags, *pDevice);
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auto usedAfterFirstFlush = commandStreamReceiver.commandStream.getUsed();
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commandStreamReceiver.registerInstructionCacheFlush();
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// only instruction cache flush is dispatched in dynamic preamble
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auto immediateBufferStartOffset = commandStream.getUsed();
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commandStreamReceiver.flushImmediateTask(commandStream, immediateBufferStartOffset, immediateFlushTaskFlags, *pDevice);
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HardwareParse hwParserCsr;
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hwParserCsr.parseCommands<FamilyType>(commandStreamReceiver.commandStream, usedAfterFirstFlush);
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auto cmdPtrIt = hwParserCsr.cmdList.begin();
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ASSERT_NE(hwParserCsr.cmdList.end(), cmdPtrIt);
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auto pipeControl = genCmdCast<PIPE_CONTROL *>(*cmdPtrIt);
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ASSERT_NE(nullptr, pipeControl);
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EXPECT_TRUE(pipeControl->getInstructionCacheInvalidateEnable());
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EXPECT_FALSE(commandStreamReceiver.requiresInstructionCacheFlush);
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cmdPtrIt++;
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ASSERT_NE(hwParserCsr.cmdList.end(), cmdPtrIt);
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auto bbStart = genCmdCast<MI_BATCH_BUFFER_START *>(*cmdPtrIt);
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ASSERT_NE(nullptr, bbStart);
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EXPECT_EQ(cmdBufferGpuAddress + immediateBufferStartOffset, bbStart->getBatchBufferStartAddress());
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}
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HWTEST_F(CommandStreamReceiverHwTest, GivenFlushIsBlockingWhenFlushTaskCalledThenExpectMonitorFenceFlagTrue) {
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auto &commandStreamReceiver = pDevice->getUltCommandStreamReceiver<FamilyType>();
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commandStreamReceiver.recordFlushedBatchBuffer = true;
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