mirror of
https://github.com/intel/compute-runtime.git
synced 2025-12-24 12:23:05 +08:00
Fixes for misaligned hostPtr enqueueReadWrite
- use getGpuAddress for BuiltinOpParams - fix read/writeImage Change-Id: I2e6e9a1d91871fa9f22851f31eb5a7b337b5aecc
This commit is contained in:
committed by
sys_ocldev
parent
3c59bae5a4
commit
64ff9d30b7
@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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*
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* SPDX-License-Identifier: MIT
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* SPDX-License-Identifier: MIT
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*
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*
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@@ -476,6 +476,7 @@ class BuiltInOp<HWFamily, EBuiltInOps::CopyBufferToImage3d> : public BuiltinDisp
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// Determine size of host ptr surface for residency purposes
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// Determine size of host ptr surface for residency purposes
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size_t hostPtrSize = operationParams.srcPtr ? Image::calculateHostPtrSize(region, srcRowPitch, srcSlicePitch, bytesPerPixel, dstImage->getImageDesc().image_type) : 0;
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size_t hostPtrSize = operationParams.srcPtr ? Image::calculateHostPtrSize(region, srcRowPitch, srcSlicePitch, bytesPerPixel, dstImage->getImageDesc().image_type) : 0;
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hostPtrSize += operationParams.srcOffset.x;
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// Set-up kernel
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// Set-up kernel
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auto bytesExponent = Math::log2(bytesPerPixel);
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auto bytesExponent = Math::log2(bytesPerPixel);
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@@ -562,6 +563,7 @@ class BuiltInOp<HWFamily, EBuiltInOps::CopyImage3dToBuffer> : public BuiltinDisp
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// Determine size of host ptr surface for residency purposes
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// Determine size of host ptr surface for residency purposes
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size_t hostPtrSize = operationParams.dstPtr ? Image::calculateHostPtrSize(region, dstRowPitch, dstSlicePitch, bytesPerPixel, srcImage->getImageDesc().image_type) : 0;
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size_t hostPtrSize = operationParams.dstPtr ? Image::calculateHostPtrSize(region, dstRowPitch, dstSlicePitch, bytesPerPixel, srcImage->getImageDesc().image_type) : 0;
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hostPtrSize += operationParams.dstOffset.x;
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// Set-up ISA
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// Set-up ISA
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auto bytesExponent = Math::log2(bytesPerPixel);
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auto bytesExponent = Math::log2(bytesPerPixel);
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@@ -88,13 +88,6 @@ cl_int CommandQueueHw<GfxFamily>::enqueueReadBuffer(
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BuiltInOwnershipWrapper builtInLock(builder, this->context);
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BuiltInOwnershipWrapper builtInLock(builder, this->context);
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void *dstPtr = ptr;
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void *dstPtr = ptr;
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void *alignedDstPtr = dstPtr;
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size_t dstPtrOffset = 0;
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if (!isAligned<4>(dstPtr)) {
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alignedDstPtr = alignDown(dstPtr, 4);
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dstPtrOffset = ptrDiff(dstPtr, alignedDstPtr);
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}
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MemObjSurface bufferSurf(buffer);
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MemObjSurface bufferSurf(buffer);
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HostPtrSurface hostPtrSurf(dstPtr, size);
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HostPtrSurface hostPtrSurf(dstPtr, size);
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@@ -105,8 +98,12 @@ cl_int CommandQueueHw<GfxFamily>::enqueueReadBuffer(
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if (!status) {
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if (!status) {
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return CL_OUT_OF_RESOURCES;
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return CL_OUT_OF_RESOURCES;
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}
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}
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dstPtr = reinterpret_cast<void *>(hostPtrSurf.getAllocation()->getGpuAddress());
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}
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}
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void *alignedDstPtr = alignDown(dstPtr, 4);
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size_t dstPtrOffset = ptrDiff(dstPtr, alignedDstPtr);
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BuiltinDispatchInfoBuilder::BuiltinOpParams dc;
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BuiltinDispatchInfoBuilder::BuiltinOpParams dc;
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dc.dstPtr = alignedDstPtr;
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dc.dstPtr = alignedDstPtr;
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dc.dstOffset = {dstPtrOffset, 0, 0};
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dc.dstOffset = {dstPtrOffset, 0, 0};
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@@ -80,7 +80,7 @@ cl_int CommandQueueHw<GfxFamily>::enqueueReadBufferRect(
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if (!status) {
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if (!status) {
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return CL_OUT_OF_RESOURCES;
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return CL_OUT_OF_RESOURCES;
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}
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}
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dstPtr = reinterpret_cast<void *>(hostPtrSurf.getAllocation()->getGpuAddressToPatch());
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dstPtr = reinterpret_cast<void *>(hostPtrSurf.getAllocation()->getGpuAddress());
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}
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}
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void *alignedDstPtr = alignDown(dstPtr, 4);
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void *alignedDstPtr = alignDown(dstPtr, 4);
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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*
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* SPDX-License-Identifier: MIT
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* SPDX-License-Identifier: MIT
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*
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*
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@@ -86,12 +86,16 @@ cl_int CommandQueueHw<GfxFamily>::enqueueReadImage(
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if (!status) {
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if (!status) {
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return CL_OUT_OF_RESOURCES;
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return CL_OUT_OF_RESOURCES;
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}
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}
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dstPtr = reinterpret_cast<void *>(hostPtrSurf.getAllocation()->getGpuAddressToPatch());
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dstPtr = reinterpret_cast<void *>(hostPtrSurf.getAllocation()->getGpuAddress());
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}
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}
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void *alignedDstPtr = alignDown(dstPtr, 4);
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size_t dstPtrOffset = ptrDiff(dstPtr, alignedDstPtr);
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BuiltinDispatchInfoBuilder::BuiltinOpParams dc;
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BuiltinDispatchInfoBuilder::BuiltinOpParams dc;
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dc.srcMemObj = srcImage;
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dc.srcMemObj = srcImage;
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dc.dstPtr = dstPtr;
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dc.dstPtr = alignedDstPtr;
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dc.dstOffset.x = dstPtrOffset;
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dc.srcOffset = origin;
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dc.srcOffset = origin;
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dc.size = region;
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dc.size = region;
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dc.srcRowPitch = inputRowPitch;
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dc.srcRowPitch = inputRowPitch;
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@@ -89,13 +89,6 @@ cl_int CommandQueueHw<GfxFamily>::enqueueWriteBuffer(
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BuiltInOwnershipWrapper builtInLock(builder, this->context);
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BuiltInOwnershipWrapper builtInLock(builder, this->context);
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void *srcPtr = const_cast<void *>(ptr);
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void *srcPtr = const_cast<void *>(ptr);
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void *alignedSrcPtr = srcPtr;
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size_t srcPtrOffset = 0;
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if (!isAligned<4>(srcPtr)) {
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alignedSrcPtr = alignDown(srcPtr, 4);
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srcPtrOffset = ptrDiff(srcPtr, alignedSrcPtr);
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}
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HostPtrSurface hostPtrSurf(srcPtr, size, true);
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HostPtrSurface hostPtrSurf(srcPtr, size, true);
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MemObjSurface bufferSurf(buffer);
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MemObjSurface bufferSurf(buffer);
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@@ -106,8 +99,12 @@ cl_int CommandQueueHw<GfxFamily>::enqueueWriteBuffer(
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if (!status) {
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if (!status) {
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return CL_OUT_OF_RESOURCES;
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return CL_OUT_OF_RESOURCES;
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}
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}
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srcPtr = reinterpret_cast<void *>(hostPtrSurf.getAllocation()->getGpuAddress());
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}
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}
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void *alignedSrcPtr = alignDown(srcPtr, 4);
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size_t srcPtrOffset = ptrDiff(srcPtr, alignedSrcPtr);
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BuiltinDispatchInfoBuilder::BuiltinOpParams dc;
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BuiltinDispatchInfoBuilder::BuiltinOpParams dc;
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dc.srcPtr = alignedSrcPtr;
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dc.srcPtr = alignedSrcPtr;
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dc.srcOffset = {srcPtrOffset, 0, 0};
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dc.srcOffset = {srcPtrOffset, 0, 0};
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@@ -79,7 +79,7 @@ cl_int CommandQueueHw<GfxFamily>::enqueueWriteBufferRect(
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if (!status) {
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if (!status) {
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return CL_OUT_OF_RESOURCES;
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return CL_OUT_OF_RESOURCES;
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}
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}
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srcPtr = reinterpret_cast<void *>(hostPtrSurf.getAllocation()->getGpuAddressToPatch());
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srcPtr = reinterpret_cast<void *>(hostPtrSurf.getAllocation()->getGpuAddress());
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}
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}
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void *alignedSrcPtr = alignDown(srcPtr, 4);
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void *alignedSrcPtr = alignDown(srcPtr, 4);
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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*
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* SPDX-License-Identifier: MIT
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* SPDX-License-Identifier: MIT
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*
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*
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@@ -80,11 +80,15 @@ cl_int CommandQueueHw<GfxFamily>::enqueueWriteImage(
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if (!status) {
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if (!status) {
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return CL_OUT_OF_RESOURCES;
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return CL_OUT_OF_RESOURCES;
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}
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}
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srcPtr = reinterpret_cast<void *>(hostPtrSurf.getAllocation()->getGpuAddressToPatch());
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srcPtr = reinterpret_cast<void *>(hostPtrSurf.getAllocation()->getGpuAddress());
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}
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}
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void *alignedSrcPtr = alignDown(srcPtr, 4);
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size_t srcPtrOffset = ptrDiff(srcPtr, alignedSrcPtr);
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BuiltinDispatchInfoBuilder::BuiltinOpParams dc;
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BuiltinDispatchInfoBuilder::BuiltinOpParams dc;
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dc.srcPtr = srcPtr;
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dc.srcPtr = alignedSrcPtr;
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dc.srcOffset.x = srcPtrOffset;
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dc.dstMemObj = dstImage;
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dc.dstMemObj = dstImage;
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dc.dstOffset = origin;
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dc.dstOffset = origin;
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dc.size = region;
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dc.size = region;
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@@ -18,6 +18,7 @@ target_sources(igdrcl_aub_tests PRIVATE
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_read_buffer_aub_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_read_buffer_aub_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_read_buffer_rect_aub_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_read_buffer_rect_aub_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_read_image_aub_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_read_image_aub_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_read_write_image_aub_fixture.h
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_verify_memory_buffer_aub_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_verify_memory_buffer_aub_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_verify_memory_image_aub_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_verify_memory_image_aub_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_with_timestamp_packet_aub_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/enqueue_with_timestamp_packet_aub_tests.cpp
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (C) 2017-2018 Intel Corporation
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* Copyright (C) 2017-2019 Intel Corporation
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*
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*
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* SPDX-License-Identifier: MIT
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* SPDX-License-Identifier: MIT
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*
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*
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@@ -12,6 +12,7 @@
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#include "runtime/mem_obj/image.h"
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#include "runtime/mem_obj/image.h"
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#include "runtime/memory_manager/os_agnostic_memory_manager.h"
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#include "runtime/memory_manager/os_agnostic_memory_manager.h"
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#include "unit_tests/aub_tests/command_queue/command_enqueue_fixture.h"
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#include "unit_tests/aub_tests/command_queue/command_enqueue_fixture.h"
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#include "unit_tests/aub_tests/command_queue/enqueue_read_write_image_aub_fixture.h"
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#include "unit_tests/mocks/mock_context.h"
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#include "unit_tests/mocks/mock_context.h"
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#include "test.h"
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#include "test.h"
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@@ -222,3 +223,19 @@ INSTANTIATE_TEST_CASE_P(
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::testing::Values( // channels
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::testing::Values( // channels
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CL_R, CL_RG, CL_RGBA),
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CL_R, CL_RG, CL_RGBA),
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::testing::ValuesIn(readImageParams)));
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::testing::ValuesIn(readImageParams)));
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using AUBReadImageUnaligned = AUBImageUnaligned;
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HWTEST_F(AUBReadImageUnaligned, misalignedHostPtr) {
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const std::vector<size_t> pixelSizes = {1, 2, 4};
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const std::vector<size_t> offsets = {0, 1, 2, 3};
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const std::vector<size_t> sizes = {3, 2, 1};
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for (auto pixelSize : pixelSizes) {
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for (auto offset : offsets) {
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for (auto size : sizes) {
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testReadImageUnaligned<FamilyType>(offset, size, pixelSize);
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}
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}
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}
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}
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@@ -0,0 +1,211 @@
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/*
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* Copyright (C) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "runtime/helpers/aligned_memory.h"
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#include "runtime/helpers/ptr_math.h"
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#include "runtime/mem_obj/image.h"
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#include "unit_tests/aub_tests/command_queue/command_enqueue_fixture.h"
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#include "unit_tests/helpers/debug_manager_state_restore.h"
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#include "unit_tests/mocks/mock_context.h"
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#include "test.h"
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using namespace OCLRT;
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struct AUBImageUnaligned
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: public CommandEnqueueAUBFixture,
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public ::testing::Test {
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void SetUp() override {
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CommandEnqueueAUBFixture::SetUp();
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}
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void TearDown() override {
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CommandEnqueueAUBFixture::TearDown();
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}
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template <typename FamilyType>
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void testReadImageUnaligned(size_t offset, size_t size, size_t pixelSize) {
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MockContext context(&pCmdQ->getDevice());
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char srcMemory[] = "_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnoprstuwxyz";
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const auto bufferSize = sizeof(srcMemory) - 1;
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char *imageMemory = &srcMemory[1]; //ensure non cacheline-aligned hostPtr to create non-zerocopy image
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void *dstMemory = alignedMalloc(bufferSize, MemoryConstants::pageSize);
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memset(dstMemory, 0, bufferSize);
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char referenceMemory[bufferSize] = {0};
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const size_t testWidth = bufferSize / 4 / pixelSize;
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const size_t testHeight = 4;
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const size_t testDepth = 1;
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cl_image_format imageFormat;
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cl_image_desc imageDesc;
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imageFormat.image_channel_data_type = CL_UNSIGNED_INT8;
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switch (pixelSize) {
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case 1:
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imageFormat.image_channel_order = CL_R;
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break;
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case 2:
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imageFormat.image_channel_order = CL_RG;
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break;
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case 3:
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ASSERT_TRUE(false);
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break;
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case 4:
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imageFormat.image_channel_order = CL_RGBA;
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break;
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}
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imageDesc.image_type = CL_MEM_OBJECT_IMAGE2D;
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imageDesc.image_width = testWidth;
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imageDesc.image_height = testHeight;
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imageDesc.image_depth = testDepth;
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imageDesc.image_array_size = 1;
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imageDesc.image_row_pitch = 0;
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imageDesc.image_slice_pitch = 0;
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imageDesc.num_mip_levels = 0;
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imageDesc.num_samples = 0;
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imageDesc.mem_object = NULL;
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auto graphicsAllocation = createResidentAllocationAndStoreItInCsr(dstMemory, bufferSize);
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auto dstMemoryGPUPtr = reinterpret_cast<char *>(graphicsAllocation->getGpuAddress());
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cl_mem_flags flags = CL_MEM_USE_HOST_PTR | CL_MEM_READ_WRITE;
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auto surfaceFormat = Image::getSurfaceFormatFromTable(flags, &imageFormat);
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auto retVal = CL_INVALID_VALUE;
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auto image = std::unique_ptr<Image>(Image::create(
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&context,
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flags,
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surfaceFormat,
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&imageDesc,
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imageMemory,
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retVal));
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ASSERT_NE(nullptr, image);
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EXPECT_FALSE(image->isMemObjZeroCopy());
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const size_t origin[3] = {0, 1, 0};
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const size_t region[3] = {size, 1, 1};
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size_t inputRowPitch = testWidth;
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size_t inputSlicePitch = inputRowPitch * testHeight;
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retVal = pCmdQ->enqueueReadImage(
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image.get(),
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CL_TRUE,
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origin,
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region,
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inputRowPitch,
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inputSlicePitch,
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ptrOffset(dstMemory, offset),
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0,
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nullptr,
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nullptr);
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EXPECT_EQ(CL_SUCCESS, retVal);
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pCmdQ->finish(true);
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AUBCommandStreamFixture::expectMemory<FamilyType>(dstMemoryGPUPtr, referenceMemory, offset);
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AUBCommandStreamFixture::expectMemory<FamilyType>(ptrOffset(dstMemoryGPUPtr, offset), &imageMemory[inputRowPitch * origin[1] * pixelSize], size * pixelSize);
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AUBCommandStreamFixture::expectMemory<FamilyType>(ptrOffset(dstMemoryGPUPtr, size * pixelSize + offset), referenceMemory, bufferSize - offset - size * pixelSize);
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alignedFree(dstMemory);
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}
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template <typename FamilyType>
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void testWriteImageUnaligned(size_t offset, size_t size, size_t pixelSize) {
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||||||
|
DebugManagerStateRestore restorer;
|
||||||
|
DebugManager.flags.ForceLinearImages.set(true);
|
||||||
|
MockContext context(&pCmdQ->getDevice());
|
||||||
|
|
||||||
|
char srcMemory[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnoprstuwxyz";
|
||||||
|
const auto bufferSize = sizeof(srcMemory);
|
||||||
|
char dstMemory[bufferSize + 1] = {0};
|
||||||
|
char *imageMemory = &dstMemory[1]; //ensure non cacheline-aligned hostPtr to create non-zerocopy image
|
||||||
|
char referenceMemory[bufferSize] = {0};
|
||||||
|
|
||||||
|
const size_t testWidth = bufferSize / 4 / pixelSize;
|
||||||
|
const size_t testHeight = 4;
|
||||||
|
const size_t testDepth = 1;
|
||||||
|
|
||||||
|
cl_image_format imageFormat;
|
||||||
|
cl_image_desc imageDesc;
|
||||||
|
|
||||||
|
imageFormat.image_channel_data_type = CL_UNSIGNED_INT8;
|
||||||
|
switch (pixelSize) {
|
||||||
|
case 1:
|
||||||
|
imageFormat.image_channel_order = CL_R;
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
imageFormat.image_channel_order = CL_RG;
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
ASSERT_TRUE(false);
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
imageFormat.image_channel_order = CL_RGBA;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
imageDesc.image_type = CL_MEM_OBJECT_IMAGE2D;
|
||||||
|
imageDesc.image_width = testWidth;
|
||||||
|
imageDesc.image_height = testHeight;
|
||||||
|
imageDesc.image_depth = testDepth;
|
||||||
|
imageDesc.image_array_size = 1;
|
||||||
|
imageDesc.image_row_pitch = 0;
|
||||||
|
imageDesc.image_slice_pitch = 0;
|
||||||
|
imageDesc.num_mip_levels = 0;
|
||||||
|
imageDesc.num_samples = 0;
|
||||||
|
imageDesc.mem_object = NULL;
|
||||||
|
|
||||||
|
cl_mem_flags flags = CL_MEM_USE_HOST_PTR | CL_MEM_READ_WRITE;
|
||||||
|
auto surfaceFormat = Image::getSurfaceFormatFromTable(flags, &imageFormat);
|
||||||
|
auto retVal = CL_INVALID_VALUE;
|
||||||
|
|
||||||
|
auto image = std::unique_ptr<Image>(Image::create(
|
||||||
|
&context,
|
||||||
|
flags,
|
||||||
|
surfaceFormat,
|
||||||
|
&imageDesc,
|
||||||
|
imageMemory,
|
||||||
|
retVal));
|
||||||
|
ASSERT_NE(nullptr, image);
|
||||||
|
EXPECT_FALSE(image->isMemObjZeroCopy());
|
||||||
|
|
||||||
|
auto dstMemoryGPUPtr = reinterpret_cast<char *>(image->getGraphicsAllocation()->getGpuAddress());
|
||||||
|
|
||||||
|
const size_t origin[3] = {0, 1, 0}; // write first row
|
||||||
|
const size_t region[3] = {size, 1, 1}; // write only "size" number of pixels
|
||||||
|
|
||||||
|
size_t inputRowPitch = testWidth;
|
||||||
|
size_t inputSlicePitch = inputRowPitch * testHeight;
|
||||||
|
|
||||||
|
retVal = pCmdQ->enqueueWriteImage(
|
||||||
|
image.get(),
|
||||||
|
CL_TRUE,
|
||||||
|
origin,
|
||||||
|
region,
|
||||||
|
inputRowPitch,
|
||||||
|
inputSlicePitch,
|
||||||
|
ptrOffset(srcMemory, offset),
|
||||||
|
0,
|
||||||
|
nullptr,
|
||||||
|
nullptr);
|
||||||
|
EXPECT_EQ(CL_SUCCESS, retVal);
|
||||||
|
|
||||||
|
pCmdQ->finish(true);
|
||||||
|
|
||||||
|
auto imageRowPitch = image->getImageDesc().image_row_pitch;
|
||||||
|
|
||||||
|
AUBCommandStreamFixture::expectMemory<FamilyType>(dstMemoryGPUPtr, referenceMemory, inputRowPitch * pixelSize); // validate zero row is not written
|
||||||
|
AUBCommandStreamFixture::expectMemory<FamilyType>(ptrOffset(dstMemoryGPUPtr, imageRowPitch), &srcMemory[offset], size * pixelSize); // validate first row is written,
|
||||||
|
AUBCommandStreamFixture::expectMemory<FamilyType>(ptrOffset(dstMemoryGPUPtr, imageRowPitch + size * pixelSize), referenceMemory, (inputRowPitch - size) * pixelSize); // only size number of pixels, with correct data
|
||||||
|
for (uint32_t row = 2; row < testHeight; row++) {
|
||||||
|
AUBCommandStreamFixture::expectMemory<FamilyType>(ptrOffset(dstMemoryGPUPtr, row * imageRowPitch), referenceMemory, inputRowPitch * pixelSize); // next image rows shouldn;t be modified
|
||||||
|
}
|
||||||
|
}
|
||||||
|
};
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* Copyright (C) 2017-2018 Intel Corporation
|
* Copyright (C) 2017-2019 Intel Corporation
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: MIT
|
* SPDX-License-Identifier: MIT
|
||||||
*
|
*
|
||||||
@@ -11,6 +11,7 @@
|
|||||||
#include "runtime/mem_obj/image.h"
|
#include "runtime/mem_obj/image.h"
|
||||||
#include "runtime/memory_manager/os_agnostic_memory_manager.h"
|
#include "runtime/memory_manager/os_agnostic_memory_manager.h"
|
||||||
#include "unit_tests/aub_tests/command_queue/command_enqueue_fixture.h"
|
#include "unit_tests/aub_tests/command_queue/command_enqueue_fixture.h"
|
||||||
|
#include "unit_tests/aub_tests/command_queue/enqueue_read_write_image_aub_fixture.h"
|
||||||
#include "unit_tests/mocks/mock_context.h"
|
#include "unit_tests/mocks/mock_context.h"
|
||||||
#include "test.h"
|
#include "test.h"
|
||||||
|
|
||||||
@@ -214,3 +215,19 @@ INSTANTIATE_TEST_CASE_P(AUBWriteImage_simple, AUBWriteImage,
|
|||||||
::testing::Values( // channels
|
::testing::Values( // channels
|
||||||
CL_R, CL_RG, CL_RGBA),
|
CL_R, CL_RG, CL_RGBA),
|
||||||
::testing::ValuesIn(writeImageParams)));
|
::testing::ValuesIn(writeImageParams)));
|
||||||
|
|
||||||
|
using AUBWriteImageUnaligned = AUBImageUnaligned;
|
||||||
|
|
||||||
|
HWTEST_F(AUBWriteImageUnaligned, misalignedHostPtr) {
|
||||||
|
const std::vector<size_t> pixelSizes = {1, 2, 4};
|
||||||
|
const std::vector<size_t> offsets = {0, 1, 2, 3};
|
||||||
|
const std::vector<size_t> sizes = {3, 2, 1};
|
||||||
|
|
||||||
|
for (auto pixelSize : pixelSizes) {
|
||||||
|
for (auto offset : offsets) {
|
||||||
|
for (auto size : sizes) {
|
||||||
|
testWriteImageUnaligned<FamilyType>(offset, size, pixelSize);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|||||||
Reference in New Issue
Block a user