mirror of
https://github.com/intel/compute-runtime.git
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feature(sysman): Add support for zesMemoryGetBandwidth API in BMG Linux
- Added implementation for getMemoryBandwidth() in BMG product file - Additionally corrected Tempearature offsets for BMG OOBMSM rev 15 Related-to: NEO-11295 Signed-off-by: Anvesh Bakwad <anvesh.bakwad@intel.com>
This commit is contained in:
Anvesh Bakwad
committed by
Compute-Runtime-Automation
Compute-Runtime-Automation
parent
a54a3bf624
commit
6afe6da4b6
@@ -17,9 +17,11 @@ constexpr static auto gfxProduct = IGFX_BMG;
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#include "level_zero/sysman/source/shared/linux/product_helper/sysman_product_helper_xe_hp_and_later.inl"
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static std::map<std::string, std::map<std::string, uint64_t>> guidToKeyOffsetMap = {
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{"0x1e2f8200", // BMG PUNIT rev 1
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{{"VRAM_BANDWIDTH", 14}}},
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{"0x5e2F8210", // BMG OOBMSM Rev 15
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{{"SOC_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[1]", 42},
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{"VRAM_TEMPERATURE_0_2_0_GTTMMADR", 43},
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{{"SOC_THERMAL_SENSORS_TEMPERATURE_0_2_0_GTTMMADR[1]", 41},
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{"VRAM_TEMPERATURE_0_2_0_GTTMMADR", 42},
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{"reg_PCIESS_rx_bytecount_lsb", 70},
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{"reg_PCIESS_rx_bytecount_msb", 69},
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{"reg_PCIESS_tx_bytecount_lsb", 72},
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@@ -27,7 +29,250 @@ static std::map<std::string, std::map<std::string, uint64_t>> guidToKeyOffsetMap
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{"reg_PCIESS_rx_pktcount_lsb", 74},
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{"reg_PCIESS_rx_pktcount_msb", 73},
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{"reg_PCIESS_tx_pktcount_lsb", 76},
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{"reg_PCIESS_tx_pktcount_msb", 75}}}};
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{"reg_PCIESS_tx_pktcount_msb", 75},
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{"MSU_BITMASK", 922},
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{"GDDR_TELEM_CAPTURE_TIMESTAMP_UPPER", 92},
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{"GDDR_TELEM_CAPTURE_TIMESTAMP_LOWER", 93},
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{"GDDR0_CH0_GT_32B_RD_REQ_UPPER", 94},
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{"GDDR0_CH0_GT_32B_RD_REQ_LOWER", 95},
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{"GDDR1_CH0_GT_32B_RD_REQ_UPPER", 134},
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{"GDDR1_CH0_GT_32B_RD_REQ_LOWER", 135},
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{"GDDR2_CH0_GT_32B_RD_REQ_UPPER", 174},
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{"GDDR2_CH0_GT_32B_RD_REQ_LOWER", 175},
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{"GDDR3_CH0_GT_32B_RD_REQ_UPPER", 214},
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{"GDDR3_CH0_GT_32B_RD_REQ_LOWER", 215},
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{"GDDR4_CH0_GT_32B_RD_REQ_UPPER", 254},
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{"GDDR4_CH0_GT_32B_RD_REQ_LOWER", 255},
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{"GDDR5_CH0_GT_32B_RD_REQ_UPPER", 294},
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{"GDDR5_CH0_GT_32B_RD_REQ_LOWER", 295},
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{"GDDR0_CH1_GT_32B_RD_REQ_UPPER", 114},
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{"GDDR0_CH1_GT_32B_RD_REQ_LOWER", 115},
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{"GDDR1_CH1_GT_32B_RD_REQ_UPPER", 154},
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{"GDDR1_CH1_GT_32B_RD_REQ_LOWER", 155},
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{"GDDR2_CH1_GT_32B_RD_REQ_UPPER", 194},
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{"GDDR2_CH1_GT_32B_RD_REQ_LOWER", 195},
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{"GDDR3_CH1_GT_32B_RD_REQ_UPPER", 234},
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{"GDDR3_CH1_GT_32B_RD_REQ_LOWER", 235},
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{"GDDR4_CH1_GT_32B_RD_REQ_UPPER", 274},
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{"GDDR4_CH1_GT_32B_RD_REQ_LOWER", 275},
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{"GDDR5_CH1_GT_32B_RD_REQ_UPPER", 314},
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{"GDDR5_CH1_GT_32B_RD_REQ_LOWER", 315},
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{"GDDR0_CH0_GT_32B_WR_REQ_UPPER", 98},
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{"GDDR0_CH0_GT_32B_WR_REQ_LOWER", 99},
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{"GDDR1_CH0_GT_32B_WR_REQ_UPPER", 138},
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{"GDDR1_CH0_GT_32B_WR_REQ_LOWER", 139},
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{"GDDR2_CH0_GT_32B_WR_REQ_UPPER", 178},
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{"GDDR2_CH0_GT_32B_WR_REQ_LOWER", 179},
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{"GDDR3_CH0_GT_32B_WR_REQ_UPPER", 218},
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{"GDDR3_CH0_GT_32B_WR_REQ_LOWER", 219},
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{"GDDR4_CH0_GT_32B_WR_REQ_UPPER", 258},
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{"GDDR4_CH0_GT_32B_WR_REQ_LOWER", 259},
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{"GDDR5_CH0_GT_32B_WR_REQ_UPPER", 298},
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{"GDDR5_CH0_GT_32B_WR_REQ_LOWER", 299},
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{"GDDR0_CH1_GT_32B_WR_REQ_UPPER", 118},
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{"GDDR0_CH1_GT_32B_WR_REQ_LOWER", 119},
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{"GDDR1_CH1_GT_32B_WR_REQ_UPPER", 158},
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{"GDDR1_CH1_GT_32B_WR_REQ_LOWER", 159},
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{"GDDR2_CH1_GT_32B_WR_REQ_UPPER", 198},
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{"GDDR2_CH1_GT_32B_WR_REQ_LOWER", 199},
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{"GDDR3_CH1_GT_32B_WR_REQ_UPPER", 238},
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{"GDDR3_CH1_GT_32B_WR_REQ_LOWER", 239},
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{"GDDR4_CH1_GT_32B_WR_REQ_UPPER", 278},
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{"GDDR4_CH1_GT_32B_WR_REQ_LOWER", 279},
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{"GDDR5_CH1_GT_32B_WR_REQ_UPPER", 318},
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{"GDDR5_CH1_GT_32B_WR_REQ_LOWER", 319},
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{"GDDR0_CH0_DISPLAYVC0_32B_RD_REQ_UPPER", 102},
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{"GDDR0_CH0_DISPLAYVC0_32B_RD_REQ_LOWER", 103},
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{"GDDR1_CH0_DISPLAYVC0_32B_RD_REQ_UPPER", 142},
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{"GDDR1_CH0_DISPLAYVC0_32B_RD_REQ_LOWER", 143},
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{"GDDR2_CH0_DISPLAYVC0_32B_RD_REQ_UPPER", 182},
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{"GDDR2_CH0_DISPLAYVC0_32B_RD_REQ_LOWER", 183},
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{"GDDR3_CH0_DISPLAYVC0_32B_RD_REQ_UPPER", 222},
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{"GDDR3_CH0_DISPLAYVC0_32B_RD_REQ_LOWER", 223},
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{"GDDR4_CH0_DISPLAYVC0_32B_RD_REQ_UPPER", 262},
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{"GDDR4_CH0_DISPLAYVC0_32B_RD_REQ_LOWER", 263},
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{"GDDR5_CH0_DISPLAYVC0_32B_RD_REQ_UPPER", 302},
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{"GDDR5_CH0_DISPLAYVC0_32B_RD_REQ_LOWER", 303},
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{"GDDR0_CH1_DISPLAYVC0_32B_RD_REQ_UPPER", 122},
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{"GDDR0_CH1_DISPLAYVC0_32B_RD_REQ_LOWER", 123},
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{"GDDR1_CH1_DISPLAYVC0_32B_RD_REQ_UPPER", 162},
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{"GDDR1_CH1_DISPLAYVC0_32B_RD_REQ_LOWER", 163},
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{"GDDR2_CH1_DISPLAYVC0_32B_RD_REQ_UPPER", 202},
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{"GDDR2_CH1_DISPLAYVC0_32B_RD_REQ_LOWER", 203},
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{"GDDR3_CH1_DISPLAYVC0_32B_RD_REQ_UPPER", 242},
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{"GDDR3_CH1_DISPLAYVC0_32B_RD_REQ_LOWER", 243},
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{"GDDR4_CH1_DISPLAYVC0_32B_RD_REQ_UPPER", 282},
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{"GDDR4_CH1_DISPLAYVC0_32B_RD_REQ_LOWER", 283},
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{"GDDR5_CH1_DISPLAYVC0_32B_RD_REQ_UPPER", 322},
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{"GDDR5_CH1_DISPLAYVC0_32B_RD_REQ_LOWER", 323},
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{"GDDR0_CH0_SOC_32B_RD_REQ_UPPER", 106},
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{"GDDR0_CH0_SOC_32B_RD_REQ_LOWER", 107},
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{"GDDR1_CH0_SOC_32B_RD_REQ_UPPER", 146},
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{"GDDR1_CH0_SOC_32B_RD_REQ_LOWER", 147},
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{"GDDR2_CH0_SOC_32B_RD_REQ_UPPER", 186},
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{"GDDR2_CH0_SOC_32B_RD_REQ_LOWER", 187},
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{"GDDR3_CH0_SOC_32B_RD_REQ_UPPER", 226},
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{"GDDR3_CH0_SOC_32B_RD_REQ_LOWER", 227},
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{"GDDR4_CH0_SOC_32B_RD_REQ_UPPER", 266},
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{"GDDR4_CH0_SOC_32B_RD_REQ_LOWER", 267},
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{"GDDR5_CH0_SOC_32B_RD_REQ_UPPER", 306},
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{"GDDR5_CH0_SOC_32B_RD_REQ_LOWER", 307},
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{"GDDR0_CH1_SOC_32B_RD_REQ_UPPER", 126},
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{"GDDR0_CH1_SOC_32B_RD_REQ_LOWER", 127},
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{"GDDR1_CH1_SOC_32B_RD_REQ_UPPER", 166},
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{"GDDR1_CH1_SOC_32B_RD_REQ_LOWER", 167},
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{"GDDR2_CH1_SOC_32B_RD_REQ_UPPER", 206},
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{"GDDR2_CH1_SOC_32B_RD_REQ_LOWER", 207},
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{"GDDR3_CH1_SOC_32B_RD_REQ_UPPER", 246},
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{"GDDR3_CH1_SOC_32B_RD_REQ_LOWER", 247},
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{"GDDR4_CH1_SOC_32B_RD_REQ_UPPER", 286},
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{"GDDR4_CH1_SOC_32B_RD_REQ_LOWER", 287},
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{"GDDR5_CH1_SOC_32B_RD_REQ_UPPER", 326},
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{"GDDR5_CH1_SOC_32B_RD_REQ_LOWER", 327},
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{"GDDR0_CH0_SOC_32B_WR_REQ_UPPER", 110},
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{"GDDR0_CH0_SOC_32B_WR_REQ_LOWER", 111},
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{"GDDR1_CH0_SOC_32B_WR_REQ_UPPER", 150},
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{"GDDR1_CH0_SOC_32B_WR_REQ_LOWER", 151},
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{"GDDR2_CH0_SOC_32B_WR_REQ_UPPER", 190},
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{"GDDR2_CH0_SOC_32B_WR_REQ_LOWER", 191},
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{"GDDR3_CH0_SOC_32B_WR_REQ_UPPER", 230},
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{"GDDR3_CH0_SOC_32B_WR_REQ_LOWER", 231},
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{"GDDR4_CH0_SOC_32B_WR_REQ_UPPER", 270},
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{"GDDR4_CH0_SOC_32B_WR_REQ_LOWER", 271},
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{"GDDR5_CH0_SOC_32B_WR_REQ_UPPER", 310},
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{"GDDR5_CH0_SOC_32B_WR_REQ_LOWER", 311},
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{"GDDR0_CH1_SOC_32B_WR_REQ_UPPER", 130},
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{"GDDR0_CH1_SOC_32B_WR_REQ_LOWER", 131},
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{"GDDR1_CH1_SOC_32B_WR_REQ_UPPER", 170},
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{"GDDR1_CH1_SOC_32B_WR_REQ_LOWER", 171},
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{"GDDR2_CH1_SOC_32B_WR_REQ_UPPER", 210},
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{"GDDR2_CH1_SOC_32B_WR_REQ_LOWER", 211},
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{"GDDR3_CH1_SOC_32B_WR_REQ_UPPER", 250},
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{"GDDR3_CH1_SOC_32B_WR_REQ_LOWER", 251},
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{"GDDR4_CH1_SOC_32B_WR_REQ_UPPER", 290},
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{"GDDR4_CH1_SOC_32B_WR_REQ_LOWER", 291},
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{"GDDR5_CH1_SOC_32B_WR_REQ_UPPER", 330},
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{"GDDR5_CH1_SOC_32B_WR_REQ_LOWER", 331},
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{"GDDR0_CH0_GT_64B_RD_REQ_UPPER", 96},
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{"GDDR0_CH0_GT_64B_RD_REQ_LOWER", 97},
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{"GDDR1_CH0_GT_64B_RD_REQ_UPPER", 136},
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{"GDDR1_CH0_GT_64B_RD_REQ_LOWER", 137},
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{"GDDR2_CH0_GT_64B_RD_REQ_UPPER", 176},
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{"GDDR2_CH0_GT_64B_RD_REQ_LOWER", 177},
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{"GDDR3_CH0_GT_64B_RD_REQ_UPPER", 216},
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{"GDDR3_CH0_GT_64B_RD_REQ_LOWER", 217},
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{"GDDR4_CH0_GT_64B_RD_REQ_UPPER", 256},
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{"GDDR4_CH0_GT_64B_RD_REQ_LOWER", 257},
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{"GDDR5_CH0_GT_64B_RD_REQ_UPPER", 296},
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{"GDDR5_CH0_GT_64B_RD_REQ_LOWER", 297},
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{"GDDR0_CH1_GT_64B_RD_REQ_UPPER", 116},
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{"GDDR0_CH1_GT_64B_RD_REQ_LOWER", 117},
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{"GDDR1_CH1_GT_64B_RD_REQ_UPPER", 156},
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{"GDDR1_CH1_GT_64B_RD_REQ_LOWER", 157},
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{"GDDR2_CH1_GT_64B_RD_REQ_UPPER", 196},
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{"GDDR2_CH1_GT_64B_RD_REQ_LOWER", 197},
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{"GDDR3_CH1_GT_64B_RD_REQ_UPPER", 236},
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{"GDDR3_CH1_GT_64B_RD_REQ_LOWER", 237},
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{"GDDR4_CH1_GT_64B_RD_REQ_UPPER", 276},
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{"GDDR4_CH1_GT_64B_RD_REQ_LOWER", 277},
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{"GDDR5_CH1_GT_64B_RD_REQ_UPPER", 316},
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{"GDDR5_CH1_GT_64B_RD_REQ_LOWER", 317},
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{"GDDR0_CH0_DISPLAYVC0_64B_RD_REQ_UPPER", 104},
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{"GDDR0_CH0_DISPLAYVC0_64B_RD_REQ_LOWER", 105},
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{"GDDR1_CH0_DISPLAYVC0_64B_RD_REQ_UPPER", 144},
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{"GDDR1_CH0_DISPLAYVC0_64B_RD_REQ_LOWER", 145},
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{"GDDR2_CH0_DISPLAYVC0_64B_RD_REQ_UPPER", 184},
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{"GDDR2_CH0_DISPLAYVC0_64B_RD_REQ_LOWER", 185},
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{"GDDR3_CH0_DISPLAYVC0_64B_RD_REQ_UPPER", 224},
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{"GDDR3_CH0_DISPLAYVC0_64B_RD_REQ_LOWER", 225},
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{"GDDR4_CH0_DISPLAYVC0_64B_RD_REQ_UPPER", 264},
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{"GDDR4_CH0_DISPLAYVC0_64B_RD_REQ_LOWER", 265},
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{"GDDR5_CH0_DISPLAYVC0_64B_RD_REQ_UPPER", 304},
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{"GDDR5_CH0_DISPLAYVC0_64B_RD_REQ_LOWER", 305},
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{"GDDR0_CH1_DISPLAYVC0_64B_RD_REQ_UPPER", 124},
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{"GDDR0_CH1_DISPLAYVC0_64B_RD_REQ_LOWER", 125},
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{"GDDR1_CH1_DISPLAYVC0_64B_RD_REQ_UPPER", 164},
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{"GDDR1_CH1_DISPLAYVC0_64B_RD_REQ_LOWER", 165},
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{"GDDR2_CH1_DISPLAYVC0_64B_RD_REQ_UPPER", 204},
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{"GDDR2_CH1_DISPLAYVC0_64B_RD_REQ_LOWER", 205},
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{"GDDR3_CH1_DISPLAYVC0_64B_RD_REQ_UPPER", 244},
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{"GDDR3_CH1_DISPLAYVC0_64B_RD_REQ_LOWER", 245},
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{"GDDR4_CH1_DISPLAYVC0_64B_RD_REQ_UPPER", 284},
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{"GDDR4_CH1_DISPLAYVC0_64B_RD_REQ_LOWER", 285},
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{"GDDR5_CH1_DISPLAYVC0_64B_RD_REQ_UPPER", 324},
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{"GDDR5_CH1_DISPLAYVC0_64B_RD_REQ_LOWER", 325},
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{"GDDR0_CH0_SOC_64B_RD_REQ_UPPER", 108},
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{"GDDR0_CH0_SOC_64B_RD_REQ_LOWER", 109},
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{"GDDR1_CH0_SOC_64B_RD_REQ_UPPER", 148},
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{"GDDR1_CH0_SOC_64B_RD_REQ_LOWER", 149},
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{"GDDR2_CH0_SOC_64B_RD_REQ_UPPER", 188},
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{"GDDR2_CH0_SOC_64B_RD_REQ_LOWER", 189},
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{"GDDR3_CH0_SOC_64B_RD_REQ_UPPER", 228},
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{"GDDR3_CH0_SOC_64B_RD_REQ_LOWER", 229},
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{"GDDR4_CH0_SOC_64B_RD_REQ_UPPER", 268},
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{"GDDR4_CH0_SOC_64B_RD_REQ_LOWER", 269},
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{"GDDR5_CH0_SOC_64B_RD_REQ_UPPER", 308},
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{"GDDR5_CH0_SOC_64B_RD_REQ_LOWER", 309},
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{"GDDR0_CH1_SOC_64B_RD_REQ_UPPER", 128},
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{"GDDR0_CH1_SOC_64B_RD_REQ_LOWER", 129},
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{"GDDR1_CH1_SOC_64B_RD_REQ_UPPER", 168},
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{"GDDR1_CH1_SOC_64B_RD_REQ_LOWER", 169},
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{"GDDR2_CH1_SOC_64B_RD_REQ_UPPER", 208},
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{"GDDR2_CH1_SOC_64B_RD_REQ_LOWER", 209},
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{"GDDR3_CH1_SOC_64B_RD_REQ_UPPER", 248},
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{"GDDR3_CH1_SOC_64B_RD_REQ_LOWER", 249},
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{"GDDR4_CH1_SOC_64B_RD_REQ_UPPER", 288},
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{"GDDR4_CH1_SOC_64B_RD_REQ_LOWER", 289},
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{"GDDR5_CH1_SOC_64B_RD_REQ_UPPER", 328},
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{"GDDR5_CH1_SOC_64B_RD_REQ_LOWER", 329},
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{"GDDR0_CH0_SOC_64B_WR_REQ_UPPER", 112},
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{"GDDR0_CH0_SOC_64B_WR_REQ_LOWER", 113},
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{"GDDR1_CH0_SOC_64B_WR_REQ_UPPER", 152},
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{"GDDR1_CH0_SOC_64B_WR_REQ_LOWER", 153},
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{"GDDR2_CH0_SOC_64B_WR_REQ_UPPER", 192},
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{"GDDR2_CH0_SOC_64B_WR_REQ_LOWER", 193},
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{"GDDR3_CH0_SOC_64B_WR_REQ_UPPER", 232},
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{"GDDR3_CH0_SOC_64B_WR_REQ_LOWER", 233},
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{"GDDR4_CH0_SOC_64B_WR_REQ_UPPER", 272},
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{"GDDR4_CH0_SOC_64B_WR_REQ_LOWER", 273},
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{"GDDR5_CH0_SOC_64B_WR_REQ_UPPER", 312},
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{"GDDR5_CH0_SOC_64B_WR_REQ_LOWER", 313},
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{"GDDR0_CH1_SOC_64B_WR_REQ_UPPER", 132},
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{"GDDR0_CH1_SOC_64B_WR_REQ_LOWER", 133},
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{"GDDR1_CH1_SOC_64B_WR_REQ_UPPER", 172},
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{"GDDR1_CH1_SOC_64B_WR_REQ_LOWER", 173},
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{"GDDR2_CH1_SOC_64B_WR_REQ_UPPER", 212},
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{"GDDR2_CH1_SOC_64B_WR_REQ_LOWER", 213},
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{"GDDR3_CH1_SOC_64B_WR_REQ_UPPER", 252},
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{"GDDR3_CH1_SOC_64B_WR_REQ_LOWER", 253},
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{"GDDR4_CH1_SOC_64B_WR_REQ_UPPER", 292},
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{"GDDR4_CH1_SOC_64B_WR_REQ_LOWER", 293},
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{"GDDR5_CH1_SOC_64B_WR_REQ_UPPER", 332},
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{"GDDR5_CH1_SOC_64B_WR_REQ_LOWER", 333},
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{"GDDR0_CH0_GT_64B_WR_REQ_UPPER", 100},
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{"GDDR0_CH0_GT_64B_WR_REQ_LOWER", 101},
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{"GDDR1_CH0_GT_64B_WR_REQ_UPPER", 140},
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{"GDDR1_CH0_GT_64B_WR_REQ_LOWER", 141},
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{"GDDR2_CH0_GT_64B_WR_REQ_UPPER", 180},
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{"GDDR2_CH0_GT_64B_WR_REQ_LOWER", 181},
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{"GDDR3_CH0_GT_64B_WR_REQ_UPPER", 220},
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{"GDDR3_CH0_GT_64B_WR_REQ_LOWER", 221},
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{"GDDR4_CH0_GT_64B_WR_REQ_UPPER", 260},
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{"GDDR4_CH0_GT_64B_WR_REQ_LOWER", 261},
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{"GDDR5_CH0_GT_64B_WR_REQ_UPPER", 300},
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{"GDDR5_CH0_GT_64B_WR_REQ_LOWER", 301},
|
||||
{"GDDR0_CH1_GT_64B_WR_REQ_UPPER", 120},
|
||||
{"GDDR0_CH1_GT_64B_WR_REQ_LOWER", 121},
|
||||
{"GDDR1_CH1_GT_64B_WR_REQ_UPPER", 160},
|
||||
{"GDDR1_CH1_GT_64B_WR_REQ_LOWER", 161},
|
||||
{"GDDR2_CH1_GT_64B_WR_REQ_UPPER", 200},
|
||||
{"GDDR2_CH1_GT_64B_WR_REQ_LOWER", 201},
|
||||
{"GDDR3_CH1_GT_64B_WR_REQ_UPPER", 240},
|
||||
{"GDDR3_CH1_GT_64B_WR_REQ_LOWER", 241},
|
||||
{"GDDR4_CH1_GT_64B_WR_REQ_UPPER", 280},
|
||||
{"GDDR4_CH1_GT_64B_WR_REQ_LOWER", 281},
|
||||
{"GDDR5_CH1_GT_64B_WR_REQ_UPPER", 320},
|
||||
{"GDDR5_CH1_GT_64B_WR_REQ_LOWER", 321}}}};
|
||||
|
||||
template <>
|
||||
const std::map<std::string, std::map<std::string, uint64_t>> *SysmanProductHelperHw<gfxProduct>::getGuidToKeyOffsetMap() {
|
||||
@@ -218,6 +463,185 @@ ze_result_t SysmanProductHelperHw<gfxProduct>::getGlobalMaxTemperature(LinuxSysm
|
||||
return result;
|
||||
}
|
||||
|
||||
static ze_result_t getMemoryMaxBandwidth(const std::map<std::string, uint64_t> &keyOffsetMap, std::unordered_map<std::string, std::pair<std::string, uint64_t>> &keyTelemInfoMap,
|
||||
zes_mem_bandwidth_t *pBandwidth) {
|
||||
uint32_t maxBandwidth = 0;
|
||||
std::string key = "VRAM_BANDWIDTH";
|
||||
if (!PlatformMonitoringTech::readValue(keyOffsetMap, keyTelemInfoMap[key].first, key, keyTelemInfoMap[key].second, maxBandwidth)) {
|
||||
return ZE_RESULT_ERROR_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
maxBandwidth = maxBandwidth >> 16;
|
||||
pBandwidth->maxBandwidth = static_cast<uint64_t>(maxBandwidth) * megaBytesToBytes * 100;
|
||||
|
||||
return ZE_RESULT_SUCCESS;
|
||||
}
|
||||
|
||||
static ze_result_t getMemoryBandwidthTimestamp(const std::map<std::string, uint64_t> &keyOffsetMap, std::unordered_map<std::string, std::pair<std::string, uint64_t>> &keyTelemInfoMap,
|
||||
zes_mem_bandwidth_t *pBandwidth) {
|
||||
uint32_t timeStampH = 0;
|
||||
uint32_t timeStampL = 0;
|
||||
pBandwidth->timestamp = 0;
|
||||
|
||||
std::string key = "GDDR_TELEM_CAPTURE_TIMESTAMP_UPPER";
|
||||
if (!PlatformMonitoringTech::readValue(keyOffsetMap, keyTelemInfoMap[key].first, key, keyTelemInfoMap[key].second, timeStampH)) {
|
||||
return ZE_RESULT_ERROR_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
key = "GDDR_TELEM_CAPTURE_TIMESTAMP_LOWER";
|
||||
if (!PlatformMonitoringTech::readValue(keyOffsetMap, keyTelemInfoMap[key].first, key, keyTelemInfoMap[key].second, timeStampL)) {
|
||||
return ZE_RESULT_ERROR_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
pBandwidth->timestamp = PACK_INTO_64BIT(timeStampH, timeStampL);
|
||||
|
||||
return ZE_RESULT_SUCCESS;
|
||||
}
|
||||
|
||||
static ze_result_t getCounterValues(const std::vector<std::pair<const std::string, const std::string>> ®isterList, const std::string &keyPrefix,
|
||||
const std::map<std::string, uint64_t> &keyOffsetMap, std::unordered_map<std::string, std::pair<std::string, uint64_t>> &keyTelemInfoMap, uint64_t &totalCounter) {
|
||||
for (const auto ®Pair : registerList) {
|
||||
uint32_t regL = 0;
|
||||
uint32_t regH = 0;
|
||||
|
||||
std::string keyL = keyPrefix + regPair.first;
|
||||
if (!PlatformMonitoringTech::readValue(keyOffsetMap, keyTelemInfoMap[keyL].first, keyL, keyTelemInfoMap[keyL].second, regL)) {
|
||||
return ZE_RESULT_ERROR_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
std::string keyH = keyPrefix + regPair.second;
|
||||
if (!PlatformMonitoringTech::readValue(keyOffsetMap, keyTelemInfoMap[keyH].first, keyH, keyTelemInfoMap[keyH].second, regH)) {
|
||||
return ZE_RESULT_ERROR_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
totalCounter += PACK_INTO_64BIT(regH, regL);
|
||||
}
|
||||
|
||||
return ZE_RESULT_SUCCESS;
|
||||
}
|
||||
|
||||
static ze_result_t getMemoryBandwidthCounterValues(const std::map<std::string, uint64_t> &keyOffsetMap, std::unordered_map<std::string, std::pair<std::string, uint64_t>> &keyTelemInfoMap,
|
||||
const uint32_t &supportedMsu, zes_mem_bandwidth_t *pBandwidth) {
|
||||
const std::vector<std::pair<const std::string, const std::string>> readBwRegisterList{
|
||||
{"_CH0_GT_32B_RD_REQ_LOWER", "_CH0_GT_32B_RD_REQ_UPPER"},
|
||||
{"_CH0_DISPLAYVC0_32B_RD_REQ_LOWER", "_CH0_DISPLAYVC0_32B_RD_REQ_UPPER"},
|
||||
{"_CH0_SOC_32B_RD_REQ_LOWER", "_CH0_SOC_32B_RD_REQ_UPPER"},
|
||||
{"_CH1_GT_32B_RD_REQ_LOWER", "_CH1_GT_32B_RD_REQ_UPPER"},
|
||||
{"_CH1_DISPLAYVC0_32B_RD_REQ_LOWER", "_CH1_DISPLAYVC0_32B_RD_REQ_UPPER"},
|
||||
{"_CH1_SOC_32B_RD_REQ_LOWER", "_CH1_SOC_32B_RD_REQ_UPPER"},
|
||||
{"_CH0_GT_64B_RD_REQ_LOWER", "_CH0_GT_64B_RD_REQ_UPPER"},
|
||||
{"_CH0_DISPLAYVC0_64B_RD_REQ_LOWER", "_CH0_DISPLAYVC0_64B_RD_REQ_UPPER"},
|
||||
{"_CH0_SOC_64B_RD_REQ_LOWER", "_CH0_SOC_64B_RD_REQ_UPPER"},
|
||||
{"_CH1_GT_64B_RD_REQ_LOWER", "_CH1_GT_64B_RD_REQ_UPPER"},
|
||||
{"_CH1_DISPLAYVC0_64B_RD_REQ_LOWER", "_CH1_DISPLAYVC0_64B_RD_REQ_UPPER"},
|
||||
{"_CH1_SOC_64B_RD_REQ_LOWER", "_CH1_SOC_64B_RD_REQ_UPPER"}};
|
||||
|
||||
const std::vector<std::pair<const std::string, const std::string>> writeBwRegisterList{
|
||||
{"_CH0_GT_32B_WR_REQ_LOWER", "_CH0_GT_32B_WR_REQ_UPPER"},
|
||||
{"_CH0_SOC_32B_WR_REQ_LOWER", "_CH0_SOC_32B_WR_REQ_UPPER"},
|
||||
{"_CH1_GT_32B_WR_REQ_LOWER", "_CH1_GT_32B_WR_REQ_UPPER"},
|
||||
{"_CH1_SOC_32B_WR_REQ_LOWER", "_CH1_SOC_32B_WR_REQ_UPPER"},
|
||||
{"_CH0_GT_64B_WR_REQ_LOWER", "_CH0_GT_64B_WR_REQ_UPPER"},
|
||||
{"_CH0_SOC_64B_WR_REQ_LOWER", "_CH0_SOC_64B_WR_REQ_UPPER"},
|
||||
{"_CH1_GT_64B_WR_REQ_LOWER", "_CH1_GT_64B_WR_REQ_UPPER"},
|
||||
{"_CH1_SOC_64B_WR_REQ_LOWER", "_CH1_SOC_64B_WR_REQ_UPPER"}};
|
||||
|
||||
constexpr uint64_t maxSupportedMsu = 8;
|
||||
constexpr uint64_t transactionSize = 32;
|
||||
|
||||
pBandwidth->readCounter = 0;
|
||||
pBandwidth->writeCounter = 0;
|
||||
|
||||
for (uint32_t i = 0; i < maxSupportedMsu; i++) {
|
||||
if (supportedMsu & (1 << i)) {
|
||||
std::ostringstream keyStream;
|
||||
keyStream << "GDDR" << i;
|
||||
std::string keyPrefix = keyStream.str();
|
||||
|
||||
if (ZE_RESULT_SUCCESS != getCounterValues(readBwRegisterList, keyPrefix, keyOffsetMap, keyTelemInfoMap, pBandwidth->readCounter)) {
|
||||
return ZE_RESULT_ERROR_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
if (ZE_RESULT_SUCCESS != getCounterValues(writeBwRegisterList, keyPrefix, keyOffsetMap, keyTelemInfoMap, pBandwidth->writeCounter)) {
|
||||
return ZE_RESULT_ERROR_NOT_AVAILABLE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pBandwidth->readCounter = (pBandwidth->readCounter * transactionSize) / microFactor;
|
||||
pBandwidth->writeCounter = (pBandwidth->writeCounter * transactionSize) / microFactor;
|
||||
|
||||
return ZE_RESULT_SUCCESS;
|
||||
}
|
||||
|
||||
template <>
|
||||
ze_result_t SysmanProductHelperHw<gfxProduct>::getMemoryBandwidth(zes_mem_bandwidth_t *pBandwidth, LinuxSysmanImp *pLinuxSysmanImp, uint32_t subdeviceId) {
|
||||
|
||||
std::string &rootPath = pLinuxSysmanImp->getPciRootPath();
|
||||
std::map<uint32_t, std::string> telemNodes;
|
||||
NEO::PmtUtil::getTelemNodesInPciPath(std::string_view(rootPath), telemNodes);
|
||||
if (telemNodes.empty()) {
|
||||
return ZE_RESULT_ERROR_UNSUPPORTED_FEATURE;
|
||||
}
|
||||
|
||||
std::map<std::string, uint64_t> keyOffsetMap;
|
||||
std::unordered_map<std::string, std::pair<std::string, uint64_t>> keyTelemInfoMap;
|
||||
|
||||
// Iterate through all the TelemNodes to find both OOBMSM and PUNIT guids along with their keyOffsetMap
|
||||
for (const auto &it : telemNodes) {
|
||||
std::string telemNodeDir = it.second;
|
||||
|
||||
std::array<char, NEO::PmtUtil::guidStringSize> guidString = {};
|
||||
if (!NEO::PmtUtil::readGuid(telemNodeDir, guidString)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
uint64_t telemOffset = 0;
|
||||
if (!NEO::PmtUtil::readOffset(telemNodeDir, telemOffset)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
auto keyOffsetMapIterator = guidToKeyOffsetMap.find(guidString.data());
|
||||
if (keyOffsetMapIterator == guidToKeyOffsetMap.end()) {
|
||||
continue;
|
||||
}
|
||||
|
||||
const auto &tempKeyOffsetMap = keyOffsetMapIterator->second;
|
||||
for (auto it = tempKeyOffsetMap.begin(); it != tempKeyOffsetMap.end(); it++) {
|
||||
keyOffsetMap[it->first] = it->second;
|
||||
keyTelemInfoMap[it->first] = std::make_pair(telemNodeDir, telemOffset);
|
||||
}
|
||||
}
|
||||
|
||||
if (keyOffsetMap.empty()) {
|
||||
return ZE_RESULT_ERROR_UNSUPPORTED_FEATURE;
|
||||
}
|
||||
|
||||
// Get Memory Subsystem Bitmask
|
||||
uint32_t supportedMsu = 0;
|
||||
std::string key = "MSU_BITMASK";
|
||||
if (!PlatformMonitoringTech::readValue(keyOffsetMap, keyTelemInfoMap[key].first, key, keyTelemInfoMap[key].second, supportedMsu)) {
|
||||
return ZE_RESULT_ERROR_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
// Get Read and Write Counter Values
|
||||
if (ZE_RESULT_SUCCESS != getMemoryBandwidthCounterValues(keyOffsetMap, keyTelemInfoMap, supportedMsu, pBandwidth)) {
|
||||
return ZE_RESULT_ERROR_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
// Get Timestamp Values
|
||||
if (ZE_RESULT_SUCCESS != getMemoryBandwidthTimestamp(keyOffsetMap, keyTelemInfoMap, pBandwidth)) {
|
||||
return ZE_RESULT_ERROR_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
// Get Max Bandwidth
|
||||
if (ZE_RESULT_SUCCESS != getMemoryMaxBandwidth(keyOffsetMap, keyTelemInfoMap, pBandwidth)) {
|
||||
return ZE_RESULT_ERROR_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
return ZE_RESULT_SUCCESS;
|
||||
}
|
||||
|
||||
template class SysmanProductHelperHw<gfxProduct>;
|
||||
|
||||
} // namespace Sysman
|
||||
|
||||
Reference in New Issue
Block a user