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Use L3_CONTROL only for DG1

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Related-To: LOCI-1877
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
This commit is contained in:
Young Jin Yoon
2021-02-10 15:20:50 +00:00
committed by Compute-Runtime-Automation
parent a79f67958e
commit 6f555d6258
18 changed files with 1414 additions and 13 deletions
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6
level_zero/core/source/gen12lp/CMakeLists.txt
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@@ -1,5 +1,5 @@
#
# Copyright (C) 2019-2020 Intel Corporation
# Copyright (C) 2019-2021 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
@@ -9,12 +9,12 @@ if(SUPPORT_GEN12LP)
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_gen12lp.h
${CMAKE_CURRENT_SOURCE_DIR}/debugger_gen12lp.cpp
${CMAKE_CURRENT_SOURCE_DIR}/definitions${BRANCH_DIR_SUFFIX}/cache_flush_gen12lp.inl
${CMAKE_CURRENT_SOURCE_DIR}/definitions/cache_flush_gen12lp.inl
${CMAKE_CURRENT_SOURCE_DIR}/enable_family_full_l0_gen12lp.cpp
${CMAKE_CURRENT_SOURCE_DIR}/l0_hw_helper_gen12lp.cpp
)
add_subdirectories()
target_include_directories(${L0_STATIC_LIB_NAME} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/definitions${BRANCH_DIR_SUFFIX}/)
target_include_directories(${L0_STATIC_LIB_NAME} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/definitions/)
target_sources(${L0_STATIC_LIB_NAME} PRIVATE ${HW_SOURCES_GEN12LP})
set_property(GLOBAL APPEND PROPERTY L0_HW_SOURCES_GEN12LP ${HW_SOURCES_GEN12LP})

64
level_zero/core/source/gen12lp/definitions/cache_flush_gen12lp.inl
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@@ -1,10 +1,12 @@
/*
* Copyright (C) 2020 Intel Corporation
* Copyright (C) 2020-2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/helpers/cache_flush.inl"
#include "level_zero/core/source/cmdlist/cmdlist_hw.h"
#include "pipe_control_args.h"
@@ -15,9 +17,61 @@ template <GFXCORE_FAMILY gfxCoreFamily>
void CommandListCoreFamily<gfxCoreFamily>::applyMemoryRangesBarrier(uint32_t numRanges,
const size_t *pRangeSizes,
const void **pRanges) {
NEO::PipeControlArgs args(true);
NEO::MemorySynchronizationCommands<GfxFamily>::addPipeControl(*commandContainer.getCommandStream(),
args);
}
using GfxFamily = typename NEO::GfxFamilyMapper<gfxCoreFamily>::GfxFamily;
auto &hwInfo = commandContainer.getDevice()->getHardwareInfo();
bool supportL3Control = hwInfo.capabilityTable.supportCacheFlushAfterWalker;
if (!supportL3Control) {
NEO::PipeControlArgs args(true);
NEO::MemorySynchronizationCommands<GfxFamily>::addPipeControl(*commandContainer.getCommandStream(),
args);
} else {
NEO::LinearStream *commandStream = commandContainer.getCommandStream();
NEO::SVMAllocsManager *svmAllocsManager =
device->getDriverHandle()->getSvmAllocsManager();
for (uint32_t i = 0; i < numRanges; i++) {
StackVec<NEO::L3Range, NEO::maxFlushSubrangeCount> subranges;
const uint64_t pRange = reinterpret_cast<uint64_t>(pRanges[i]);
const size_t pRangeSize = pRangeSizes[i];
const uint64_t pEndRange = pRange + pRangeSize;
uint64_t pFlushRange;
size_t pFlushRangeSize;
uint64_t postSyncAddressToFlush = 0;
NEO::SvmAllocationData *allocData =
svmAllocsManager->getSVMAllocs()->get(pRanges[i]);
if (allocData == nullptr || pRangeSize > allocData->size) {
continue;
}
pFlushRange = pRange;
pFlushRangeSize = pRangeSize;
if (NEO::L3Range::meetsMinimumAlignment(pRange) == false) {
pFlushRange = alignDown(pRange, MemoryConstants::pageSize);
}
if (NEO::L3Range::meetsMinimumAlignment(pRangeSize) == false) {
pFlushRangeSize = alignUp(pRangeSize, MemoryConstants::pageSize);
}
bool isRangeSharedBetweenTwoPages =
(alignDown(pEndRange, MemoryConstants::pageSize) !=
pFlushRange);
if (isRangeSharedBetweenTwoPages) {
pFlushRangeSize += MemoryConstants::pageSize;
}
coverRangeExact(pFlushRange,
pFlushRangeSize,
subranges,
GfxFamily::L3_FLUSH_ADDRESS_RANGE::L3_FLUSH_EVICTION_POLICY_FLUSH_L3_WITH_EVICTION);
NEO::flushGpuCache<GfxFamily>(commandStream, subranges,
postSyncAddressToFlush,
device->getHwInfo());
}
}
}
} // namespace L0

4
level_zero/core/source/gen12lp/dg1/cmdlist_dg1.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2020 Intel Corporation
* Copyright (C) 2019-2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -26,4 +26,4 @@ static CommandListPopulateFactory<IGFX_DG1, CommandListProductFamily<IGFX_DG1>>
static CommandListImmediatePopulateFactory<IGFX_DG1, CommandListImmediateProductFamily<IGFX_DG1>>
populateDG1Immediate;
} // namespace L0
} // namespace L0

3
level_zero/core/test/unit_tests/gen12lp/CMakeLists.txt
View File

@@ -9,10 +9,11 @@ if(TESTS_GEN12LP)
${COMPUTE_RUNTIME_ULT_GEN12LP}
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/enable_l0_mocks_gen12lp.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_cmdlist_gen12lp.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_device_gen12lp.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_events_gen12lp.cpp
${CMAKE_CURRENT_SOURCE_DIR}/test_module_gen12lp.cpp
)
target_include_directories(${TARGET_NAME} PRIVATE ${COMPUTE_RUNTIME_DIR}/level_zero/core/source/gen12lp/definitions${BRANCH_DIR_SUFFIX}/)
target_include_directories(${TARGET_NAME} PRIVATE ${COMPUTE_RUNTIME_DIR}/level_zero/core/source/gen12lp/definitions/)
endif()

278
level_zero/core/test/unit_tests/gen12lp/test_cmdlist_gen12lp.cpp Normal file
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@@ -0,0 +1,278 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/gmm_helper/gmm_helper.h"
#include "shared/source/helpers/register_offsets.h"
#include "shared/source/helpers/state_base_address.h"
#include "shared/test/common/cmd_parse/gen_cmd_parse.h"
#include "shared/test/common/mocks/mock_graphics_allocation.h"
#include "test.h"
#include "level_zero/core/source/gen12lp/cmdlist_gen12lp.h"
#include "level_zero/core/test/unit_tests/fixtures/device_fixture.h"
#include "level_zero/core/test/unit_tests/mocks/mock_cmdlist.h"
#include "level_zero/core/test/unit_tests/mocks/mock_kernel.h"
namespace L0 {
namespace ult {
using CommandListCreate = Test<DeviceFixture>;
template <PRODUCT_FAMILY productFamily>
struct CommandListAdjustStateComputeMode : public WhiteBox<::L0::CommandListProductFamily<productFamily>> {
CommandListAdjustStateComputeMode() : WhiteBox<::L0::CommandListProductFamily<productFamily>>(1) {}
using ::L0::CommandListProductFamily<productFamily>::applyMemoryRangesBarrier;
};
HWTEST2_F(CommandListCreate, givenAllocationsWhenApplyRangesBarrierThenCheckWhetherL3ControlIsProgrammed, IsGen12LP) {
using GfxFamily = typename NEO::GfxFamilyMapper<gfxCoreFamily>::GfxFamily;
using L3_CONTROL = typename GfxFamily::L3_CONTROL;
auto &hardwareInfo = this->neoDevice->getHardwareInfo();
auto commandList = std::make_unique<WhiteBox<::L0::CommandListCoreFamily<gfxCoreFamily>>>();
commandList->initialize(device, NEO::EngineGroupType::Copy);
uint64_t gpuAddress = 0x1200;
void *buffer = reinterpret_cast<void *>(gpuAddress);
size_t size = 0x1100;
NEO::MockGraphicsAllocation mockAllocation(buffer, gpuAddress, size);
NEO::SvmAllocationData allocData(0);
allocData.size = size;
allocData.gpuAllocations.addAllocation(&mockAllocation);
device->getDriverHandle()->getSvmAllocsManager()->insertSVMAlloc(allocData);
const void *ranges[] = {buffer};
const size_t sizes[] = {size};
commandList->applyMemoryRangesBarrier(1, sizes, ranges);
GenCmdList cmdList;
ASSERT_TRUE(FamilyType::PARSE::parseCommandBuffer(
cmdList, ptrOffset(commandList->commandContainer.getCommandStream()->getCpuBase(), 0), commandList->commandContainer.getCommandStream()->getUsed()));
auto itor = find<L3_CONTROL *>(cmdList.begin(), cmdList.end());
if (hardwareInfo.capabilityTable.supportCacheFlushAfterWalker) {
EXPECT_NE(cmdList.end(), itor);
} else {
EXPECT_EQ(cmdList.end(), itor);
}
}
HWTEST2_F(CommandListCreate, GivenHostMemoryNotInSvmManagerWhenAppendingMemoryBarrierThenAdditionalCommandsNotAdded,
IsDG1) {
ze_result_t result;
uint32_t numRanges = 1;
const size_t pRangeSizes = 1;
const char *_pRanges[pRangeSizes];
const void **pRanges = reinterpret_cast<const void **>(&_pRanges[0]);
auto commandList = new CommandListAdjustStateComputeMode<productFamily>();
bool ret = commandList->initialize(device, NEO::EngineGroupType::RenderCompute);
ASSERT_FALSE(ret);
auto usedSpaceBefore =
commandList->commandContainer.getCommandStream()->getUsed();
result = commandList->appendMemoryRangesBarrier(numRanges, &pRangeSizes,
pRanges, nullptr, 0,
nullptr);
EXPECT_EQ(ZE_RESULT_SUCCESS, result);
auto usedSpaceAfter =
commandList->commandContainer.getCommandStream()->getUsed();
ASSERT_EQ(usedSpaceAfter, usedSpaceBefore);
commandList->destroy();
}
HWTEST2_F(CommandListCreate, GivenHostMemoryInSvmManagerWhenAppendingMemoryBarrierThenL3CommandsAdded,
IsDG1) {
ze_result_t result;
uint32_t numRanges = 1;
const size_t pRangeSizes = 1;
void *_pRanges;
ze_device_mem_alloc_desc_t deviceDesc = {};
result = context->allocDeviceMem(device->toHandle(),
&deviceDesc,
pRangeSizes,
4096u,
&_pRanges);
EXPECT_EQ(ZE_RESULT_SUCCESS, result);
const void **pRanges = const_cast<const void **>(&_pRanges);
auto commandList = new CommandListAdjustStateComputeMode<productFamily>();
bool ret = commandList->initialize(device, NEO::EngineGroupType::RenderCompute);
ASSERT_FALSE(ret);
auto usedSpaceBefore =
commandList->commandContainer.getCommandStream()->getUsed();
result = commandList->appendMemoryRangesBarrier(numRanges, &pRangeSizes,
pRanges, nullptr, 0,
nullptr);
EXPECT_EQ(ZE_RESULT_SUCCESS, result);
auto usedSpaceAfter =
commandList->commandContainer.getCommandStream()->getUsed();
ASSERT_NE(usedSpaceAfter, usedSpaceBefore);
GenCmdList cmdList;
ASSERT_TRUE(FamilyType::PARSE::parseCommandBuffer(
cmdList,
ptrOffset(
commandList->commandContainer.getCommandStream()->getCpuBase(), 0),
usedSpaceAfter));
using L3_CONTROL = typename FamilyType::L3_CONTROL;
auto itorPC = find<L3_CONTROL *>(cmdList.begin(), cmdList.end());
ASSERT_NE(cmdList.end(), itorPC);
{
using L3_FLUSH_EVICTION_POLICY = typename FamilyType::L3_FLUSH_ADDRESS_RANGE::L3_FLUSH_EVICTION_POLICY;
auto cmd = genCmdCast<L3_CONTROL *>(*itorPC);
auto &hwHelper = NEO::HwHelper::get(device->getHwInfo().platform.eRenderCoreFamily);
auto isA0Stepping = (hwHelper.getSteppingFromHwRevId(device->getHwInfo()) == REVISION_A0);
auto maskedAddress = cmd->getL3FlushAddressRange().getAddress(isA0Stepping);
EXPECT_NE(maskedAddress, 0u);
EXPECT_EQ(reinterpret_cast<uint64_t>(*pRanges),
static_cast<uint64_t>(maskedAddress));
EXPECT_EQ(
cmd->getL3FlushAddressRange().getL3FlushEvictionPolicy(isA0Stepping),
L3_FLUSH_EVICTION_POLICY::L3_FLUSH_EVICTION_POLICY_FLUSH_L3_WITH_EVICTION);
}
commandList->destroy();
context->freeMem(_pRanges);
}
HWTEST2_F(CommandListCreate, GivenHostMemoryWhenAppendingMemoryBarrierThenAddressMisalignmentCorrected,
IsDG1) {
ze_result_t result;
uint32_t numRanges = 1;
const size_t misalignment_factor = 761;
const size_t pRangeSizes = 4096;
void *_pRanges;
ze_device_mem_alloc_desc_t deviceDesc = {};
result = context->allocDeviceMem(device->toHandle(),
&deviceDesc,
pRangeSizes,
4096u,
&_pRanges);
EXPECT_EQ(ZE_RESULT_SUCCESS, result);
unsigned char *c_pRanges = reinterpret_cast<unsigned char *>(_pRanges);
c_pRanges += misalignment_factor;
_pRanges = static_cast<void *>(c_pRanges);
const void **pRanges = const_cast<const void **>(&_pRanges);
auto commandList = new CommandListAdjustStateComputeMode<productFamily>();
bool ret = commandList->initialize(device, NEO::EngineGroupType::RenderCompute);
ASSERT_FALSE(ret);
auto usedSpaceBefore =
commandList->commandContainer.getCommandStream()->getUsed();
result = commandList->appendMemoryRangesBarrier(numRanges, &pRangeSizes,
pRanges, nullptr, 0,
nullptr);
EXPECT_EQ(ZE_RESULT_SUCCESS, result);
auto usedSpaceAfter =
commandList->commandContainer.getCommandStream()->getUsed();
ASSERT_NE(usedSpaceAfter, usedSpaceBefore);
GenCmdList cmdList;
ASSERT_TRUE(FamilyType::PARSE::parseCommandBuffer(
cmdList,
ptrOffset(
commandList->commandContainer.getCommandStream()->getCpuBase(), 0),
usedSpaceAfter));
using L3_CONTROL = typename FamilyType::L3_CONTROL;
auto itorPC = find<L3_CONTROL *>(cmdList.begin(), cmdList.end());
ASSERT_NE(cmdList.end(), itorPC);
{
using L3_FLUSH_EVICTION_POLICY = typename FamilyType::L3_FLUSH_ADDRESS_RANGE::L3_FLUSH_EVICTION_POLICY;
auto cmd = genCmdCast<L3_CONTROL *>(*itorPC);
auto &hwHelper = NEO::HwHelper::get(device->getHwInfo().platform.eRenderCoreFamily);
auto isA0Stepping = (hwHelper.getSteppingFromHwRevId(device->getHwInfo()) == REVISION_A0);
auto maskedAddress = cmd->getL3FlushAddressRange().getAddress(isA0Stepping);
EXPECT_NE(maskedAddress, 0u);
EXPECT_EQ(reinterpret_cast<uint64_t>(*pRanges) - misalignment_factor,
static_cast<uint64_t>(maskedAddress));
EXPECT_EQ(
cmd->getL3FlushAddressRange().getL3FlushEvictionPolicy(isA0Stepping),
L3_FLUSH_EVICTION_POLICY::L3_FLUSH_EVICTION_POLICY_FLUSH_L3_WITH_EVICTION);
}
commandList->destroy();
context->freeMem(_pRanges);
}
HWTEST2_F(CommandListCreate, givenAllocationsWhenApplyRangesBarrierWithInvalidAddressSizeThenL3ControlIsNotProgrammed, IsDG1) {
using GfxFamily = typename NEO::GfxFamilyMapper<gfxCoreFamily>::GfxFamily;
using L3_CONTROL = typename GfxFamily::L3_CONTROL;
ze_result_t result;
const size_t pRangeSizes = 4096;
void *_pRanges;
ze_device_mem_alloc_desc_t deviceDesc = {};
result = context->allocDeviceMem(device->toHandle(),
&deviceDesc,
pRangeSizes,
4096u,
&_pRanges);
EXPECT_EQ(ZE_RESULT_SUCCESS, result);
auto commandList = new CommandListAdjustStateComputeMode<productFamily>();
ASSERT_NE(nullptr, commandList);
bool ret = commandList->initialize(device, NEO::EngineGroupType::RenderCompute);
ASSERT_FALSE(ret);
const void *ranges[] = {_pRanges};
const size_t sizes[] = {2 * pRangeSizes};
commandList->applyMemoryRangesBarrier(1, sizes, ranges);
GenCmdList cmdList;
ASSERT_TRUE(FamilyType::PARSE::parseCommandBuffer(
cmdList, ptrOffset(commandList->commandContainer.getCommandStream()->getCpuBase(), 0), commandList->commandContainer.getCommandStream()->getUsed()));
auto itor = find<L3_CONTROL *>(cmdList.begin(), cmdList.end());
EXPECT_EQ(cmdList.end(), itor);
commandList->destroy();
context->freeMem(_pRanges);
}
HWTEST2_F(CommandListCreate, givenAllocationsWhenApplyRangesBarrierWithInvalidAddressThenL3ControlIsNotProgrammed, IsDG1) {
using GfxFamily = typename NEO::GfxFamilyMapper<gfxCoreFamily>::GfxFamily;
using L3_CONTROL = typename GfxFamily::L3_CONTROL;
ze_result_t result;
const size_t pRangeSizes = 4096;
void *_pRanges;
ze_device_mem_alloc_desc_t deviceDesc = {};
result = context->allocDeviceMem(device->toHandle(),
&deviceDesc,
pRangeSizes,
4096u,
&_pRanges);
EXPECT_EQ(ZE_RESULT_SUCCESS, result);
auto commandList = new CommandListAdjustStateComputeMode<productFamily>();
ASSERT_NE(nullptr, commandList);
bool ret = commandList->initialize(device, NEO::EngineGroupType::RenderCompute);
ASSERT_FALSE(ret);
const void *ranges[] = {nullptr};
const size_t sizes[] = {pRangeSizes};
commandList->applyMemoryRangesBarrier(1, sizes, ranges);
GenCmdList cmdList;
ASSERT_TRUE(FamilyType::PARSE::parseCommandBuffer(
cmdList, ptrOffset(commandList->commandContainer.getCommandStream()->getCpuBase(), 0), commandList->commandContainer.getCommandStream()->getUsed()));
auto itor = find<L3_CONTROL *>(cmdList.begin(), cmdList.end());
EXPECT_EQ(cmdList.end(), itor);
commandList->destroy();
context->freeMem(_pRanges);
}
} // namespace ult
} // namespace L0

3
level_zero/core/test/unit_tests/sources/helper/CMakeLists.txt
View File

@@ -1,11 +1,12 @@
#
# Copyright (C) 2020 Intel Corporation
# Copyright (C) 2020-2021 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
target_sources(${TARGET_NAME} PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/cache_flush_tests.cpp
${CMAKE_CURRENT_SOURCE_DIR}/heap_assigner_l0_tests.cpp
)
add_subdirectories()

92
level_zero/core/test/unit_tests/sources/helper/cache_flush_tests.cpp Normal file
View File

@@ -0,0 +1,92 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/helpers/cache_flush.inl"
#include "shared/source/helpers/l3_range.h"
#include "shared/test/common/cmd_parse/gen_cmd_parse.h"
#include "shared/test/common/mocks/mock_graphics_allocation.h"
#include "test.h"
#include "level_zero/core/source/gen12lp/cmdlist_gen12lp.h"
#include "level_zero/core/test/unit_tests/fixtures/device_fixture.h"
#include "level_zero/core/test/unit_tests/mocks/mock_cmdlist.h"
namespace L0 {
namespace ult {
using CacheFlushTests = Test<DeviceFixture>;
HWTEST2_F(CacheFlushTests, GivenCommandStreamWithSingleL3RangeAndNonZeroPostSyncAddressWhenFlushGpuCacheIsCalledThenPostSyncOperationIsSetForL3Control, IsDG1) {
using GfxFamily = typename NEO::GfxFamilyMapper<gfxCoreFamily>::GfxFamily;
using L3_CONTROL = typename GfxFamily::L3_CONTROL;
auto &hardwareInfo = this->neoDevice->getHardwareInfo();
auto commandList = std::make_unique<WhiteBox<::L0::CommandListCoreFamily<gfxCoreFamily>>>();
commandList->initialize(device, NEO::EngineGroupType::Copy);
LinearStream *cmdStream = commandList->commandContainer.getCommandStream();
uint64_t gpuAddress = 0x1200;
void *buffer = reinterpret_cast<void *>(gpuAddress);
size_t size = 0x1000;
uint64_t postSyncAddress = 0x1200;
NEO::MockGraphicsAllocation mockAllocation(buffer, gpuAddress, size);
NEO::SvmAllocationData allocData(0);
allocData.size = size;
allocData.gpuAllocations.addAllocation(&mockAllocation);
device->getDriverHandle()->getSvmAllocsManager()->insertSVMAlloc(allocData);
L3RangesVec ranges;
ranges.push_back(L3Range::fromAddressSizeWithPolicy(
gpuAddress, size,
GfxFamily::L3_FLUSH_ADDRESS_RANGE::
L3_FLUSH_EVICTION_POLICY_FLUSH_L3_WITH_EVICTION));
NEO::flushGpuCache<GfxFamily>(cmdStream, ranges, postSyncAddress,
hardwareInfo);
GenCmdList cmdList;
EXPECT_TRUE(FamilyType::PARSE::parseCommandBuffer(
cmdList, ptrOffset(cmdStream->getCpuBase(), 0), cmdStream->getUsed()));
auto itor = find<L3_CONTROL *>(cmdList.begin(), cmdList.end());
EXPECT_NE(cmdList.end(), itor);
}
HWTEST2_F(CacheFlushTests, GivenCommandStreamWithMultipleL3RangeAndUsePostSyncIsSetToTrueWhenGetSizeNeededToFlushGpuCacheIsCalledThenCorrectSizeIsReturned, IsDG1) {
using GfxFamily = typename NEO::GfxFamilyMapper<gfxCoreFamily>::GfxFamily;
using L3_CONTROL = typename GfxFamily::L3_CONTROL;
uint64_t gpuAddress = 0x1200;
size_t size = 0x1000;
L3RangesVec ranges;
ranges.push_back(L3Range::fromAddressSizeWithPolicy(
gpuAddress, size,
GfxFamily::L3_FLUSH_ADDRESS_RANGE::
L3_FLUSH_EVICTION_POLICY_FLUSH_L3_WITH_EVICTION));
EXPECT_NE(0u, ranges.size());
size_t ret = NEO::getSizeNeededToFlushGpuCache<GfxFamily>(ranges, true);
size_t expected = ranges.size() * sizeof(L3_CONTROL);
EXPECT_EQ(ret, expected);
}
HWTEST2_F(CacheFlushTests, GivenCommandStreamWithMultipleL3RangeAndUsePostSyncIsSetToFalseWhenGetSizeNeededToFlushGpuCacheIsCalledThenCorrectSizeIsReturned, IsDG1) {
using GfxFamily = typename NEO::GfxFamilyMapper<gfxCoreFamily>::GfxFamily;
using L3_CONTROL = typename GfxFamily::L3_CONTROL;
uint64_t gpuAddress = 0x1200;
size_t size = 0x1000;
L3RangesVec ranges;
ranges.push_back(L3Range::fromAddressSizeWithPolicy(
gpuAddress, size,
GfxFamily::L3_FLUSH_ADDRESS_RANGE::
L3_FLUSH_EVICTION_POLICY_FLUSH_L3_WITH_EVICTION));
EXPECT_NE(0u, ranges.size());
size_t ret = NEO::getSizeNeededToFlushGpuCache<GfxFamily>(ranges, false);
size_t expected = ranges.size() * sizeof(L3_CONTROL);
EXPECT_EQ(ret, expected);
}
} // namespace ult
} // namespace L0