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https://github.com/intel/compute-runtime.git
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Improve build time: command_queue tests
Change-Id: I22f7788bacd4a36488d5b6d56bae79b1f4788625 Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
This commit is contained in:
Maciej Dziuban
@@ -1,387 +0,0 @@
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/*
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* Copyright (c) 2017 - 2018, Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "runtime/built_ins/built_ins.h"
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#include "runtime/built_ins/builtins_dispatch_builder.h"
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#include "reg_configs_common.h"
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#include "runtime/helpers/dispatch_info.h"
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#include "runtime/memory_manager/memory_constants.h"
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#include "unit_tests/command_queue/enqueue_copy_buffer_rect_fixture.h"
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#include "unit_tests/gen_common/gen_commands_common_validation.h"
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#include "test.h"
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using namespace OCLRT;
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const size_t EnqueueCopyBufferRectTest::BufferRect::sizeInBytes = 100 * 100 * 100 * sizeof(cl_char);
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HWTEST_F(EnqueueCopyBufferRectTest, null_src_mem_object) {
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auto retVal = CL_SUCCESS;
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size_t srcOrigin[] = {0, 0, 0};
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size_t dstOrigin[] = {0, 0, 0};
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size_t region[] = {1, 1, 0};
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retVal = clEnqueueCopyBufferRect(
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pCmdQ,
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nullptr,
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dstBuffer,
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srcOrigin,
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dstOrigin,
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region,
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10,
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0,
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10,
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0,
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0,
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nullptr,
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nullptr);
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EXPECT_EQ(CL_INVALID_MEM_OBJECT, retVal);
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}
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HWTEST_F(EnqueueCopyBufferRectTest, null_dst_mem_object) {
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auto retVal = CL_SUCCESS;
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size_t srcOrigin[] = {0, 0, 0};
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size_t dstOrigin[] = {0, 0, 0};
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size_t region[] = {1, 1, 0};
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retVal = clEnqueueCopyBufferRect(
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pCmdQ,
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srcBuffer,
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nullptr,
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srcOrigin,
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dstOrigin,
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region,
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10,
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0,
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10,
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0,
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0,
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nullptr,
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nullptr);
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EXPECT_EQ(CL_INVALID_MEM_OBJECT, retVal);
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}
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HWTEST_F(EnqueueCopyBufferRectTest, returnSuccess) {
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auto retVal = CL_SUCCESS;
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size_t srcOrigin[] = {0, 0, 0};
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size_t dstOrigin[] = {0, 0, 0};
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size_t region[] = {1, 1, 1};
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retVal = clEnqueueCopyBufferRect(
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pCmdQ,
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srcBuffer,
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dstBuffer,
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srcOrigin,
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dstOrigin,
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region,
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10,
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0,
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10,
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0,
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0,
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nullptr,
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nullptr);
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EXPECT_EQ(CL_SUCCESS, retVal);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, alignsToCSR) {
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//this test case assumes IOQ
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auto &csr = pDevice->getUltCommandStreamReceiver<FamilyType>();
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csr.taskCount = pCmdQ->taskCount + 100;
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csr.taskLevel = pCmdQ->taskLevel + 50;
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enqueueCopyBufferRect2D<FamilyType>();
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EXPECT_EQ(csr.peekTaskCount(), pCmdQ->taskCount);
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EXPECT_EQ(csr.peekTaskLevel(), pCmdQ->taskLevel + 1);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 2D_GPGPUWalker) {
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typedef typename FamilyType::GPGPU_WALKER GPGPU_WALKER;
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enqueueCopyBufferRect2D<FamilyType>();
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auto *cmd = (GPGPU_WALKER *)cmdWalker;
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ASSERT_NE(nullptr, cmd);
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// Verify GPGPU_WALKER parameters
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EXPECT_NE(0u, cmd->getThreadGroupIdXDimension());
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EXPECT_NE(0u, cmd->getThreadGroupIdYDimension());
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EXPECT_EQ(1u, cmd->getThreadGroupIdZDimension());
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EXPECT_NE(0u, cmd->getRightExecutionMask());
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EXPECT_NE(0u, cmd->getBottomExecutionMask());
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EXPECT_EQ(GPGPU_WALKER::SIMD_SIZE_SIMD32, cmd->getSimdSize());
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EXPECT_NE(0u, cmd->getIndirectDataLength());
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EXPECT_EQ(0u, cmd->getIndirectDataLength() % GPGPU_WALKER::INDIRECTDATASTARTADDRESS_ALIGN_SIZE);
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EXPECT_FALSE(cmd->getIndirectParameterEnable());
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// Compute the SIMD lane mask
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size_t simd =
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cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16 : 8;
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uint64_t simdMask = (1ull << simd) - 1;
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// Mask off lanes based on the execution masks
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auto laneMaskRight = cmd->getRightExecutionMask() & simdMask;
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auto lanesPerThreadX = 0;
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while (laneMaskRight) {
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lanesPerThreadX += laneMaskRight & 1;
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laneMaskRight >>= 1;
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}
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 2D_bumpsTaskLevel) {
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auto taskLevelBefore = pCmdQ->taskLevel;
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enqueueCopyBufferRect2D<FamilyType>();
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EXPECT_GT(pCmdQ->taskLevel, taskLevelBefore);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 2D_addsCommands) {
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auto usedCmdBufferBefore = pCS->getUsed();
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enqueueCopyBufferRect2D<FamilyType>();
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EXPECT_NE(usedCmdBufferBefore, pCS->getUsed());
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 2D_addsIndirectData) {
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auto dshBefore = pDSH->getUsed();
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auto iohBefore = pIOH->getUsed();
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auto sshBefore = pSSH->getUsed();
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enqueueCopyBufferRect2D<FamilyType>();
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// Extract the kernel used
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MultiDispatchInfo multiDispatchInfo;
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auto &builder = pCmdQ->getDevice().getExecutionEnvironment()->getBuiltIns()->getBuiltinDispatchInfoBuilder(EBuiltInOps::CopyBufferRect,
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pCmdQ->getContext(), pCmdQ->getDevice());
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ASSERT_NE(nullptr, &builder);
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BuiltinDispatchInfoBuilder::BuiltinOpParams dc;
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dc.srcMemObj = srcBuffer;
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dc.dstMemObj = dstBuffer;
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dc.srcOffset = {0, 0, 0};
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dc.dstOffset = {0, 0, 0};
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dc.size = {50, 50, 1};
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dc.srcRowPitch = rowPitch;
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dc.srcSlicePitch = slicePitch;
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dc.dstRowPitch = rowPitch;
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dc.dstSlicePitch = slicePitch;
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builder.buildDispatchInfos(multiDispatchInfo, dc);
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EXPECT_NE(0u, multiDispatchInfo.size());
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auto kernel = multiDispatchInfo.begin()->getKernel();
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ASSERT_NE(nullptr, kernel);
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EXPECT_NE(dshBefore, pDSH->getUsed());
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EXPECT_NE(iohBefore, pIOH->getUsed());
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if (kernel->requiresSshForBuffers()) {
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EXPECT_NE(sshBefore, pSSH->getUsed());
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}
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 2D_LoadRegisterImmediateL3CNTLREG) {
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enqueueCopyBufferRect2D<FamilyType>();
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validateL3Programming<FamilyType>(cmdList, itorWalker);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, When2DEnqueueIsDoneThenStateBaseAddressIsProperlyProgrammed) {
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enqueueCopyBufferRect2D<FamilyType>();
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validateStateBaseAddress<FamilyType>(this->pDevice->getCommandStreamReceiver().getMemoryManager()->getInternalHeapBaseAddress(),
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pDSH, pIOH, pSSH, itorPipelineSelect, itorWalker, cmdList, 0llu);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 2D_MediaInterfaceDescriptorLoad) {
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typedef typename FamilyType::MEDIA_INTERFACE_DESCRIPTOR_LOAD MEDIA_INTERFACE_DESCRIPTOR_LOAD;
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typedef typename FamilyType::INTERFACE_DESCRIPTOR_DATA INTERFACE_DESCRIPTOR_DATA;
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enqueueCopyBufferRect2D<FamilyType>();
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auto *cmd = (MEDIA_INTERFACE_DESCRIPTOR_LOAD *)cmdMediaInterfaceDescriptorLoad;
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ASSERT_NE(nullptr, cmd);
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// Verify we have a valid length -- multiple of INTERFACE_DESCRIPTOR_DATAs
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EXPECT_EQ(0u, cmd->getInterfaceDescriptorTotalLength() % sizeof(INTERFACE_DESCRIPTOR_DATA));
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// Validate the start address
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size_t alignmentStartAddress = 64 * sizeof(uint8_t);
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EXPECT_EQ(0u, cmd->getInterfaceDescriptorDataStartAddress() % alignmentStartAddress);
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// Validate the length
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EXPECT_NE(0u, cmd->getInterfaceDescriptorTotalLength());
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size_t alignmentTotalLength = 32 * sizeof(uint8_t);
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EXPECT_EQ(0u, cmd->getInterfaceDescriptorTotalLength() % alignmentTotalLength);
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// Generically validate this command
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FamilyType::PARSE::template validateCommand<MEDIA_INTERFACE_DESCRIPTOR_LOAD *>(cmdList.begin(), itorMediaInterfaceDescriptorLoad);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 2D_InterfaceDescriptorData) {
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typedef typename FamilyType::MEDIA_INTERFACE_DESCRIPTOR_LOAD MEDIA_INTERFACE_DESCRIPTOR_LOAD;
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typedef typename FamilyType::STATE_BASE_ADDRESS STATE_BASE_ADDRESS;
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typedef typename FamilyType::INTERFACE_DESCRIPTOR_DATA INTERFACE_DESCRIPTOR_DATA;
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enqueueCopyBufferRect2D<FamilyType>();
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auto *cmdSBA = (STATE_BASE_ADDRESS *)cmdStateBaseAddress;
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auto &IDD = *(INTERFACE_DESCRIPTOR_DATA *)cmdInterfaceDescriptorData;
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// Validate the kernel start pointer. Technically, a kernel can start at address 0 but let's force a value.
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auto kernelStartPointer = ((uint64_t)IDD.getKernelStartPointerHigh() << 32) + IDD.getKernelStartPointer();
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EXPECT_LE(kernelStartPointer, cmdSBA->getInstructionBufferSize() * MemoryConstants::pageSize);
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EXPECT_NE(0u, IDD.getNumberOfThreadsInGpgpuThreadGroup());
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EXPECT_NE(0u, IDD.getCrossThreadConstantDataReadLength());
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EXPECT_NE(0u, IDD.getConstantIndirectUrbEntryReadLength());
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 2D_PipelineSelect) {
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enqueueCopyBufferRect2D<FamilyType>();
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int numCommands = getNumberOfPipelineSelectsThatEnablePipelineSelect<FamilyType>();
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EXPECT_EQ(1, numCommands);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 2D_MediaVFEState) {
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enqueueCopyBufferRect2D<FamilyType>();
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validateMediaVFEState<FamilyType>(&pDevice->getHardwareInfo(), cmdMediaVfeState, cmdList, itorMediaVfeState);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 3D_GPGPUWalker) {
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typedef typename FamilyType::GPGPU_WALKER GPGPU_WALKER;
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enqueueCopyBufferRect3D<FamilyType>();
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auto *cmd = (GPGPU_WALKER *)cmdWalker;
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ASSERT_NE(nullptr, cmd);
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// Verify GPGPU_WALKER parameters
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EXPECT_NE(0u, cmd->getThreadGroupIdXDimension());
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EXPECT_NE(0u, cmd->getThreadGroupIdYDimension());
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EXPECT_LT(1u, cmd->getThreadGroupIdZDimension());
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EXPECT_NE(0u, cmd->getRightExecutionMask());
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EXPECT_NE(0u, cmd->getBottomExecutionMask());
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EXPECT_EQ(GPGPU_WALKER::SIMD_SIZE_SIMD32, cmd->getSimdSize());
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EXPECT_NE(0u, cmd->getIndirectDataLength());
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EXPECT_EQ(0u, cmd->getIndirectDataLength() % GPGPU_WALKER::INDIRECTDATASTARTADDRESS_ALIGN_SIZE);
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EXPECT_FALSE(cmd->getIndirectParameterEnable());
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// Compute the SIMD lane mask
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size_t simd =
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cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD32 ? 32 : cmd->getSimdSize() == GPGPU_WALKER::SIMD_SIZE_SIMD16 ? 16 : 8;
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uint64_t simdMask = (1ull << simd) - 1;
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// Mask off lanes based on the execution masks
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auto laneMaskRight = cmd->getRightExecutionMask() & simdMask;
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auto lanesPerThreadX = 0;
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while (laneMaskRight) {
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lanesPerThreadX += laneMaskRight & 1;
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laneMaskRight >>= 1;
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}
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//auto numWorkItems = ( ( cmd->getThreadWidthCounterMaximum() - 1 ) * simd + lanesPerThreadX ) * cmd->getThreadGroupIdXDimension();
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//EXPECT_EQ( expectedWorkItems, numWorkItems );
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 3D_bumpsTaskLevel) {
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auto taskLevelBefore = pCmdQ->taskLevel;
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enqueueCopyBufferRect3D<FamilyType>();
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EXPECT_GT(pCmdQ->taskLevel, taskLevelBefore);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 3D_addsCommands) {
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auto usedCmdBufferBefore = pCS->getUsed();
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enqueueCopyBufferRect3D<FamilyType>();
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EXPECT_NE(usedCmdBufferBefore, pCS->getUsed());
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 3D_addsIndirectData) {
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auto usedIndirectHeapBefore = pDSH->getUsed();
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enqueueCopyBufferRect3D<FamilyType>();
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EXPECT_NE(usedIndirectHeapBefore, pDSH->getUsed());
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 3D_LoadRegisterImmediateL3CNTLREG) {
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enqueueCopyBufferRect3D<FamilyType>();
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validateL3Programming<FamilyType>(cmdList, itorWalker);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, When3DEnqueueIsDoneThenStateBaseAddressIsProperlyProgrammed) {
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enqueueCopyBufferRect3D<FamilyType>();
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validateStateBaseAddress<FamilyType>(this->pDevice->getCommandStreamReceiver().getMemoryManager()->getInternalHeapBaseAddress(),
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pDSH, pIOH, pSSH, itorPipelineSelect, itorWalker, cmdList, 0llu);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 3D_MediaInterfaceDescriptorLoad) {
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typedef typename FamilyType::MEDIA_INTERFACE_DESCRIPTOR_LOAD MEDIA_INTERFACE_DESCRIPTOR_LOAD;
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typedef typename FamilyType::INTERFACE_DESCRIPTOR_DATA INTERFACE_DESCRIPTOR_DATA;
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enqueueCopyBufferRect3D<FamilyType>();
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auto *cmd = (MEDIA_INTERFACE_DESCRIPTOR_LOAD *)cmdMediaInterfaceDescriptorLoad;
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ASSERT_NE(nullptr, cmd);
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// Verify we have a valid length -- multiple of INTERFACE_DESCRIPTOR_DATAs
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EXPECT_EQ(0u, cmd->getInterfaceDescriptorTotalLength() % sizeof(INTERFACE_DESCRIPTOR_DATA));
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// Validate the start address
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size_t alignmentStartAddress = 64 * sizeof(uint8_t);
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EXPECT_EQ(0u, cmd->getInterfaceDescriptorDataStartAddress() % alignmentStartAddress);
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// Validate the length
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EXPECT_NE(0u, cmd->getInterfaceDescriptorTotalLength());
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size_t alignmentTotalLength = 32 * sizeof(uint8_t);
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EXPECT_EQ(0u, cmd->getInterfaceDescriptorTotalLength() % alignmentTotalLength);
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// Generically validate this command
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FamilyType::PARSE::template validateCommand<MEDIA_INTERFACE_DESCRIPTOR_LOAD *>(cmdList.begin(), itorMediaInterfaceDescriptorLoad);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 3D_InterfaceDescriptorData) {
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typedef typename FamilyType::MEDIA_INTERFACE_DESCRIPTOR_LOAD MEDIA_INTERFACE_DESCRIPTOR_LOAD;
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typedef typename FamilyType::STATE_BASE_ADDRESS STATE_BASE_ADDRESS;
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typedef typename FamilyType::INTERFACE_DESCRIPTOR_DATA INTERFACE_DESCRIPTOR_DATA;
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enqueueCopyBufferRect3D<FamilyType>();
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auto *cmdSBA = (STATE_BASE_ADDRESS *)cmdStateBaseAddress;
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auto &IDD = *(INTERFACE_DESCRIPTOR_DATA *)cmdInterfaceDescriptorData;
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// Validate the kernel start pointer. Technically, a kernel can start at address 0 but let's force a value.
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auto kernelStartPointer = ((uint64_t)IDD.getKernelStartPointerHigh() << 32) + IDD.getKernelStartPointer();
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EXPECT_LE(kernelStartPointer, cmdSBA->getInstructionBufferSize() * MemoryConstants::pageSize);
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EXPECT_NE(0u, IDD.getNumberOfThreadsInGpgpuThreadGroup());
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EXPECT_NE(0u, IDD.getCrossThreadConstantDataReadLength());
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EXPECT_NE(0u, IDD.getConstantIndirectUrbEntryReadLength());
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 3D_PipelineSelect) {
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enqueueCopyBufferRect3D<FamilyType>();
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int numCommands = getNumberOfPipelineSelectsThatEnablePipelineSelect<FamilyType>();
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EXPECT_EQ(1, numCommands);
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}
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HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueCopyBufferRectTest, 3D_MediaVFEState) {
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enqueueCopyBufferRect3D<FamilyType>();
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validateMediaVFEState<FamilyType>(&pDevice->getHardwareInfo(), cmdMediaVfeState, cmdList, itorMediaVfeState);
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}
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