Optimize number of calls for pipe control post syncs

Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
This commit is contained in:
Zbigniew Zdanowicz
2021-11-10 15:17:52 +00:00
committed by Compute-Runtime-Automation
parent 620484010d
commit 78609cd9f5
6 changed files with 27 additions and 38 deletions

View File

@@ -119,17 +119,6 @@ EngineGroupType HwHelperHw<Family>::getEngineGroupType(aub_stream::EngineType en
}
}
template <>
void MemorySynchronizationCommands<Family>::setPipeControlWA(void *&commandsBuffer, uint64_t gpuAddress, const HardwareInfo &hwInfo) {
if (HwInfoConfig::get(hwInfo.platform.eProductFamily)->pipeControlWARequired(hwInfo)) {
PIPE_CONTROL cmd = Family::cmdInitPipeControl;
cmd.setCommandStreamerStallEnable(true);
*reinterpret_cast<PIPE_CONTROL *>(commandsBuffer) = cmd;
commandsBuffer = ptrOffset(commandsBuffer, sizeof(PIPE_CONTROL));
}
}
template <>
std::string HwHelperHw<Family>::getExtensions() const {
return "cl_intel_subgroup_local_block_io ";

View File

@@ -24,15 +24,6 @@ SipKernelType HwHelperHw<Family>::getSipKernelType(bool debuggingActive) const {
return DebugManager.flags.UseBindlessDebugSip.get() ? SipKernelType::DbgBindless : SipKernelType::DbgCsrLocal;
}
template <>
void MemorySynchronizationCommands<Family>::setPipeControlWA(void *&commandsBuffer, uint64_t gpuAddress, const HardwareInfo &hwInfo) {
PIPE_CONTROL cmd = Family::cmdInitPipeControl;
cmd.setCommandStreamerStallEnable(true);
*reinterpret_cast<PIPE_CONTROL *>(commandsBuffer) = cmd;
commandsBuffer = ptrOffset(commandsBuffer, sizeof(PIPE_CONTROL));
}
template <>
uint32_t HwHelperHw<Family>::getMetricsLibraryGenId() const {
return static_cast<uint32_t>(MetricsLibraryApi::ClientGen::Gen9);

View File

@@ -436,7 +436,7 @@ struct MemorySynchronizationCommands {
PipeControlArgs &args);
static void setPostSyncExtraProperties(PipeControlArgs &args, const HardwareInfo &hwInfo);
static void setPipeControl(PIPE_CONTROL &pipeControl, PipeControlArgs &args);
static void setPipeControlWAFlags(PIPE_CONTROL &pipeControl);
static void addPipeControlWA(LinearStream &commandStream, uint64_t gpuAddress, const HardwareInfo &hwInfo);
static void setPipeControlWA(void *&commandsBuffer, uint64_t gpuAddress, const HardwareInfo &hwInfo);
@@ -445,6 +445,8 @@ struct MemorySynchronizationCommands {
static void setAdditionalSynchronization(void *&commandsBuffer, uint64_t gpuAddress, const HardwareInfo &hwInfo);
static void addPipeControl(LinearStream &commandStream, PipeControlArgs &args);
static void setPipeControl(PIPE_CONTROL &pipeControl, PipeControlArgs &args);
static void addPipeControlWithCSStallOnly(LinearStream &commandStream);
static bool isDcFlushAllowed();

View File

@@ -277,14 +277,27 @@ void MemorySynchronizationCommands<GfxFamily>::addPipeControlWithPostSync(
template <typename GfxFamily>
void MemorySynchronizationCommands<GfxFamily>::addPipeControlWA(LinearStream &commandStream, uint64_t gpuAddress, const HardwareInfo &hwInfo) {
size_t requiredSize = MemorySynchronizationCommands<GfxFamily>::getSizeForPipeControlWA(hwInfo);
if (requiredSize > 0) {
void *commandBuffer = commandStream.getSpace(requiredSize);
setPipeControlWA(commandBuffer, gpuAddress, hwInfo);
}
template <typename GfxFamily>
void MemorySynchronizationCommands<GfxFamily>::setPipeControlWA(void *&commandsBuffer, uint64_t gpuAddress, const HardwareInfo &hwInfo) {
if (MemorySynchronizationCommands<GfxFamily>::isPipeControlWArequired(hwInfo)) {
PIPE_CONTROL cmd = GfxFamily::cmdInitPipeControl;
MemorySynchronizationCommands<GfxFamily>::setPipeControlWAFlags(cmd);
*reinterpret_cast<PIPE_CONTROL *>(commandsBuffer) = cmd;
commandsBuffer = ptrOffset(commandsBuffer, sizeof(PIPE_CONTROL));
MemorySynchronizationCommands<GfxFamily>::setAdditionalSynchronization(commandsBuffer, gpuAddress, hwInfo);
}
}
template <typename GfxFamily>
void MemorySynchronizationCommands<GfxFamily>::addAdditionalSynchronization(LinearStream &commandStream, uint64_t gpuAddress, const HardwareInfo &hwInfo) {
size_t requiredSize = MemorySynchronizationCommands<GfxFamily>::getSizeForSingleAdditionalSynchronization(hwInfo);
void *commandBuffer = commandStream.getSpace(requiredSize);
setAdditionalSynchronization(commandBuffer, gpuAddress, hwInfo);
}
template <typename GfxFamily>

View File

@@ -100,10 +100,6 @@ aub_stream::MMIOList HwHelperHw<GfxFamily>::getExtraMmioList(const HardwareInfo
return {};
}
template <typename GfxFamily>
inline void MemorySynchronizationCommands<GfxFamily>::setPipeControlWA(void *&commandsBuffer, uint64_t gpuAddress, const HardwareInfo &hwInfo) {
}
template <typename GfxFamily>
inline void MemorySynchronizationCommands<GfxFamily>::setPostSyncExtraProperties(PipeControlArgs &args, const HardwareInfo &hwInfo) {
}
@@ -119,6 +115,11 @@ inline void MemorySynchronizationCommands<GfxFamily>::setPipeControlExtraPropert
template <typename GfxFamily>
bool MemorySynchronizationCommands<GfxFamily>::isPipeControlWArequired(const HardwareInfo &hwInfo) { return false; }
template <typename GfxFamily>
inline void MemorySynchronizationCommands<GfxFamily>::setPipeControlWAFlags(PIPE_CONTROL &pipeControl) {
pipeControl.setCommandStreamerStallEnable(true);
}
template <typename GfxFamily>
bool HwHelperHw<GfxFamily>::additionalPipeControlArgsRequired() const {
return false;

View File

@@ -118,16 +118,9 @@ std::string HwHelperHw<Family>::getExtensions() const {
}
template <>
void MemorySynchronizationCommands<Family>::setPipeControlWA(void *&commandsBuffer, uint64_t gpuAddress, const HardwareInfo &hwInfo) {
if (DebugManager.flags.DisablePipeControlPrecedingPostSyncCommand.get() == 1) {
if (hwInfo.featureTable.ftrLocalMemory) {
PIPE_CONTROL cmd = Family::cmdInitPipeControl;
cmd.setCommandStreamerStallEnable(true);
cmd.setHdcPipelineFlush(true);
*reinterpret_cast<PIPE_CONTROL *>(commandsBuffer) = cmd;
commandsBuffer = ptrOffset(commandsBuffer, sizeof(PIPE_CONTROL));
}
}
void MemorySynchronizationCommands<Family>::setPipeControlWAFlags(PIPE_CONTROL &pipeControl) {
pipeControl.setCommandStreamerStallEnable(true);
pipeControl.setHdcPipelineFlush(true);
}
template <>