diff --git a/level_zero/core/test/aub_tests/debugger/debugger_aub_tests.cpp b/level_zero/core/test/aub_tests/debugger/debugger_aub_tests.cpp index d3cf995c35..46aea89ecc 100644 --- a/level_zero/core/test/aub_tests/debugger/debugger_aub_tests.cpp +++ b/level_zero/core/test/aub_tests/debugger/debugger_aub_tests.cpp @@ -115,8 +115,8 @@ HWTEST2_F(DebuggerSingleAddressSpaceAub, GivenSingleAddressSpaceWhenCmdListIsExe uint32_t low = sbaAddress & 0xffffffff; uint32_t high = (sbaAddress >> 32) & 0xffffffff; - expectMMIO(RegisterOffsets::csGprR15, low); - expectMMIO(RegisterOffsets::csGprR15 + 4, high); + expectMMIO(DebuggerRegisterOffsets::csGprR15, low); + expectMMIO(DebuggerRegisterOffsets::csGprR15 + 4, high); auto instructionHeapBaseAddress = memoryManager->getInternalHeapBaseAddress(rootDeviceIndex, memoryManager->isLocalMemoryUsedForIsa(rootDeviceIndex)); diff --git a/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_2.cpp b/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_2.cpp index 794d7ffd4c..63ad75224c 100644 --- a/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_2.cpp +++ b/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_2.cpp @@ -150,7 +150,7 @@ HWTEST2_F(singleAddressSpaceModeTest, givenImmediateCommandListWhenExecutingWith MI_LOAD_REGISTER_IMM *miLoad = genCmdCast(*miLoadImm[i]); ASSERT_NE(nullptr, miLoad); - if (miLoad->getRegisterOffset() == RegisterOffsets::csGprR15) { + if (miLoad->getRegisterOffset() == DebuggerRegisterOffsets::csGprR15) { gpr15Found = true; break; } @@ -197,7 +197,7 @@ HWTEST2_F(singleAddressSpaceModeTest, givenUseCsrImmediateSubmissionEnabledAndSh MI_LOAD_REGISTER_IMM *miLoad = genCmdCast(*miLoadImm[i]); ASSERT_NE(nullptr, miLoad); - if (miLoad->getRegisterOffset() == RegisterOffsets::csGprR15) { + if (miLoad->getRegisterOffset() == DebuggerRegisterOffsets::csGprR15) { gpr15Found = true; break; } diff --git a/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_sba_tracking.cpp b/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_sba_tracking.cpp index ab81ac4a35..81ac052205 100644 --- a/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_sba_tracking.cpp +++ b/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_sba_tracking.cpp @@ -447,11 +447,11 @@ HWTEST2_F(L0DebuggerSingleAddressSpace, givenDebuggingEnabledWhenCommandListIsEx MI_LOAD_REGISTER_IMM *miLoad = genCmdCast(*miLoadImm[i]); ASSERT_NE(nullptr, miLoad); - if (miLoad->getRegisterOffset() == RegisterOffsets::csGprR15) { + if (miLoad->getRegisterOffset() == DebuggerRegisterOffsets::csGprR15) { gpr15RegisterCount++; gprMiLoadindex = i; } - if (miLoad->getRegisterOffset() == RegisterOffsets::csGprR15 + 4) { + if (miLoad->getRegisterOffset() == DebuggerRegisterOffsets::csGprR15 + 4) { gpr15RegisterCount++; } } @@ -464,11 +464,11 @@ HWTEST2_F(L0DebuggerSingleAddressSpace, givenDebuggingEnabledWhenCommandListIsEx uint32_t high = (sbaGpuVa >> 32) & 0xffffffff; MI_LOAD_REGISTER_IMM *miLoad = genCmdCast(*miLoadImm[gprMiLoadindex]); - EXPECT_EQ(RegisterOffsets::csGprR15, miLoad->getRegisterOffset()); + EXPECT_EQ(DebuggerRegisterOffsets::csGprR15, miLoad->getRegisterOffset()); EXPECT_EQ(low, miLoad->getDataDword()); miLoad = genCmdCast(*miLoadImm[gprMiLoadindex + 1]); - EXPECT_EQ(RegisterOffsets::csGprR15 + 4, miLoad->getRegisterOffset()); + EXPECT_EQ(DebuggerRegisterOffsets::csGprR15 + 4, miLoad->getRegisterOffset()); EXPECT_EQ(high, miLoad->getDataDword()); for (auto i = 0u; i < numCommandLists; i++) { diff --git a/level_zero/tools/source/debug/windows/debug_session.cpp b/level_zero/tools/source/debug/windows/debug_session.cpp index c6af484f26..611ec23450 100644 --- a/level_zero/tools/source/debug/windows/debug_session.cpp +++ b/level_zero/tools/source/debug/windows/debug_session.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021-2023 Intel Corporation + * Copyright (C) 2021-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -691,7 +691,7 @@ ze_result_t DebugSessionWindows::readSbaBuffer(EuThread::ThreadId threadId, NEO: void DebugSessionWindows::getSbaBufferGpuVa(uint64_t &gpuVa) { KM_ESCAPE_INFO escapeInfo = {}; escapeInfo.KmEuDbgL0EscapeInfo.EscapeActionType = DBGUMD_ACTION_READ_MMIO; - escapeInfo.KmEuDbgL0EscapeInfo.MmioReadParams.MmioOffset = RegisterOffsets::csGprR15; + escapeInfo.KmEuDbgL0EscapeInfo.MmioReadParams.MmioOffset = DebuggerRegisterOffsets::csGprR15; escapeInfo.KmEuDbgL0EscapeInfo.MmioReadParams.RegisterOutBufferPtr = reinterpret_cast(&gpuVa); auto status = runEscape(escapeInfo); diff --git a/shared/source/debugger/debugger_l0.inl b/shared/source/debugger/debugger_l0.inl index b36c0115f0..a04c72f504 100644 --- a/shared/source/debugger/debugger_l0.inl +++ b/shared/source/debugger/debugger_l0.inl @@ -129,12 +129,12 @@ void DebuggerL0Hw::programSbaAddressLoad(NEO::LinearStream &cmdStream uint32_t high = (sbaGpuVa >> 32) & 0xffffffff; NEO::LriHelper::program(&cmdStream, - RegisterOffsets::csGprR15, + DebuggerRegisterOffsets::csGprR15, low, true); NEO::LriHelper::program(&cmdStream, - RegisterOffsets::csGprR15 + 4, + DebuggerRegisterOffsets::csGprR15 + 4, high, true); } diff --git a/shared/source/debugger/debugger_l0_tgllp_and_later.inl b/shared/source/debugger/debugger_l0_tgllp_and_later.inl index 813d2fd22a..e1f6eaeff9 100644 --- a/shared/source/debugger/debugger_l0_tgllp_and_later.inl +++ b/shared/source/debugger/debugger_l0_tgllp_and_later.inl @@ -77,7 +77,7 @@ void DebuggerL0Hw::programSbaTrackingCommandsSingleAddressSpace(NEO:: // Store SBA field offset to R0 NEO::EncodeSetMMIO::encodeIMM(cmdStream, RegisterOffsets::csGprR0, static_cast(pair.first), true); // Add GPR0 to GPR15, store result in GPR1 - NEO::EncodeMath::addition(cmdStream, AluRegisters::gpr0, AluRegisters::gpr15, AluRegisters::gpr1); + NEO::EncodeMath::addition(cmdStream, AluRegisters::gpr0, static_cast(DebuggerAluRegisters::gpr15), AluRegisters::gpr1); // Cmds to store dest address - from GPR auto miStoreRegMemLow = cmdStream.getSpaceForCmd(); diff --git a/shared/source/helpers/register_offsets.h b/shared/source/helpers/register_offsets.h index bfe8bbc4ee..98db37aa98 100644 --- a/shared/source/helpers/register_offsets.h +++ b/shared/source/helpers/register_offsets.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2019-2023 Intel Corporation + * Copyright (C) 2019-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -40,7 +40,6 @@ inline constexpr uint32_t csGprR11 = 0x2658; inline constexpr uint32_t csGprR12 = 0x2660; inline constexpr uint32_t csGprR13 = 0x2668; inline constexpr uint32_t csGprR14 = 0x2670; -inline constexpr uint32_t csGprR15 = 0x2678; inline constexpr uint32_t csPredicateResult = 0x2418; inline constexpr uint32_t csPredicateResult2 = 0x23BC; @@ -53,6 +52,10 @@ inline constexpr uint32_t globalTimestampLdw = 0x2358; inline constexpr uint32_t globalTimestampUn = 0x235c; } // namespace RegisterOffsets +namespace DebuggerRegisterOffsets { +inline constexpr uint32_t csGprR15 = 0x2678; +} // namespace DebuggerRegisterOffsets + // Alu opcodes enum class AluRegisters : uint32_t { opcodeNone = 0x000, @@ -86,7 +89,6 @@ enum class AluRegisters : uint32_t { gpr12 = 0xC, gpr13 = 0xD, gpr14 = 0xE, - gpr15 = 0xF, srca = 0x20, srcb = 0x21, @@ -94,3 +96,7 @@ enum class AluRegisters : uint32_t { zf = 0x32, cf = 0x33 }; + +enum class DebuggerAluRegisters : uint32_t { + gpr15 = 0xF +};