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Unify programming of partition registers

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Related-To: NEO-6262


Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
This commit is contained in:
Zbigniew Zdanowicz
2021-11-17 19:51:43 +00:00
committed by Compute-Runtime-Automation
parent 49d1e04800
commit 7ea0a11c0a
31 changed files with 225 additions and 74 deletions
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3
level_zero/core/source/cmdqueue/cmdqueue_hw.h
View File

@@ -52,6 +52,9 @@ struct CommandQueueHw : public CommandQueueImp {
bool getPreemptionCmdProgramming() override;
void patchCommands(CommandList &commandList, uint64_t scratchAddress);
size_t getPartitionProgrammingSize();
void programPartitionConfiguration(NEO::LinearStream &stream);
};
} // namespace L0

11
level_zero/core/source/cmdqueue/cmdqueue_hw.inl
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@@ -270,7 +270,7 @@ ze_result_t CommandQueueHw<gfxCoreFamily>::executeCommandLists(
linearStreamSizeEstimate += isCopyOnlyCommandQueue ? NEO::EncodeMiFlushDW<GfxFamily>::getMiFlushDwCmdSizeForDataWrite() : NEO::MemorySynchronizationCommands<GfxFamily>::getSizeForPipeControlWithPostSyncOperation(hwInfo);
if (partitionCount > 1) {
linearStreamSizeEstimate += sizeof(MI_LOAD_REGISTER_MEM) + sizeof(MI_LOAD_REGISTER_IMM);
linearStreamSizeEstimate += getPartitionProgrammingSize();
}
size_t alignedSize = alignUp<size_t>(linearStreamSizeEstimate, minCmdBufferPtrAlign);
@@ -420,14 +420,7 @@ ze_result_t CommandQueueHw<gfxCoreFamily>::executeCommandLists(
commandQueuePreemptionMode = statePreemption;
if (partitionCount > 1) {
uint64_t workPartitionAddress = csr->getWorkPartitionAllocationGpuAddress();
NEO::EncodeSetMMIO<GfxFamily>::encodeMEM(child,
NEO::PartitionRegisters<GfxFamily>::wparidCCSOffset,
workPartitionAddress);
NEO::EncodeSetMMIO<GfxFamily>::encodeIMM(child,
NEO::PartitionRegisters<GfxFamily>::addressOffsetCCSOffset,
CommonConstants::partitionAddressOffset,
true);
programPartitionConfiguration(child);
}
if (hFence) {

9
level_zero/core/source/cmdqueue/cmdqueue_hw_base.inl
View File

@@ -123,4 +123,13 @@ void CommandQueueHw<gfxCoreFamily>::patchCommands(CommandList &commandList, uint
UNRECOVERABLE_IF(!commandsToPatch.empty());
}
template <GFXCORE_FAMILY gfxCoreFamily>
size_t CommandQueueHw<gfxCoreFamily>::getPartitionProgrammingSize() {
return 0;
}
template <GFXCORE_FAMILY gfxCoreFamily>
void CommandQueueHw<gfxCoreFamily>::programPartitionConfiguration(NEO::LinearStream &stream) {
}
} // namespace L0

16
level_zero/core/source/cmdqueue/cmdqueue_xe_hp_core_and_later.inl
View File

@@ -153,4 +153,20 @@ void CommandQueueHw<gfxCoreFamily>::patchCommands(CommandList &commandList, uint
}
}
template <GFXCORE_FAMILY gfxCoreFamily>
size_t CommandQueueHw<gfxCoreFamily>::getPartitionProgrammingSize() {
using GfxFamily = typename NEO::GfxFamilyMapper<gfxCoreFamily>::GfxFamily;
return NEO::ImplicitScalingDispatch<GfxFamily>::getRegisterConfigurationSize();
}
template <GFXCORE_FAMILY gfxCoreFamily>
void CommandQueueHw<gfxCoreFamily>::programPartitionConfiguration(NEO::LinearStream &stream) {
using GfxFamily = typename NEO::GfxFamilyMapper<gfxCoreFamily>::GfxFamily;
uint64_t workPartitionAddress = csr->getWorkPartitionAllocationGpuAddress();
NEO::ImplicitScalingDispatch<GfxFamily>::dispatchRegisterConfiguration(stream,
workPartitionAddress,
CommonConstants::partitionAddressOffset);
}
} // namespace L0