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Unify programming of partition registers

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Related-To: NEO-6262


Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
This commit is contained in:
Zbigniew Zdanowicz
2021-11-17 19:51:43 +00:00
committed by Compute-Runtime-Automation
parent 49d1e04800
commit 7ea0a11c0a
31 changed files with 225 additions and 74 deletions
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2
shared/source/direct_submission/CMakeLists.txt
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@@ -12,6 +12,7 @@ set(NEO_CORE_DIRECT_SUBMISSION
${CMAKE_CURRENT_SOURCE_DIR}/direct_submission_controller.h
${CMAKE_CURRENT_SOURCE_DIR}/direct_submission_hw.h
${CMAKE_CURRENT_SOURCE_DIR}/direct_submission_hw.inl
${CMAKE_CURRENT_SOURCE_DIR}/direct_submission_bdw_and_later.inl
${CMAKE_CURRENT_SOURCE_DIR}/direct_submission_hw_diagnostic_mode.cpp
${CMAKE_CURRENT_SOURCE_DIR}/direct_submission_hw_diagnostic_mode.h
${CMAKE_CURRENT_SOURCE_DIR}/direct_submission_properties.h
@@ -19,6 +20,7 @@ set(NEO_CORE_DIRECT_SUBMISSION
if(SUPPORT_XEHP_AND_LATER)
list(APPEND NEO_CORE_DIRECT_SUBMISSION
${CMAKE_CURRENT_SOURCE_DIR}/direct_submission_xe_hp_core_and_later.inl
${CMAKE_CURRENT_SOURCE_DIR}/direct_submission_prefetcher_xe_hp_core_and_later.inl
${CMAKE_CURRENT_SOURCE_DIR}/direct_submission_prefetch_mitigation_xe_hp_core_and_later.inl
)

21
shared/source/direct_submission/direct_submission_bdw_and_later.inl Normal file
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@@ -0,0 +1,21 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/direct_submission/direct_submission_hw.h"
namespace NEO {
template <typename GfxFamily, typename Dispatcher>
inline void DirectSubmissionHw<GfxFamily, Dispatcher>::dispatchPartitionRegisterConfiguration() {
}
template <typename GfxFamily, typename Dispatcher>
inline size_t DirectSubmissionHw<GfxFamily, Dispatcher>::getSizePartitionRegisterConfigurationSection() {
return 0;
}
} // namespace NEO

3
shared/source/direct_submission/direct_submission_hw.h
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@@ -113,6 +113,9 @@ class DirectSubmissionHw {
uint64_t getCommandBufferPositionGpuAddress(void *position);
void dispatchPartitionRegisterConfiguration();
size_t getSizePartitionRegisterConfigurationSection();
void createDiagnostic();
void initDiagnostic(bool &submitOnInit);
MOCKABLE_VIRTUAL void performDiagnosticMode();

23
shared/source/direct_submission/direct_submission_hw.inl
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@@ -6,7 +6,6 @@
*/
#include "shared/source/command_container/command_encoder.h"
#include "shared/source/command_container/implicit_scaling.h"
#include "shared/source/command_stream/submissions_aggregator.h"
#include "shared/source/debug_settings/debug_settings_manager.h"
#include "shared/source/device/device.h"
@@ -148,16 +147,9 @@ bool DirectSubmissionHw<GfxFamily, Dispatcher>::initialize(bool submitOnInit) {
Dispatcher::dispatchPreemption(ringCommandStream);
if (this->partitionedMode) {
startBufferSize += (EncodeSetMMIO<GfxFamily>::sizeMEM +
EncodeSetMMIO<GfxFamily>::sizeIMM);
startBufferSize += getSizePartitionRegisterConfigurationSection();
dispatchPartitionRegisterConfiguration();
EncodeSetMMIO<GfxFamily>::encodeMEM(ringCommandStream,
PartitionRegisters<GfxFamily>::wparidCCSOffset,
this->workPartitionAllocation->getGpuAddress());
EncodeSetMMIO<GfxFamily>::encodeIMM(ringCommandStream,
PartitionRegisters<GfxFamily>::addressOffsetCCSOffset,
CommonConstants::partitionAddressOffset,
true);
this->partitionConfigSet = true;
}
if (workloadMode == 1) {
@@ -181,8 +173,7 @@ bool DirectSubmissionHw<GfxFamily, Dispatcher>::startRingBuffer() {
size_t startSize = getSizeSemaphoreSection();
if (!this->partitionConfigSet) {
startSize += (EncodeSetMMIO<GfxFamily>::sizeMEM +
EncodeSetMMIO<GfxFamily>::sizeIMM);
startSize += getSizePartitionRegisterConfigurationSection();
}
size_t requiredSize = startSize + getSizeDispatch() + getSizeEnd();
if (ringCommandStream.getAvailableSpace() < requiredSize) {
@@ -191,13 +182,7 @@ bool DirectSubmissionHw<GfxFamily, Dispatcher>::startRingBuffer() {
uint64_t gpuStartVa = getCommandBufferPositionGpuAddress(ringCommandStream.getSpace(0));
if (!this->partitionConfigSet) {
EncodeSetMMIO<GfxFamily>::encodeMEM(ringCommandStream,
PartitionRegisters<GfxFamily>::wparidCCSOffset,
this->workPartitionAllocation->getGpuAddress());
EncodeSetMMIO<GfxFamily>::encodeIMM(ringCommandStream,
PartitionRegisters<GfxFamily>::addressOffsetCCSOffset,
CommonConstants::partitionAddressOffset,
true);
dispatchPartitionRegisterConfiguration();
this->partitionConfigSet = true;
}

25
shared/source/direct_submission/direct_submission_xe_hp_core_and_later.inl Normal file
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@@ -0,0 +1,25 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_container/implicit_scaling.h"
#include "shared/source/direct_submission/direct_submission_hw.h"
namespace NEO {
template <typename GfxFamily, typename Dispatcher>
inline void DirectSubmissionHw<GfxFamily, Dispatcher>::dispatchPartitionRegisterConfiguration() {
ImplicitScalingDispatch<GfxFamily>::dispatchRegisterConfiguration(ringCommandStream,
this->workPartitionAllocation->getGpuAddress(),
CommonConstants::partitionAddressOffset);
}
template <typename GfxFamily, typename Dispatcher>
inline size_t DirectSubmissionHw<GfxFamily, Dispatcher>::getSizePartitionRegisterConfigurationSection() {
return ImplicitScalingDispatch<GfxFamily>::getRegisterConfigurationSize();
}
} // namespace NEO