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https://github.com/intel/compute-runtime.git
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performance: Signal inOrder counter with pipe control, part 5
When on DC flush platform resolve in order implicit dependency with pipe control. Related-To: NEO-13441 Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
This commit is contained in:
Lukasz Jobczyk
committed by
Compute-Runtime-Automation
Compute-Runtime-Automation
parent
9e5a52f689
commit
7ee8328c1d
@@ -2623,75 +2623,88 @@ void CommandListCoreFamily<gfxCoreFamily>::appendWaitOnInOrderDependency(std::sh
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NEO::EncodeBatchBufferStartOrEnd<GfxFamily>::programConditionalDataMemBatchBufferStart(*commandContainer.getCommandStream(), 0, gpuAddress, waitValue, NEO::CompareOperation::less, true, isQwordInOrderCounter(), isCopyOnly(copyOffloadOperation));
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} else {
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using MI_SEMAPHORE_WAIT = typename GfxFamily::MI_SEMAPHORE_WAIT;
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using MI_LOAD_REGISTER_IMM = typename GfxFamily::MI_LOAD_REGISTER_IMM;
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auto resolveDependenciesViaPipeControls = !this->asMutable() && implicitDependency && this->dcFlushSupport;
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bool indirectMode = false;
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if (NEO::debugManager.flags.ResolveDependenciesViaPipeControls.get() != -1) {
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resolveDependenciesViaPipeControls = NEO::debugManager.flags.ResolveDependenciesViaPipeControls.get();
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}
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size_t inOrderPatchListIndex = std::numeric_limits<size_t>::max();
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if (isQwordInOrderCounter()) {
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indirectMode = true;
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if (resolveDependenciesViaPipeControls) {
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NEO::PipeControlArgs args;
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args.csStallOnly = true;
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NEO::MemorySynchronizationCommands<GfxFamily>::addSingleBarrier(*commandContainer.getCommandStream(), args);
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break;
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} else {
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using MI_SEMAPHORE_WAIT = typename GfxFamily::MI_SEMAPHORE_WAIT;
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using MI_LOAD_REGISTER_IMM = typename GfxFamily::MI_LOAD_REGISTER_IMM;
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constexpr uint32_t firstRegister = RegisterOffsets::csGprR0;
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constexpr uint32_t secondRegister = RegisterOffsets::csGprR0 + 4;
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bool indirectMode = false;
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auto lri1 = commandContainer.getCommandStream()->template getSpaceForCmd<MI_LOAD_REGISTER_IMM>();
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auto lri2 = commandContainer.getCommandStream()->template getSpaceForCmd<MI_LOAD_REGISTER_IMM>();
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size_t inOrderPatchListIndex = std::numeric_limits<size_t>::max();
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if (isQwordInOrderCounter()) {
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indirectMode = true;
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if (!noopDispatch) {
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NEO::LriHelper<GfxFamily>::program(lri1, firstRegister, getLowPart(waitValue), true, isCopyOnly(copyOffloadOperation));
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NEO::LriHelper<GfxFamily>::program(lri2, secondRegister, getHighPart(waitValue), true, isCopyOnly(copyOffloadOperation));
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} else {
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memset(lri1, 0, sizeof(MI_LOAD_REGISTER_IMM));
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memset(lri2, 0, sizeof(MI_LOAD_REGISTER_IMM));
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constexpr uint32_t firstRegister = RegisterOffsets::csGprR0;
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constexpr uint32_t secondRegister = RegisterOffsets::csGprR0 + 4;
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auto lri1 = commandContainer.getCommandStream()->template getSpaceForCmd<MI_LOAD_REGISTER_IMM>();
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auto lri2 = commandContainer.getCommandStream()->template getSpaceForCmd<MI_LOAD_REGISTER_IMM>();
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if (!noopDispatch) {
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NEO::LriHelper<GfxFamily>::program(lri1, firstRegister, getLowPart(waitValue), true, isCopyOnly(copyOffloadOperation));
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NEO::LriHelper<GfxFamily>::program(lri2, secondRegister, getHighPart(waitValue), true, isCopyOnly(copyOffloadOperation));
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} else {
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memset(lri1, 0, sizeof(MI_LOAD_REGISTER_IMM));
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memset(lri2, 0, sizeof(MI_LOAD_REGISTER_IMM));
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}
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if (inOrderExecInfo->isRegularCmdList()) {
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inOrderPatchListIndex = addCmdForPatching((implicitDependency ? nullptr : &inOrderExecInfo), lri1, lri2, waitValue, NEO::InOrderPatchCommandHelpers::PatchCmdType::lri64b);
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if (noopDispatch) {
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disablePatching(inOrderPatchListIndex);
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}
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}
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if (outListCommands != nullptr) {
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auto &lri1ToPatch = outListCommands->emplace_back();
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lri1ToPatch.type = CommandToPatch::CbWaitEventLoadRegisterImm;
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lri1ToPatch.pDestination = lri1;
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lri1ToPatch.inOrderPatchListIndex = inOrderPatchListIndex;
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lri1ToPatch.offset = firstRegister;
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auto &lri2ToPatch = outListCommands->emplace_back();
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lri2ToPatch.type = CommandToPatch::CbWaitEventLoadRegisterImm;
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lri2ToPatch.pDestination = lri2;
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lri2ToPatch.inOrderPatchListIndex = inOrderPatchListIndex;
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lri2ToPatch.offset = secondRegister;
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}
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}
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if (inOrderExecInfo->isRegularCmdList()) {
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inOrderPatchListIndex = addCmdForPatching((implicitDependency ? nullptr : &inOrderExecInfo), lri1, lri2, waitValue, NEO::InOrderPatchCommandHelpers::PatchCmdType::lri64b);
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auto semaphoreCommand = reinterpret_cast<MI_SEMAPHORE_WAIT *>(commandContainer.getCommandStream()->getSpace(sizeof(MI_SEMAPHORE_WAIT)));
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if (!noopDispatch) {
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NEO::EncodeSemaphore<GfxFamily>::programMiSemaphoreWait(semaphoreCommand, gpuAddress, waitValue, COMPARE_OPERATION::COMPARE_OPERATION_SAD_GREATER_THAN_OR_EQUAL_SDD,
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false, true, isQwordInOrderCounter(), indirectMode, false);
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} else {
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memset(semaphoreCommand, 0, sizeof(MI_SEMAPHORE_WAIT));
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}
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if (inOrderExecInfo->isRegularCmdList() && !isQwordInOrderCounter()) {
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inOrderPatchListIndex = addCmdForPatching((implicitDependency ? nullptr : &inOrderExecInfo), semaphoreCommand, nullptr, waitValue, NEO::InOrderPatchCommandHelpers::PatchCmdType::semaphore);
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if (noopDispatch) {
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disablePatching(inOrderPatchListIndex);
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}
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} else {
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inOrderPatchListIndex = std::numeric_limits<size_t>::max();
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}
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if (outListCommands != nullptr) {
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auto &lri1ToPatch = outListCommands->emplace_back();
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lri1ToPatch.type = CommandToPatch::CbWaitEventLoadRegisterImm;
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lri1ToPatch.pDestination = lri1;
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lri1ToPatch.inOrderPatchListIndex = inOrderPatchListIndex;
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lri1ToPatch.offset = firstRegister;
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auto &lri2ToPatch = outListCommands->emplace_back();
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lri2ToPatch.type = CommandToPatch::CbWaitEventLoadRegisterImm;
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lri2ToPatch.pDestination = lri2;
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lri2ToPatch.inOrderPatchListIndex = inOrderPatchListIndex;
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lri2ToPatch.offset = secondRegister;
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auto &semaphoreWaitPatch = outListCommands->emplace_back();
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semaphoreWaitPatch.type = CommandToPatch::CbWaitEventSemaphoreWait;
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semaphoreWaitPatch.pDestination = semaphoreCommand;
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semaphoreWaitPatch.offset = i * immWriteOffset;
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semaphoreWaitPatch.inOrderPatchListIndex = inOrderPatchListIndex;
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}
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}
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auto semaphoreCommand = reinterpret_cast<MI_SEMAPHORE_WAIT *>(commandContainer.getCommandStream()->getSpace(sizeof(MI_SEMAPHORE_WAIT)));
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if (!noopDispatch) {
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NEO::EncodeSemaphore<GfxFamily>::programMiSemaphoreWait(semaphoreCommand, gpuAddress, waitValue, COMPARE_OPERATION::COMPARE_OPERATION_SAD_GREATER_THAN_OR_EQUAL_SDD,
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false, true, isQwordInOrderCounter(), indirectMode, false);
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} else {
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memset(semaphoreCommand, 0, sizeof(MI_SEMAPHORE_WAIT));
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}
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if (inOrderExecInfo->isRegularCmdList() && !isQwordInOrderCounter()) {
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inOrderPatchListIndex = addCmdForPatching((implicitDependency ? nullptr : &inOrderExecInfo), semaphoreCommand, nullptr, waitValue, NEO::InOrderPatchCommandHelpers::PatchCmdType::semaphore);
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if (noopDispatch) {
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disablePatching(inOrderPatchListIndex);
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}
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} else {
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inOrderPatchListIndex = std::numeric_limits<size_t>::max();
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}
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if (outListCommands != nullptr) {
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auto &semaphoreWaitPatch = outListCommands->emplace_back();
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semaphoreWaitPatch.type = CommandToPatch::CbWaitEventSemaphoreWait;
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semaphoreWaitPatch.pDestination = semaphoreCommand;
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semaphoreWaitPatch.offset = i * immWriteOffset;
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semaphoreWaitPatch.inOrderPatchListIndex = inOrderPatchListIndex;
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}
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}
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gpuAddress += immWriteOffset;
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