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https://github.com/intel/compute-runtime.git
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Refactor preemption methods
- moving primary template definitions to preemption.inl Change-Id: Ia54c652503a6272c55800e5ba59b94ef21fa2a19
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sys_ocldev
parent
d563059c14
commit
85f890690d
@@ -66,4 +66,17 @@ class PreemptionHelper {
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static PreemptionMode getDefaultPreemptionMode(const HardwareInfo &hwInfo);
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};
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template <typename GfxFamily>
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struct PreemptionConfig {
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static const uint32_t mmioAddress;
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static const uint32_t maskVal;
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static const uint32_t maskShift;
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static const uint32_t mask;
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static const uint32_t threadGroupVal;
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static const uint32_t cmdLevelVal;
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static const uint32_t midThreadVal;
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};
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} // namespace OCLRT
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@@ -23,6 +23,7 @@
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#include "runtime/command_stream/preemption.h"
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#include "runtime/device/device.h"
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#include "runtime/command_queue/dispatch_walker_helper.h"
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#include "runtime/memory_manager/graphics_allocation.h"
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namespace OCLRT {
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@@ -70,4 +71,63 @@ void PreemptionHelper::applyPreemptionWaCmdsEnd(LinearStream *pCommandStream, co
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}
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}
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template <typename GfxFamily>
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void PreemptionHelper::programPreamble(LinearStream &preambleCmdStream, const Device &device,
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const GraphicsAllocation *preemptionCsr) {
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if (device.getPreemptionMode() != PreemptionMode::MidThread) {
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return;
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}
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UNRECOVERABLE_IF(nullptr == preemptionCsr);
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using GPGPU_CSR_BASE_ADDRESS = typename GfxFamily::GPGPU_CSR_BASE_ADDRESS;
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using STATE_SIP = typename GfxFamily::STATE_SIP;
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auto csr = reinterpret_cast<GPGPU_CSR_BASE_ADDRESS *>(preambleCmdStream.getSpace(sizeof(GPGPU_CSR_BASE_ADDRESS)));
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csr->init();
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csr->setGpgpuCsrBaseAddress(preemptionCsr->getGpuAddressToPatch());
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auto sip = reinterpret_cast<STATE_SIP *>(preambleCmdStream.getSpace(sizeof(STATE_SIP)));
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sip->init();
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sip->setSystemInstructionPointer(0);
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}
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template <typename GfxFamily>
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void PreemptionHelper::programCmdStream(LinearStream &cmdStream,
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PreemptionMode newPreemptionMode, PreemptionMode oldPreemptionMode,
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GraphicsAllocation *preemptionCsr,
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const LinearStream &ih, const Device &device) {
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if (oldPreemptionMode == newPreemptionMode) {
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DEBUG_BREAK_IF((newPreemptionMode == PreemptionMode::MidThread) && (false == isValidInstructionHeapForMidThreadPreemption(ih, device)));
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return;
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}
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uint32_t regVal = 0;
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if (newPreemptionMode == PreemptionMode::MidThread) {
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regVal = PreemptionConfig<GfxFamily>::midThreadVal | PreemptionConfig<GfxFamily>::mask;
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} else if (newPreemptionMode == PreemptionMode::ThreadGroup) {
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regVal = PreemptionConfig<GfxFamily>::threadGroupVal | PreemptionConfig<GfxFamily>::mask;
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} else {
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regVal = PreemptionConfig<GfxFamily>::cmdLevelVal | PreemptionConfig<GfxFamily>::mask;
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}
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LriHelper<GfxFamily>::program(&cmdStream, PreemptionConfig<GfxFamily>::mmioAddress, regVal);
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}
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template <typename GfxFamily>
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size_t PreemptionHelper::getRequiredCmdStreamSize(PreemptionMode newPreemptionMode, PreemptionMode oldPreemptionMode) {
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if (newPreemptionMode == oldPreemptionMode) {
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return 0;
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}
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return sizeof(typename GfxFamily::MI_LOAD_REGISTER_IMM);
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}
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template <typename GfxFamily>
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size_t PreemptionHelper::getRequiredPreambleSize(const Device &device) {
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if (device.getPreemptionMode() != PreemptionMode::MidThread) {
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return 0;
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}
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return sizeof(typename GfxFamily::GPGPU_CSR_BASE_ADDRESS) + sizeof(typename GfxFamily::STATE_SIP);
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}
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} // namespace OCLRT
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