Add new atomic operation

Related-To: NEO-5244

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
This commit is contained in:
Zbigniew Zdanowicz
2021-03-04 17:54:14 +00:00
committed by Compute-Runtime-Automation
parent 3a91bcfb9b
commit 8f91fcdd73
13 changed files with 249 additions and 15 deletions

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@@ -11,6 +11,7 @@ target_sources(igdrcl_aub_tests PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/aub_command_stream_tests.cpp
${CMAKE_CURRENT_SOURCE_DIR}/aub_mem_dump_tests.h
${CMAKE_CURRENT_SOURCE_DIR}/aub_mem_dump_tests.cpp
${CMAKE_CURRENT_SOURCE_DIR}/aub_mi_atomic_tests.cpp
)
add_subdirectories()

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@@ -0,0 +1,147 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/command_stream/command_stream_receiver_hw.h"
#include "shared/test/common/helpers/dispatch_flags_helper.h"
#include "opencl/source/command_stream/aub_command_stream_receiver_hw.h"
#include "opencl/test/unit_test/aub_tests/fixtures/aub_fixture.h"
#include "test.h"
#include <cstdint>
using namespace NEO;
struct MiAtomicAubFixture : public AUBFixture {
void SetUp() {
AUBFixture::SetUp(nullptr);
auto memoryManager = this->device->getMemoryManager();
AllocationProperties commandBufferProperties = {device->getRootDeviceIndex(),
true,
MemoryConstants::pageSize,
GraphicsAllocation::AllocationType::COMMAND_BUFFER,
false,
device->getDeviceBitfield()};
streamAllocation = memoryManager->allocateGraphicsMemoryWithProperties(commandBufferProperties);
ASSERT_NE(nullptr, streamAllocation);
AllocationProperties deviceBufferProperties = {device->getRootDeviceIndex(),
true,
MemoryConstants::pageSize,
GraphicsAllocation::AllocationType::BUFFER,
false,
device->getDeviceBitfield()};
deviceSurface = memoryManager->allocateGraphicsMemoryWithProperties(deviceBufferProperties);
ASSERT_NE(nullptr, deviceSurface);
AllocationProperties systemBufferProperties = {device->getRootDeviceIndex(),
true,
MemoryConstants::pageSize,
GraphicsAllocation::AllocationType::SVM_CPU,
false,
device->getDeviceBitfield()};
systemSurface = memoryManager->allocateGraphicsMemoryWithProperties(systemBufferProperties);
ASSERT_NE(nullptr, systemSurface);
taskStream.replaceGraphicsAllocation(streamAllocation);
taskStream.replaceBuffer(streamAllocation->getUnderlyingBuffer(),
streamAllocation->getUnderlyingBufferSize());
}
void TearDown() {
auto memoryManager = this->device->getMemoryManager();
memoryManager->freeGraphicsMemory(streamAllocation);
memoryManager->freeGraphicsMemory(deviceSurface);
memoryManager->freeGraphicsMemory(systemSurface);
AUBFixture::TearDown();
}
void flushStream() {
DispatchFlags dispatchFlags = DispatchFlagsHelper::createDefaultDispatchFlags();
dispatchFlags.guardCommandBufferWithPipeControl = true;
csr->makeResident(*deviceSurface);
csr->makeResident(*systemSurface);
csr->flushTask(taskStream, 0,
csr->getIndirectHeap(IndirectHeap::DYNAMIC_STATE, 0u),
csr->getIndirectHeap(IndirectHeap::INDIRECT_OBJECT, 0u),
csr->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0u),
0u, dispatchFlags, device->getDevice());
csr->flushBatchedSubmissions();
}
LinearStream taskStream;
GraphicsAllocation *streamAllocation = nullptr;
GraphicsAllocation *deviceSurface = nullptr;
GraphicsAllocation *systemSurface = nullptr;
};
using MiAtomicAubTest = Test<MiAtomicAubFixture>;
HWTEST_F(MiAtomicAubTest, WhenDispatchingAtomicMoveOperationThenExpectCorrectEndValues) {
using MI_ATOMIC = typename FamilyType::MI_ATOMIC;
auto atomicAddress = deviceSurface->getGpuAddress();
auto expectedGpuAddressDwordOp1 = atomicAddress;
auto expectedGpuAddressDwordOp2 = expectedGpuAddressDwordOp1 + sizeof(uint32_t);
auto expectedGpuAddressQwordOp3 = expectedGpuAddressDwordOp2 + sizeof(uint32_t);
uint32_t operation1dword0 = 0x10;
EncodeAtomic<FamilyType>::programMiAtomic(taskStream, expectedGpuAddressDwordOp1,
MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_4B_MOVE,
MI_ATOMIC::DATA_SIZE::DATA_SIZE_DWORD,
0, 0, operation1dword0, 0u);
uint32_t operation2dword0 = 0x22;
EncodeAtomic<FamilyType>::programMiAtomic(taskStream, expectedGpuAddressDwordOp2,
MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_4B_MOVE,
MI_ATOMIC::DATA_SIZE::DATA_SIZE_DWORD,
0, 0, operation2dword0, 0u);
uint32_t operation3dword0 = 0xF0;
uint32_t operation3dword1 = 0x1F;
EncodeAtomic<FamilyType>::programMiAtomic(taskStream, expectedGpuAddressQwordOp3,
MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_8B_MOVE,
MI_ATOMIC::DATA_SIZE::DATA_SIZE_QWORD,
0, 0, operation3dword0, operation3dword1);
uint64_t operation3qword = (static_cast<uint64_t>(operation3dword1) << 32) | operation3dword0;
flushStream();
expectMemory<FamilyType>(reinterpret_cast<void *>(expectedGpuAddressDwordOp1), &operation1dword0, sizeof(operation1dword0));
expectMemory<FamilyType>(reinterpret_cast<void *>(expectedGpuAddressDwordOp2), &operation2dword0, sizeof(operation2dword0));
expectMemory<FamilyType>(reinterpret_cast<void *>(expectedGpuAddressQwordOp3), &operation3qword, sizeof(operation3qword));
}
HWTEST_F(MiAtomicAubTest, GivenSystemMemoryWhenDispatchingAtomicMove4BytesOperationThenExpectCorrectEndValues) {
using MI_ATOMIC = typename FamilyType::MI_ATOMIC;
auto atomicAddress = systemSurface->getGpuAddress();
auto expectedGpuAddressDwordOp1 = atomicAddress;
auto expectedGpuAddressDwordOp2 = expectedGpuAddressDwordOp1 + sizeof(uint32_t);
uint32_t operation1dword0 = 0x15;
EncodeAtomic<FamilyType>::programMiAtomic(taskStream, expectedGpuAddressDwordOp1,
MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_4B_MOVE,
MI_ATOMIC::DATA_SIZE::DATA_SIZE_DWORD,
0, 0, operation1dword0, 0u);
uint32_t operation2dword0 = 0xFF;
EncodeAtomic<FamilyType>::programMiAtomic(taskStream, expectedGpuAddressDwordOp2,
MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_4B_MOVE,
MI_ATOMIC::DATA_SIZE::DATA_SIZE_DWORD,
0, 0, operation2dword0, 0u);
flushStream();
expectMemory<FamilyType>(reinterpret_cast<void *>(expectedGpuAddressDwordOp1), &operation1dword0, sizeof(operation1dword0));
expectMemory<FamilyType>(reinterpret_cast<void *>(expectedGpuAddressDwordOp2), &operation2dword0, sizeof(operation2dword0));
}

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@@ -115,7 +115,7 @@ class MockDeviceQueueHw : public DeviceQueueHw<GfxFamily> {
placeholder,
MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_8B_INCREMENT,
MI_ATOMIC::DATA_SIZE::DATA_SIZE_QWORD,
0x1u, 0x1u);
0x1u, 0x1u, 0x0u, 0x0u);
return miAtomic;
}