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https://github.com/intel/compute-runtime.git
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Add new atomic operation
Related-To: NEO-5244 Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
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Compute-Runtime-Automation
parent
3a91bcfb9b
commit
8f91fcdd73
@@ -11,6 +11,7 @@ target_sources(igdrcl_aub_tests PRIVATE
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${CMAKE_CURRENT_SOURCE_DIR}/aub_command_stream_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/aub_mem_dump_tests.h
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${CMAKE_CURRENT_SOURCE_DIR}/aub_mem_dump_tests.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/aub_mi_atomic_tests.cpp
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)
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add_subdirectories()
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@@ -0,0 +1,147 @@
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/*
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* Copyright (C) 2021 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "shared/source/command_stream/command_stream_receiver_hw.h"
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#include "shared/test/common/helpers/dispatch_flags_helper.h"
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#include "opencl/source/command_stream/aub_command_stream_receiver_hw.h"
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#include "opencl/test/unit_test/aub_tests/fixtures/aub_fixture.h"
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#include "test.h"
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#include <cstdint>
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using namespace NEO;
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struct MiAtomicAubFixture : public AUBFixture {
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void SetUp() {
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AUBFixture::SetUp(nullptr);
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auto memoryManager = this->device->getMemoryManager();
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AllocationProperties commandBufferProperties = {device->getRootDeviceIndex(),
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true,
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MemoryConstants::pageSize,
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GraphicsAllocation::AllocationType::COMMAND_BUFFER,
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false,
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device->getDeviceBitfield()};
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streamAllocation = memoryManager->allocateGraphicsMemoryWithProperties(commandBufferProperties);
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ASSERT_NE(nullptr, streamAllocation);
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AllocationProperties deviceBufferProperties = {device->getRootDeviceIndex(),
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true,
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MemoryConstants::pageSize,
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GraphicsAllocation::AllocationType::BUFFER,
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false,
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device->getDeviceBitfield()};
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deviceSurface = memoryManager->allocateGraphicsMemoryWithProperties(deviceBufferProperties);
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ASSERT_NE(nullptr, deviceSurface);
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AllocationProperties systemBufferProperties = {device->getRootDeviceIndex(),
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true,
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MemoryConstants::pageSize,
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GraphicsAllocation::AllocationType::SVM_CPU,
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false,
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device->getDeviceBitfield()};
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systemSurface = memoryManager->allocateGraphicsMemoryWithProperties(systemBufferProperties);
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ASSERT_NE(nullptr, systemSurface);
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taskStream.replaceGraphicsAllocation(streamAllocation);
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taskStream.replaceBuffer(streamAllocation->getUnderlyingBuffer(),
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streamAllocation->getUnderlyingBufferSize());
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}
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void TearDown() {
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auto memoryManager = this->device->getMemoryManager();
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memoryManager->freeGraphicsMemory(streamAllocation);
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memoryManager->freeGraphicsMemory(deviceSurface);
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memoryManager->freeGraphicsMemory(systemSurface);
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AUBFixture::TearDown();
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}
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void flushStream() {
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DispatchFlags dispatchFlags = DispatchFlagsHelper::createDefaultDispatchFlags();
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dispatchFlags.guardCommandBufferWithPipeControl = true;
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csr->makeResident(*deviceSurface);
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csr->makeResident(*systemSurface);
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csr->flushTask(taskStream, 0,
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csr->getIndirectHeap(IndirectHeap::DYNAMIC_STATE, 0u),
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csr->getIndirectHeap(IndirectHeap::INDIRECT_OBJECT, 0u),
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csr->getIndirectHeap(IndirectHeap::SURFACE_STATE, 0u),
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0u, dispatchFlags, device->getDevice());
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csr->flushBatchedSubmissions();
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}
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LinearStream taskStream;
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GraphicsAllocation *streamAllocation = nullptr;
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GraphicsAllocation *deviceSurface = nullptr;
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GraphicsAllocation *systemSurface = nullptr;
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};
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using MiAtomicAubTest = Test<MiAtomicAubFixture>;
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HWTEST_F(MiAtomicAubTest, WhenDispatchingAtomicMoveOperationThenExpectCorrectEndValues) {
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using MI_ATOMIC = typename FamilyType::MI_ATOMIC;
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auto atomicAddress = deviceSurface->getGpuAddress();
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auto expectedGpuAddressDwordOp1 = atomicAddress;
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auto expectedGpuAddressDwordOp2 = expectedGpuAddressDwordOp1 + sizeof(uint32_t);
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auto expectedGpuAddressQwordOp3 = expectedGpuAddressDwordOp2 + sizeof(uint32_t);
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uint32_t operation1dword0 = 0x10;
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EncodeAtomic<FamilyType>::programMiAtomic(taskStream, expectedGpuAddressDwordOp1,
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MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_4B_MOVE,
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MI_ATOMIC::DATA_SIZE::DATA_SIZE_DWORD,
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0, 0, operation1dword0, 0u);
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uint32_t operation2dword0 = 0x22;
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EncodeAtomic<FamilyType>::programMiAtomic(taskStream, expectedGpuAddressDwordOp2,
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MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_4B_MOVE,
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MI_ATOMIC::DATA_SIZE::DATA_SIZE_DWORD,
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0, 0, operation2dword0, 0u);
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uint32_t operation3dword0 = 0xF0;
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uint32_t operation3dword1 = 0x1F;
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EncodeAtomic<FamilyType>::programMiAtomic(taskStream, expectedGpuAddressQwordOp3,
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MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_8B_MOVE,
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MI_ATOMIC::DATA_SIZE::DATA_SIZE_QWORD,
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0, 0, operation3dword0, operation3dword1);
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uint64_t operation3qword = (static_cast<uint64_t>(operation3dword1) << 32) | operation3dword0;
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flushStream();
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expectMemory<FamilyType>(reinterpret_cast<void *>(expectedGpuAddressDwordOp1), &operation1dword0, sizeof(operation1dword0));
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expectMemory<FamilyType>(reinterpret_cast<void *>(expectedGpuAddressDwordOp2), &operation2dword0, sizeof(operation2dword0));
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expectMemory<FamilyType>(reinterpret_cast<void *>(expectedGpuAddressQwordOp3), &operation3qword, sizeof(operation3qword));
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}
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HWTEST_F(MiAtomicAubTest, GivenSystemMemoryWhenDispatchingAtomicMove4BytesOperationThenExpectCorrectEndValues) {
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using MI_ATOMIC = typename FamilyType::MI_ATOMIC;
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auto atomicAddress = systemSurface->getGpuAddress();
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auto expectedGpuAddressDwordOp1 = atomicAddress;
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auto expectedGpuAddressDwordOp2 = expectedGpuAddressDwordOp1 + sizeof(uint32_t);
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uint32_t operation1dword0 = 0x15;
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EncodeAtomic<FamilyType>::programMiAtomic(taskStream, expectedGpuAddressDwordOp1,
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MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_4B_MOVE,
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MI_ATOMIC::DATA_SIZE::DATA_SIZE_DWORD,
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0, 0, operation1dword0, 0u);
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uint32_t operation2dword0 = 0xFF;
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EncodeAtomic<FamilyType>::programMiAtomic(taskStream, expectedGpuAddressDwordOp2,
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MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_4B_MOVE,
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MI_ATOMIC::DATA_SIZE::DATA_SIZE_DWORD,
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0, 0, operation2dword0, 0u);
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flushStream();
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expectMemory<FamilyType>(reinterpret_cast<void *>(expectedGpuAddressDwordOp1), &operation1dword0, sizeof(operation1dword0));
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expectMemory<FamilyType>(reinterpret_cast<void *>(expectedGpuAddressDwordOp2), &operation2dword0, sizeof(operation2dword0));
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}
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@@ -115,7 +115,7 @@ class MockDeviceQueueHw : public DeviceQueueHw<GfxFamily> {
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placeholder,
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MI_ATOMIC::ATOMIC_OPCODES::ATOMIC_8B_INCREMENT,
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MI_ATOMIC::DATA_SIZE::DATA_SIZE_QWORD,
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0x1u, 0x1u);
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0x1u, 0x1u, 0x0u, 0x0u);
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return miAtomic;
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}
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