performance: align structures for 64-bit platforms

Signed-off-by: Semenov Herman (Семенов Герман) <GermanAizek@yandex.ru>

shared/source/command_stream/command_stream_receiver_hw.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2024 Intel Corporation
+ * Copyright (C) 2018-2025 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -25,10 +25,10 @@ class CommandStreamReceiverHw : public CommandStreamReceiver {
     using STATE_BASE_ADDRESS = typename GfxFamily::STATE_BASE_ADDRESS;
 
     struct ImmediateFlushData {
-        PipelineSelectArgs pipelineSelectArgs{};
-        size_t estimatedSize = 0;
         void *endPtr = nullptr;
+        size_t estimatedSize = 0;
         size_t csrStartOffset = 0;
+        PipelineSelectArgs pipelineSelectArgs{};
 
         bool pipelineSelectFullConfigurationNeeded = false;
         bool pipelineSelectDirty = false;

shared/source/command_stream/command_stream_receiver_simulated_common_hw.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2024 Intel Corporation
+ * Copyright (C) 2018-2025 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -81,12 +81,12 @@ class CommandStreamReceiverSimulatedCommonHw : public CommandStreamReceiverHw<Gf
 
     struct EngineInfo {
         void *pLRCA;
-        uint32_t ggttLRCA;
         void *pGlobalHWStatusPage;
-        uint32_t ggttHWSP;
         void *pRingBuffer;
-        uint32_t ggttRingBuffer;
         size_t sizeRingBuffer;
+        uint32_t ggttLRCA;
+        uint32_t ggttHWSP;
+        uint32_t ggttRingBuffer;
         uint32_t tailRingBuffer;
     } engineInfo = {};
 

shared/source/command_stream/submissions_aggregator.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2024 Intel Corporation
+ * Copyright (C) 2018-2025 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -99,11 +99,11 @@ NEO::BatchBuffer::BatchBuffer(GraphicsAllocation *commandBufferAllocation, size_
                               size_t usedSize, LinearStream *stream, void *endCmdPtr, uint32_t numCsrClients, bool hasStallingCmds,
                               bool hasRelaxedOrderingDependencies, bool dispatchMonitorFence, bool taskCountUpdateOnly)
     : commandBufferAllocation(commandBufferAllocation), startOffset(startOffset),
-      chainedBatchBufferStartOffset(chainedBatchBufferStartOffset), taskStartAddress(taskStartAddress), chainedBatchBuffer(chainedBatchBuffer),
-      lowPriority(lowPriority),
-      throttle(throttle), sliceCount(sliceCount),
-      usedSize(usedSize), stream(stream), endCmdPtr(endCmdPtr), numCsrClients(numCsrClients), hasStallingCmds(hasStallingCmds),
-      hasRelaxedOrderingDependencies(hasRelaxedOrderingDependencies), dispatchMonitorFence(dispatchMonitorFence), taskCountUpdateOnly(taskCountUpdateOnly) {}
+      chainedBatchBufferStartOffset(chainedBatchBufferStartOffset), taskStartAddress(taskStartAddress), stream(stream), endCmdPtr(endCmdPtr),
+      numCsrClients(numCsrClients), hasStallingCmds(hasStallingCmds), hasRelaxedOrderingDependencies(hasRelaxedOrderingDependencies),
+      dispatchMonitorFence(dispatchMonitorFence), taskCountUpdateOnly(taskCountUpdateOnly), lowPriority(lowPriority), throttle(throttle),
+      chainedBatchBuffer(chainedBatchBuffer), sliceCount(sliceCount),
+      usedSize(usedSize) {}
 
 NEO::CommandBuffer::CommandBuffer(Device &device) : device(device) {
     flushStamp.reset(new FlushStampTracker(false));

shared/source/command_stream/submissions_aggregator.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2024 Intel Corporation
+ * Copyright (C) 2018-2025 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -46,30 +46,31 @@ struct BatchBuffer {
                 bool dispatchMonitorFence,
                 bool taskCountUpdateOnly);
     BatchBuffer() {}
+
+    PagingFenceSemaphoreInfo pagingFenceSemInfo{};
+
     GraphicsAllocation *commandBufferAllocation = nullptr;
     ResidencyContainer *allocationsForResidency = nullptr;
     size_t startOffset = 0u;
     size_t chainedBatchBufferStartOffset = 0u;
     uint64_t taskStartAddress = 0; // if task not available, use CSR stream
 
-    GraphicsAllocation *chainedBatchBuffer = nullptr;
-    bool lowPriority = false;
-    QueueThrottle throttle = QueueThrottle::MEDIUM;
-    uint64_t sliceCount = QueueSliceCount::defaultSliceCount;
-    size_t usedSize = 0u;
-
     // only used in drm csr in gem close worker active mode
     LinearStream *stream = nullptr;
     void *endCmdPtr = nullptr;
     uint32_t numCsrClients = 0;
 
-    PagingFenceSemaphoreInfo pagingFenceSemInfo{};
-
     bool hasStallingCmds = false;
     bool hasRelaxedOrderingDependencies = false;
     bool disableFlatRingBuffer = false;
     bool dispatchMonitorFence = false;
     bool taskCountUpdateOnly = false;
+
+    bool lowPriority = false;
+    QueueThrottle throttle = QueueThrottle::MEDIUM;
+    GraphicsAllocation *chainedBatchBuffer = nullptr;
+    uint64_t sliceCount = QueueSliceCount::defaultSliceCount;
+    size_t usedSize = 0u;
 };
 
 struct CommandBuffer : public IDNode<CommandBuffer> {

shared/source/device_binary_format/zebin/zeinfo.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2023-2024 Intel Corporation
+ * Copyright (C) 2023-2025 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -634,12 +634,12 @@ inline constexpr BtiValueT btiValue = -1;
 } // namespace Defaults
 
 struct PayloadArgumentBaseT {
-    ArgTypeT argType = argTypeUnknown;
     OffsetT offset = Defaults::offset;
     SourceOffseT sourceOffset = Defaults::sourceOffset;
     SizeT size = 0;
     ArgIndexT argIndex = Defaults::argIndex;
     BtiValueT btiValue = Defaults::btiValue;
+    ArgTypeT argType = argTypeUnknown;
     AddrmodeT addrmode = memoryAddressingModeUnknown;
     AddrspaceT addrspace = addressSpaceUnknown;
     AccessTypeT accessType = accessTypeUnknown;
@@ -692,9 +692,9 @@ inline constexpr Slot slot = 0U;
 } // namespace Defaults
 
 struct PerThreadMemoryBufferBaseT {
+    SizeT size = 0U;
     AllocationType allocationType = AllocationTypeUnknown;
     MemoryUsageT memoryUsage = MemoryUsageUnknown;
-    SizeT size = 0U;
     IsSimtThreadT isSimtThread = Defaults::isSimtThread;
     Slot slot = Defaults::slot;
 };
@@ -732,8 +732,8 @@ inline constexpr NormalizedT normalized = false;
 
 struct InlineSamplerBaseT {
     SamplerIndexT samplerIndex = Defaults::samplerIndex;
-    AddrModeT addrMode = Defaults::addrMode;
     FilterModeT filterMode = Defaults::filterMode;
+    AddrModeT addrMode = Defaults::addrMode;
     NormalizedT normalized = Defaults::normalized;
 };
 } // namespace InlineSamplers

shared/source/helpers/surface_format_info.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2020-2024 Intel Corporation
+ * Copyright (C) 2020-2025 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -218,13 +218,13 @@ enum class ImageType {
 };
 
 struct ImageDescriptor {
-    ImageType imageType;
     size_t imageWidth;
     size_t imageHeight;
     size_t imageDepth;
     size_t imageArraySize;
     size_t imageRowPitch;
     size_t imageSlicePitch;
+    ImageType imageType;
     uint32_t numMipLevels;
     uint32_t numSamples;
     bool fromParent;

shared/source/memory_manager/host_ptr_defines.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2023 Intel Corporation
+ * Copyright (C) 2018-2025 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,9 +51,9 @@ struct AllocationRequirements {
 struct FragmentStorage {
     const void *fragmentCpuPointer = nullptr;
     size_t fragmentSize = 0;
-    int refCount = 0;
     OsHandle *osInternalStorage = nullptr;
     ResidencyData *residency = nullptr;
+    int refCount = 0;
     bool driverAllocation = false;
 };
 

shared/source/os_interface/linux/xe/ioctl_helper_xe.h

@@ -190,9 +190,9 @@ class IoctlHelperXe : public IoctlHelper {
 
     std::unique_ptr<XeDrm::drm_xe_engine_class_instance> defaultEngine;
     struct DebugMetadata {
-        DrmResourceClass type;
         uint64_t offset;
         uint64_t size;
+        DrmResourceClass type;
         bool isCookie;
     };