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performance: align structures for 64-bit platforms

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Signed-off-by: Semenov Herman (Семенов Герман) <GermanAizek@yandex.ru>
This commit is contained in:
Semenov Herman (Семенов Герман)
2025-01-04 22:26:02 +03:00
committed by Compute-Runtime-Automation
parent 22cebedcd1
commit 9f07f56f7f
16 changed files with 55 additions and 54 deletions
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4
opencl/source/command_queue/copy_engine_state.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2021-2023 Intel Corporation * Copyright (C) 2021-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -13,8 +13,8 @@
namespace NEO { namespace NEO {
struct CopyEngineState { struct CopyEngineState {
aub_stream::EngineType engineType = aub_stream::EngineType::NUM_ENGINES;
TaskCountType taskCount = 0; TaskCountType taskCount = 0;
aub_stream::EngineType engineType = aub_stream::EngineType::NUM_ENGINES;
bool csrClientRegistered = false; bool csrClientRegistered = false;
bool isValid() const { bool isValid() const {

14
opencl/source/command_queue/csr_selection_args.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2021-2023 Intel Corporation * Copyright (C) 2021-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -24,21 +24,21 @@ struct CsrSelectionArgs {
const size_t *imageOrigin = nullptr; const size_t *imageOrigin = nullptr;
}; };
cl_command_type cmdType;
const size_t *size = nullptr;
Resource srcResource; Resource srcResource;
Resource dstResource; Resource dstResource;
const size_t *size = nullptr;
cl_command_type cmdType;
TransferDirection direction; TransferDirection direction;
CsrSelectionArgs(cl_command_type cmdType, const size_t *size) CsrSelectionArgs(cl_command_type cmdType, const size_t *size)
: cmdType(cmdType), : size(size),
size(size), cmdType(cmdType),
direction(TransferDirection::hostToHost) {} direction(TransferDirection::hostToHost) {}
template <typename ResourceType> template <typename ResourceType>
CsrSelectionArgs(cl_command_type cmdType, ResourceType *src, ResourceType *dst, uint32_t rootDeviceIndex, const size_t *size) CsrSelectionArgs(cl_command_type cmdType, ResourceType *src, ResourceType *dst, uint32_t rootDeviceIndex, const size_t *size)
: cmdType(cmdType), : size(size),
size(size) { cmdType(cmdType) {
if (src) { if (src) {
processResource(*src, rootDeviceIndex, this->srcResource); processResource(*src, rootDeviceIndex, this->srcResource);
} }

8
opencl/source/command_queue/enqueue_svm.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2018-2024 Intel Corporation * Copyright (C) 2018-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -25,20 +25,20 @@ using SvmFreeClbT = void(CL_CALLBACK *)(cl_command_queue queue,
void *userData); void *userData);
struct SvmFreeUserData { struct SvmFreeUserData {
cl_uint numSvmPointers;
void **svmPointers; void **svmPointers;
SvmFreeClbT clb; SvmFreeClbT clb;
void *userData; void *userData;
cl_uint numSvmPointers;
bool ownsEventDeletion; bool ownsEventDeletion;
SvmFreeUserData(cl_uint numSvmPointers, SvmFreeUserData(cl_uint numSvmPointers,
void **svmPointers, SvmFreeClbT clb, void **svmPointers, SvmFreeClbT clb,
void *userData, void *userData,
bool ownsEventDeletion) bool ownsEventDeletion)
: numSvmPointers(numSvmPointers), : svmPointers(svmPointers),
svmPointers(svmPointers),
clb(clb), clb(clb),
userData(userData), userData(userData),
numSvmPointers(numSvmPointers),
ownsEventDeletion(ownsEventDeletion){}; ownsEventDeletion(ownsEventDeletion){};
}; };

4
opencl/test/unit_test/command_queue/blit_enqueue_1_tests.cpp
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2019-2024 Intel Corporation * Copyright (C) 2019-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -1251,7 +1251,7 @@ HWTEST_TEMPLATED_F(BlitEnqueueTaskCountTests, whenWaitUntilCompletionCalledThenW
uint32_t gpgpuTaskCount = 123; uint32_t gpgpuTaskCount = 123;
uint32_t bcsTaskCount = 123; uint32_t bcsTaskCount = 123;
CopyEngineState bcsState{bcsCsr->getOsContext().getEngineType(), bcsTaskCount}; CopyEngineState bcsState{bcsTaskCount, bcsCsr->getOsContext().getEngineType()};
commandQueue->waitUntilComplete(gpgpuTaskCount, Range{&bcsState}, 0, false); commandQueue->waitUntilComplete(gpgpuTaskCount, Range{&bcsState}, 0, false);
EXPECT_EQ(gpgpuTaskCount, static_cast<UltCommandStreamReceiver<FamilyType> *>(gpgpuCsr)->latestWaitForCompletionWithTimeoutTaskCount.load()); EXPECT_EQ(gpgpuTaskCount, static_cast<UltCommandStreamReceiver<FamilyType> *>(gpgpuCsr)->latestWaitForCompletionWithTimeoutTaskCount.load());

4
opencl/test/unit_test/command_queue/command_queue_hw_1_tests.cpp
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2018-2024 Intel Corporation * Copyright (C) 2018-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -55,7 +55,7 @@ HWTEST_F(CommandQueueHwTest, whenCallingIsCompletedThenTestTaskCountValue) {
bcsCsr->setupContext(*osContext); bcsCsr->setupContext(*osContext);
bcsCsr->initializeTagAllocation(); bcsCsr->initializeTagAllocation();
EngineControl control(bcsCsr.get(), osContext.get()); EngineControl control(bcsCsr.get(), osContext.get());
CopyEngineState state{aub_stream::EngineType::ENGINE_BCS, 1, false}; CopyEngineState state{1, aub_stream::EngineType::ENGINE_BCS, false};
MockCommandQueueHw<FamilyType> cmdQ(context, pClDevice, nullptr); MockCommandQueueHw<FamilyType> cmdQ(context, pClDevice, nullptr);

4
opencl/test/unit_test/command_stream/cl_tbx_command_stream_tests.cpp
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2021-2023 Intel Corporation * Copyright (C) 2021-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -47,7 +47,7 @@ HWTEST_F(ClTbxCommandStreamTests, givenTbxCsrWhenDispatchBlitEnqueueThenProcessC
cmdQ.clearBcsEngines(); cmdQ.clearBcsEngines();
cmdQ.bcsEngines[0] = &engineControl1; cmdQ.bcsEngines[0] = &engineControl1;
cmdQ.bcsStates[0] = {aub_stream::ENGINE_BCS, 0, false}; cmdQ.bcsStates[0] = {0, aub_stream::ENGINE_BCS, false};
cl_int error = CL_SUCCESS; cl_int error = CL_SUCCESS;
std::unique_ptr<Buffer> buffer(Buffer::create(&context, 0, 1, nullptr, error)); std::unique_ptr<Buffer> buffer(Buffer::create(&context, 0, 1, nullptr, error));

4
opencl/test/unit_test/mem_obj/buffer_bcs_tests.cpp
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2020-2024 Intel Corporation * Copyright (C) 2020-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -619,7 +619,7 @@ HWTEST_TEMPLATED_F(BcsBufferTests, givenAllBcsEnginesReadyWhenWaitingForEventThe
ultCsr2.initializeTagAllocation(); ultCsr2.initializeTagAllocation();
ultCsr2.setupContext(osContext); ultCsr2.setupContext(osContext);
CopyEngineState copyEngineState = {aub_stream::EngineType::ENGINE_BCS2, 2, false}; CopyEngineState copyEngineState = {2, aub_stream::EngineType::ENGINE_BCS2, false};
EngineControl engineControl = {&ultCsr2, &osContext}; EngineControl engineControl = {&ultCsr2, &osContext};
auto bcs2Index = EngineHelpers::getBcsIndex(aub_stream::EngineType::ENGINE_BCS2); auto bcs2Index = EngineHelpers::getBcsIndex(aub_stream::EngineType::ENGINE_BCS2);
mockCmdQ->bcsStates[bcs2Index] = copyEngineState; mockCmdQ->bcsStates[bcs2Index] = copyEngineState;

4
opencl/test/unit_test/mem_obj/image_tests.cpp
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2018-2024 Intel Corporation * Copyright (C) 2018-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -1559,7 +1559,7 @@ TEST(ImageConvertDescriptorTest, givenClImageDescWhenConvertedThenCorrectImageDe
} }
TEST(ImageConvertDescriptorTest, givenImageDescriptorWhenConvertedThenCorrectClImageDescIsReturned) { TEST(ImageConvertDescriptorTest, givenImageDescriptorWhenConvertedThenCorrectClImageDescIsReturned) {
ImageDescriptor desc = {ImageType::image2D, 16, 24, 1, 1, 1024, 2048, 1, 3, false}; ImageDescriptor desc = {16, 24, 1, 1, 1024, 2048, ImageType::image2D, 1, 3, false};
auto clDesc = Image::convertDescriptor(desc); auto clDesc = Image::convertDescriptor(desc);
EXPECT_EQ(clDesc.image_type, static_cast<cl_mem_object_type>(CL_MEM_OBJECT_IMAGE2D)); EXPECT_EQ(clDesc.image_type, static_cast<cl_mem_object_type>(CL_MEM_OBJECT_IMAGE2D));

6
shared/source/command_stream/command_stream_receiver_hw.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2018-2024 Intel Corporation * Copyright (C) 2018-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -25,10 +25,10 @@ class CommandStreamReceiverHw : public CommandStreamReceiver {
using STATE_BASE_ADDRESS = typename GfxFamily::STATE_BASE_ADDRESS; using STATE_BASE_ADDRESS = typename GfxFamily::STATE_BASE_ADDRESS;
struct ImmediateFlushData { struct ImmediateFlushData {
PipelineSelectArgs pipelineSelectArgs{};
size_t estimatedSize = 0;
void *endPtr = nullptr; void *endPtr = nullptr;
size_t estimatedSize = 0;
size_t csrStartOffset = 0; size_t csrStartOffset = 0;
PipelineSelectArgs pipelineSelectArgs{};
bool pipelineSelectFullConfigurationNeeded = false; bool pipelineSelectFullConfigurationNeeded = false;
bool pipelineSelectDirty = false; bool pipelineSelectDirty = false;

8
shared/source/command_stream/command_stream_receiver_simulated_common_hw.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2018-2024 Intel Corporation * Copyright (C) 2018-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -81,12 +81,12 @@ class CommandStreamReceiverSimulatedCommonHw : public CommandStreamReceiverHw<Gf
struct EngineInfo { struct EngineInfo {
void *pLRCA; void *pLRCA;
uint32_t ggttLRCA;
void *pGlobalHWStatusPage; void *pGlobalHWStatusPage;
uint32_t ggttHWSP;
void *pRingBuffer; void *pRingBuffer;
uint32_t ggttRingBuffer;
size_t sizeRingBuffer; size_t sizeRingBuffer;
uint32_t ggttLRCA;
uint32_t ggttHWSP;
uint32_t ggttRingBuffer;
uint32_t tailRingBuffer; uint32_t tailRingBuffer;
} engineInfo = {}; } engineInfo = {};

12
shared/source/command_stream/submissions_aggregator.cpp
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2018-2024 Intel Corporation * Copyright (C) 2018-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -99,11 +99,11 @@ NEO::BatchBuffer::BatchBuffer(GraphicsAllocation *commandBufferAllocation, size_
size_t usedSize, LinearStream *stream, void *endCmdPtr, uint32_t numCsrClients, bool hasStallingCmds, size_t usedSize, LinearStream *stream, void *endCmdPtr, uint32_t numCsrClients, bool hasStallingCmds,
bool hasRelaxedOrderingDependencies, bool dispatchMonitorFence, bool taskCountUpdateOnly) bool hasRelaxedOrderingDependencies, bool dispatchMonitorFence, bool taskCountUpdateOnly)
: commandBufferAllocation(commandBufferAllocation), startOffset(startOffset), : commandBufferAllocation(commandBufferAllocation), startOffset(startOffset),
chainedBatchBufferStartOffset(chainedBatchBufferStartOffset), taskStartAddress(taskStartAddress), chainedBatchBuffer(chainedBatchBuffer), chainedBatchBufferStartOffset(chainedBatchBufferStartOffset), taskStartAddress(taskStartAddress), stream(stream), endCmdPtr(endCmdPtr),
lowPriority(lowPriority), numCsrClients(numCsrClients), hasStallingCmds(hasStallingCmds), hasRelaxedOrderingDependencies(hasRelaxedOrderingDependencies),
throttle(throttle), sliceCount(sliceCount), dispatchMonitorFence(dispatchMonitorFence), taskCountUpdateOnly(taskCountUpdateOnly), lowPriority(lowPriority), throttle(throttle),
usedSize(usedSize), stream(stream), endCmdPtr(endCmdPtr), numCsrClients(numCsrClients), hasStallingCmds(hasStallingCmds), chainedBatchBuffer(chainedBatchBuffer), sliceCount(sliceCount),
hasRelaxedOrderingDependencies(hasRelaxedOrderingDependencies), dispatchMonitorFence(dispatchMonitorFence), taskCountUpdateOnly(taskCountUpdateOnly) {} usedSize(usedSize) {}
NEO::CommandBuffer::CommandBuffer(Device &device) : device(device) { NEO::CommandBuffer::CommandBuffer(Device &device) : device(device) {
flushStamp.reset(new FlushStampTracker(false)); flushStamp.reset(new FlushStampTracker(false));

19
shared/source/command_stream/submissions_aggregator.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2018-2024 Intel Corporation * Copyright (C) 2018-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -46,30 +46,31 @@ struct BatchBuffer {
bool dispatchMonitorFence, bool dispatchMonitorFence,
bool taskCountUpdateOnly); bool taskCountUpdateOnly);
BatchBuffer() {} BatchBuffer() {}
PagingFenceSemaphoreInfo pagingFenceSemInfo{};
GraphicsAllocation *commandBufferAllocation = nullptr; GraphicsAllocation *commandBufferAllocation = nullptr;
ResidencyContainer *allocationsForResidency = nullptr; ResidencyContainer *allocationsForResidency = nullptr;
size_t startOffset = 0u; size_t startOffset = 0u;
size_t chainedBatchBufferStartOffset = 0u; size_t chainedBatchBufferStartOffset = 0u;
uint64_t taskStartAddress = 0; // if task not available, use CSR stream uint64_t taskStartAddress = 0; // if task not available, use CSR stream
GraphicsAllocation *chainedBatchBuffer = nullptr;
bool lowPriority = false;
QueueThrottle throttle = QueueThrottle::MEDIUM;
uint64_t sliceCount = QueueSliceCount::defaultSliceCount;
size_t usedSize = 0u;
// only used in drm csr in gem close worker active mode // only used in drm csr in gem close worker active mode
LinearStream *stream = nullptr; LinearStream *stream = nullptr;
void *endCmdPtr = nullptr; void *endCmdPtr = nullptr;
uint32_t numCsrClients = 0; uint32_t numCsrClients = 0;
PagingFenceSemaphoreInfo pagingFenceSemInfo{};
bool hasStallingCmds = false; bool hasStallingCmds = false;
bool hasRelaxedOrderingDependencies = false; bool hasRelaxedOrderingDependencies = false;
bool disableFlatRingBuffer = false; bool disableFlatRingBuffer = false;
bool dispatchMonitorFence = false; bool dispatchMonitorFence = false;
bool taskCountUpdateOnly = false; bool taskCountUpdateOnly = false;
bool lowPriority = false;
QueueThrottle throttle = QueueThrottle::MEDIUM;
GraphicsAllocation *chainedBatchBuffer = nullptr;
uint64_t sliceCount = QueueSliceCount::defaultSliceCount;
size_t usedSize = 0u;
}; };
struct CommandBuffer : public IDNode<CommandBuffer> { struct CommandBuffer : public IDNode<CommandBuffer> {

8
shared/source/device_binary_format/zebin/zeinfo.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2023-2024 Intel Corporation * Copyright (C) 2023-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -634,12 +634,12 @@ inline constexpr BtiValueT btiValue = -1;
} // namespace Defaults } // namespace Defaults
struct PayloadArgumentBaseT { struct PayloadArgumentBaseT {
ArgTypeT argType = argTypeUnknown;
OffsetT offset = Defaults::offset; OffsetT offset = Defaults::offset;
SourceOffseT sourceOffset = Defaults::sourceOffset; SourceOffseT sourceOffset = Defaults::sourceOffset;
SizeT size = 0; SizeT size = 0;
ArgIndexT argIndex = Defaults::argIndex; ArgIndexT argIndex = Defaults::argIndex;
BtiValueT btiValue = Defaults::btiValue; BtiValueT btiValue = Defaults::btiValue;
ArgTypeT argType = argTypeUnknown;
AddrmodeT addrmode = memoryAddressingModeUnknown; AddrmodeT addrmode = memoryAddressingModeUnknown;
AddrspaceT addrspace = addressSpaceUnknown; AddrspaceT addrspace = addressSpaceUnknown;
AccessTypeT accessType = accessTypeUnknown; AccessTypeT accessType = accessTypeUnknown;
@@ -692,9 +692,9 @@ inline constexpr Slot slot = 0U;
} // namespace Defaults } // namespace Defaults
struct PerThreadMemoryBufferBaseT { struct PerThreadMemoryBufferBaseT {
SizeT size = 0U;
AllocationType allocationType = AllocationTypeUnknown; AllocationType allocationType = AllocationTypeUnknown;
MemoryUsageT memoryUsage = MemoryUsageUnknown; MemoryUsageT memoryUsage = MemoryUsageUnknown;
SizeT size = 0U;
IsSimtThreadT isSimtThread = Defaults::isSimtThread; IsSimtThreadT isSimtThread = Defaults::isSimtThread;
Slot slot = Defaults::slot; Slot slot = Defaults::slot;
}; };
@@ -732,8 +732,8 @@ inline constexpr NormalizedT normalized = false;
struct InlineSamplerBaseT { struct InlineSamplerBaseT {
SamplerIndexT samplerIndex = Defaults::samplerIndex; SamplerIndexT samplerIndex = Defaults::samplerIndex;
AddrModeT addrMode = Defaults::addrMode;
FilterModeT filterMode = Defaults::filterMode; FilterModeT filterMode = Defaults::filterMode;
AddrModeT addrMode = Defaults::addrMode;
NormalizedT normalized = Defaults::normalized; NormalizedT normalized = Defaults::normalized;
}; };
} // namespace InlineSamplers } // namespace InlineSamplers

4
shared/source/helpers/surface_format_info.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2020-2024 Intel Corporation * Copyright (C) 2020-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -218,13 +218,13 @@ enum class ImageType {
}; };
struct ImageDescriptor { struct ImageDescriptor {
ImageType imageType;
size_t imageWidth; size_t imageWidth;
size_t imageHeight; size_t imageHeight;
size_t imageDepth; size_t imageDepth;
size_t imageArraySize; size_t imageArraySize;
size_t imageRowPitch; size_t imageRowPitch;
size_t imageSlicePitch; size_t imageSlicePitch;
ImageType imageType;
uint32_t numMipLevels; uint32_t numMipLevels;
uint32_t numSamples; uint32_t numSamples;
bool fromParent; bool fromParent;

4
shared/source/memory_manager/host_ptr_defines.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2018-2023 Intel Corporation * Copyright (C) 2018-2025 Intel Corporation
* *
* SPDX-License-Identifier: MIT * SPDX-License-Identifier: MIT
* *
@@ -51,9 +51,9 @@ struct AllocationRequirements {
struct FragmentStorage { struct FragmentStorage {
const void *fragmentCpuPointer = nullptr; const void *fragmentCpuPointer = nullptr;
size_t fragmentSize = 0; size_t fragmentSize = 0;
int refCount = 0;
OsHandle *osInternalStorage = nullptr; OsHandle *osInternalStorage = nullptr;
ResidencyData *residency = nullptr; ResidencyData *residency = nullptr;
int refCount = 0;
bool driverAllocation = false; bool driverAllocation = false;
}; };

2
shared/source/os_interface/linux/xe/ioctl_helper_xe.h
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@@ -190,9 +190,9 @@ class IoctlHelperXe : public IoctlHelper {
std::unique_ptr<XeDrm::drm_xe_engine_class_instance> defaultEngine; std::unique_ptr<XeDrm::drm_xe_engine_class_instance> defaultEngine;
struct DebugMetadata { struct DebugMetadata {
DrmResourceClass type;
uint64_t offset; uint64_t offset;
uint64_t size; uint64_t size;
DrmResourceClass type;
bool isCookie; bool isCookie;
}; };