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https://github.com/intel/compute-runtime.git
synced 2026-01-05 09:09:04 +08:00
refactor: Passing information about the engine
Extension of the interface with information about the engine type passed to the function Related-To: NEO-10678 Signed-off-by: Andrzej Koska <andrzej.koska@intel.com>
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Compute-Runtime-Automation
parent
31b2dcfe57
commit
ae139aeffd
@@ -154,7 +154,7 @@ struct CommandList : _ze_command_list_handle_t {
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const size_t *pOffsets, ze_event_handle_t hSignalEvent,
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uint32_t numWaitEvents, ze_event_handle_t *phWaitEvents) = 0;
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virtual ze_result_t appendMILoadRegImm(uint32_t reg, uint32_t value) = 0;
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virtual ze_result_t appendMILoadRegImm(uint32_t reg, uint32_t value, bool isBcs) = 0;
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virtual ze_result_t appendMILoadRegReg(uint32_t reg1, uint32_t reg2) = 0;
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virtual ze_result_t appendMILoadRegMem(uint32_t reg1, uint64_t address) = 0;
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virtual ze_result_t appendMIStoreRegMem(uint32_t reg1, uint64_t address) = 0;
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2020-2023 Intel Corporation
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* Copyright (C) 2020-2024 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -14,7 +14,7 @@
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namespace L0 {
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template <GFXCORE_FAMILY gfxCoreFamily>
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ze_result_t CommandListCoreFamily<gfxCoreFamily>::appendMILoadRegImm(uint32_t reg, uint32_t value) {
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ze_result_t CommandListCoreFamily<gfxCoreFamily>::appendMILoadRegImm(uint32_t reg, uint32_t value, bool isBcs) {
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return ZE_RESULT_ERROR_UNSUPPORTED_FEATURE;
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}
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template <GFXCORE_FAMILY gfxCoreFamily>
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@@ -162,7 +162,7 @@ struct CommandListCoreFamily : public CommandListImp {
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uint32_t numWaitEvents,
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ze_event_handle_t *phWaitEvents, bool relaxedOrderingDispatch) override;
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ze_result_t appendMILoadRegImm(uint32_t reg, uint32_t value) override;
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ze_result_t appendMILoadRegImm(uint32_t reg, uint32_t value, bool isBcs) override;
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ze_result_t appendMILoadRegReg(uint32_t reg1, uint32_t reg2) override;
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ze_result_t appendMILoadRegMem(uint32_t reg1, uint64_t address) override;
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ze_result_t appendMIStoreRegMem(uint32_t reg1, uint64_t address) override;
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@@ -543,7 +543,7 @@ ze_result_t CommandListCoreFamily<gfxCoreFamily>::appendLaunchMultipleKernelsInd
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commandContainer.addToResidencyContainer(alloc);
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for (uint32_t i = 0; i < numKernels; i++) {
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NEO::EncodeMathMMIO<GfxFamily>::encodeGreaterThanPredicate(commandContainer, alloc->getGpuAddress(), i);
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NEO::EncodeMathMMIO<GfxFamily>::encodeGreaterThanPredicate(commandContainer, alloc->getGpuAddress(), i, isCopyOnly());
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ret = appendLaunchKernelWithParams(Kernel::fromHandle(kernelHandles[i]),
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pLaunchArgumentsBuffer[i],
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@@ -2518,7 +2518,7 @@ void CommandListCoreFamily<gfxCoreFamily>::appendWaitOnInOrderDependency(std::sh
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for (uint32_t i = 0; i < inOrderExecInfo->getNumDevicePartitionsToWait(); i++) {
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if (relaxedOrderingAllowed) {
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NEO::EncodeBatchBufferStartOrEnd<GfxFamily>::programConditionalDataMemBatchBufferStart(*commandContainer.getCommandStream(), 0, gpuAddress, waitValue, NEO::CompareOperation::less, true, isQwordInOrderCounter());
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NEO::EncodeBatchBufferStartOrEnd<GfxFamily>::programConditionalDataMemBatchBufferStart(*commandContainer.getCommandStream(), 0, gpuAddress, waitValue, NEO::CompareOperation::less, true, isQwordInOrderCounter(), isCopyOnly());
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} else {
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using MI_SEMAPHORE_WAIT = typename GfxFamily::MI_SEMAPHORE_WAIT;
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@@ -2784,8 +2784,8 @@ void CommandListCoreFamily<gfxCoreFamily>::appendWriteKernelTimestamp(Event *eve
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uint64_t contextAddress = ptrOffset(baseAddr, contextOffset);
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if (maskLsb) {
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NEO::EncodeMathMMIO<GfxFamily>::encodeBitwiseAndVal(commandContainer, RegisterOffsets::globalTimestampLdw, mask, globalAddress, workloadPartition, globalPostSyncCmdBuffer);
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NEO::EncodeMathMMIO<GfxFamily>::encodeBitwiseAndVal(commandContainer, RegisterOffsets::gpThreadTimeRegAddressOffsetLow, mask, contextAddress, workloadPartition, contextPostSyncCmdBuffer);
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NEO::EncodeMathMMIO<GfxFamily>::encodeBitwiseAndVal(commandContainer, RegisterOffsets::globalTimestampLdw, mask, globalAddress, workloadPartition, globalPostSyncCmdBuffer, isCopyOnly());
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NEO::EncodeMathMMIO<GfxFamily>::encodeBitwiseAndVal(commandContainer, RegisterOffsets::gpThreadTimeRegAddressOffsetLow, mask, contextAddress, workloadPartition, contextPostSyncCmdBuffer, isCopyOnly());
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} else {
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NEO::EncodeStoreMMIO<GfxFamily>::encode(*commandContainer.getCommandStream(), RegisterOffsets::globalTimestampLdw, globalAddress, workloadPartition, globalPostSyncCmdBuffer);
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NEO::EncodeStoreMMIO<GfxFamily>::encode(*commandContainer.getCommandStream(), RegisterOffsets::gpThreadTimeRegAddressOffsetLow, contextAddress, workloadPartition, contextPostSyncCmdBuffer);
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@@ -3593,8 +3593,8 @@ ze_result_t CommandListCoreFamily<gfxCoreFamily>::appendWaitOnMemory(void *desc,
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if (isQwordInOrderCounter()) {
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indirectMode = true;
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NEO::LriHelper<GfxFamily>::program(commandContainer.getCommandStream(), RegisterOffsets::csGprR0, getLowPart(data), true);
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NEO::LriHelper<GfxFamily>::program(commandContainer.getCommandStream(), RegisterOffsets::csGprR0 + 4, getHighPart(data), true);
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NEO::LriHelper<GfxFamily>::program(commandContainer.getCommandStream(), RegisterOffsets::csGprR0, getLowPart(data), true, isCopyOnly());
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NEO::LriHelper<GfxFamily>::program(commandContainer.getCommandStream(), RegisterOffsets::csGprR0 + 4, getHighPart(data), true, isCopyOnly());
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} else {
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return ZE_RESULT_ERROR_UNSUPPORTED_FEATURE;
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@@ -3850,7 +3850,7 @@ void CommandListCoreFamily<gfxCoreFamily>::appendWaitOnSingleEvent(Event *event,
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for (uint32_t i = 0u; i < packetsToWait; i++) {
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if (relaxedOrderingAllowed) {
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NEO::EncodeBatchBufferStartOrEnd<GfxFamily>::programConditionalDataMemBatchBufferStart(*commandContainer.getCommandStream(), 0, gpuAddr, Event::STATE_CLEARED,
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NEO::CompareOperation::equal, true, false);
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NEO::CompareOperation::equal, true, false, isCopyOnly());
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} else {
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NEO::EncodeSemaphore<GfxFamily>::addMiSemaphoreWaitCommand(*commandContainer.getCommandStream(),
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gpuAddr,
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@@ -4045,7 +4045,7 @@ void CommandListCoreFamily<gfxCoreFamily>::appendFullSynchronizedDispatchInit()
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// Patch Primary Tile section skip (to Secondary Tile section)
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NEO::EncodeBatchBufferStartOrEnd<GfxFamily>::programConditionalDataMemBatchBufferStart(skipPrimaryTileSectionCmdStream, cmdStream->getCurrentGpuAddressPosition(), workPartitionAllocationGpuVa, 0,
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NEO::CompareOperation::notEqual, false, false);
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NEO::CompareOperation::notEqual, false, false, isCopyOnly());
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// Secondary Tile section
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{
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@@ -4059,7 +4059,7 @@ void CommandListCoreFamily<gfxCoreFamily>::appendFullSynchronizedDispatchInit()
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// Patch Primary Tile section jump to end
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NEO::EncodeBatchBufferStartOrEnd<GfxFamily>::programConditionalDataMemBatchBufferStart(jumpToEndSectionFromPrimaryTile, cmdStream->getCurrentGpuAddressPosition(), syncAllocationGpuVa + sizeof(uint32_t), queueId,
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NEO::CompareOperation::equal, false, false);
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NEO::CompareOperation::equal, false, false, isCopyOnly());
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// End section
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NEO::EncodeMiPredicate<GfxFamily>::encode(*cmdStream, NEO::MiPredicateType::disable);
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@@ -473,13 +473,15 @@ ze_result_t CommandListCoreFamily<gfxCoreFamily>::appendLaunchKernelWithParams(K
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template <GFXCORE_FAMILY gfxCoreFamily>
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void CommandListCoreFamily<gfxCoreFamily>::appendMultiPartitionPrologue(uint32_t partitionDataSize) {
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NEO::ImplicitScalingDispatch<GfxFamily>::dispatchOffsetRegister(*commandContainer.getCommandStream(),
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partitionDataSize);
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partitionDataSize,
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isCopyOnly());
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}
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template <GFXCORE_FAMILY gfxCoreFamily>
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void CommandListCoreFamily<gfxCoreFamily>::appendMultiPartitionEpilogue() {
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NEO::ImplicitScalingDispatch<GfxFamily>::dispatchOffsetRegister(*commandContainer.getCommandStream(),
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NEO::ImplicitScalingDispatch<GfxFamily>::getImmediateWritePostSyncOffset());
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NEO::ImplicitScalingDispatch<GfxFamily>::getImmediateWritePostSyncOffset(),
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isCopyOnly());
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}
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template <GFXCORE_FAMILY gfxCoreFamily>
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@@ -568,7 +570,7 @@ void CommandListCoreFamily<gfxCoreFamily>::appendDispatchOffsetRegister(bool wor
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if (workloadPartitionEvent && !device->getL0GfxCoreHelper().hasUnifiedPostSyncAllocationLayout()) {
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auto offset = beforeProfilingCmds ? NEO::ImplicitScalingDispatch<GfxFamily>::getTimeStampPostSyncOffset() : NEO::ImplicitScalingDispatch<GfxFamily>::getImmediateWritePostSyncOffset();
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NEO::ImplicitScalingDispatch<GfxFamily>::dispatchOffsetRegister(*commandContainer.getCommandStream(), offset);
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NEO::ImplicitScalingDispatch<GfxFamily>::dispatchOffsetRegister(*commandContainer.getCommandStream(), offset, isCopyOnly());
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}
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}
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@@ -23,6 +23,7 @@
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#include "shared/source/helpers/api_specific_config.h"
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#include "shared/source/helpers/compiler_product_helper.h"
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#include "shared/source/helpers/definitions/command_encoder_args.h"
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#include "shared/source/helpers/engine_node_helper.h"
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#include "shared/source/helpers/gfx_core_helper.h"
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#include "shared/source/helpers/heap_base_address_model.h"
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#include "shared/source/helpers/pause_on_gpu_properties.h"
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@@ -1005,7 +1006,8 @@ void CommandQueueHw<gfxCoreFamily>::programCommandQueueDebugCmdsForSourceLevelOr
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if (isDebugEnabled && !this->commandQueueDebugCmdsProgrammed) {
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if (this->device->getL0Debugger()) {
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this->device->getL0Debugger()->programSbaAddressLoad(cmdStream,
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device->getL0Debugger()->getSbaTrackingBuffer(csr->getOsContext().getContextId())->getGpuAddress());
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device->getL0Debugger()->getSbaTrackingBuffer(csr->getOsContext().getContextId())->getGpuAddress(),
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NEO::EngineHelpers::isBcs(this->csr->getOsContext().getEngineType()));
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this->commandQueueDebugCmdsProgrammed = true;
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}
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}
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@@ -517,7 +517,8 @@ struct MockCommandList : public CommandList {
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ADDMETHOD_NOBASE(appendMILoadRegImm, ze_result_t, ZE_RESULT_SUCCESS,
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(uint32_t reg,
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uint32_t value));
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uint32_t value,
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bool isBcs));
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ADDMETHOD_NOBASE(appendMILoadRegReg, ze_result_t, ZE_RESULT_SUCCESS,
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(uint32_t reg1,
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@@ -1857,7 +1857,7 @@ HWTEST2_F(CommandListCreate, givenInOrderExecutionWhenDispatchingRelaxedOrdering
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lrrCmd++;
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EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(lrrCmd, 0, cmdList->inOrderExecInfo->getBaseDeviceAddress(), 2,
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NEO::CompareOperation::less, true, FamilyType::isQwordInOrderCounter));
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NEO::CompareOperation::less, true, FamilyType::isQwordInOrderCounter, false));
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}
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TEST_F(CommandListCreate, GivenGpuHangWhenCreatingImmCmdListWithSyncModeAndAppendBarrierThenAppendBarrierReturnsDeviceLost) {
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@@ -1969,7 +1969,7 @@ HWTEST2_F(InOrderCmdListTests, givenRelaxedOrderingWhenProgrammingTimestampEvent
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auto eventEndGpuVa = events[0]->getCompletionFieldGpuAddress(device);
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EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(lrrCmd, 0, eventEndGpuVa, static_cast<uint64_t>(Event::STATE_CLEARED),
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NEO::CompareOperation::equal, true, false));
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NEO::CompareOperation::equal, true, false, false));
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auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(ptrOffset(lrrCmd, EncodeBatchBufferStartOrEnd<FamilyType>::getCmdSizeConditionalDataMemBatchBufferStart(false)));
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ASSERT_NE(nullptr, sdiCmd);
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@@ -6393,7 +6393,7 @@ HWTEST2_F(MultiTileSynchronizedDispatchTests, givenFullSyncDispatchWhenAppending
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}
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// Primary Tile section skip - patching
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if (!RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(primaryTileSectionSkipVa, castToUint64(miPredicate), workPartitionGpuVa, 0, NEO::CompareOperation::notEqual, false, false)) {
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if (!RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(primaryTileSectionSkipVa, castToUint64(miPredicate), workPartitionGpuVa, 0, NEO::CompareOperation::notEqual, false, false, false)) {
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return false;
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}
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@@ -6409,7 +6409,7 @@ HWTEST2_F(MultiTileSynchronizedDispatchTests, givenFullSyncDispatchWhenAppending
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}
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// Jump to end from Primary Tile section - patching
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if (!RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(jumpToEndSectionFromPrimaryTile, castToUint64(miPredicate), syncAllocGpuVa + sizeof(uint32_t), queueId, NEO::CompareOperation::equal, false, false)) {
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if (!RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(jumpToEndSectionFromPrimaryTile, castToUint64(miPredicate), syncAllocGpuVa + sizeof(uint32_t), queueId, NEO::CompareOperation::equal, false, false, false)) {
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return false;
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}
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