mirror of
https://github.com/intel/compute-runtime.git
synced 2025-12-20 17:00:59 +08:00
Revert "performance: align structures for 64-bit platforms"
This reverts commit 9f07f56f7f.
Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
This commit is contained in:
committed by
Compute-Runtime-Automation
parent
ca72dff1ab
commit
af031ee0e3
@@ -13,8 +13,8 @@
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namespace NEO {
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struct CopyEngineState {
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TaskCountType taskCount = 0;
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aub_stream::EngineType engineType = aub_stream::EngineType::NUM_ENGINES;
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TaskCountType taskCount = 0;
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bool csrClientRegistered = false;
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bool isValid() const {
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@@ -24,21 +24,21 @@ struct CsrSelectionArgs {
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const size_t *imageOrigin = nullptr;
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};
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cl_command_type cmdType;
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const size_t *size = nullptr;
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Resource srcResource;
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Resource dstResource;
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const size_t *size = nullptr;
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cl_command_type cmdType;
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TransferDirection direction;
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CsrSelectionArgs(cl_command_type cmdType, const size_t *size)
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: size(size),
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cmdType(cmdType),
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: cmdType(cmdType),
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size(size),
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direction(TransferDirection::hostToHost) {}
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template <typename ResourceType>
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CsrSelectionArgs(cl_command_type cmdType, ResourceType *src, ResourceType *dst, uint32_t rootDeviceIndex, const size_t *size)
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: size(size),
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cmdType(cmdType) {
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: cmdType(cmdType),
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size(size) {
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if (src) {
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processResource(*src, rootDeviceIndex, this->srcResource);
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}
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@@ -25,20 +25,20 @@ using SvmFreeClbT = void(CL_CALLBACK *)(cl_command_queue queue,
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void *userData);
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struct SvmFreeUserData {
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cl_uint numSvmPointers;
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void **svmPointers;
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SvmFreeClbT clb;
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void *userData;
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cl_uint numSvmPointers;
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bool ownsEventDeletion;
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SvmFreeUserData(cl_uint numSvmPointers,
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void **svmPointers, SvmFreeClbT clb,
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void *userData,
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bool ownsEventDeletion)
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: svmPointers(svmPointers),
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: numSvmPointers(numSvmPointers),
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svmPointers(svmPointers),
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clb(clb),
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userData(userData),
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numSvmPointers(numSvmPointers),
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ownsEventDeletion(ownsEventDeletion){};
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};
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@@ -1251,7 +1251,7 @@ HWTEST_TEMPLATED_F(BlitEnqueueTaskCountTests, whenWaitUntilCompletionCalledThenW
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uint32_t gpgpuTaskCount = 123;
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uint32_t bcsTaskCount = 123;
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CopyEngineState bcsState{bcsTaskCount, bcsCsr->getOsContext().getEngineType()};
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CopyEngineState bcsState{bcsCsr->getOsContext().getEngineType(), bcsTaskCount};
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commandQueue->waitUntilComplete(gpgpuTaskCount, Range{&bcsState}, 0, false);
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EXPECT_EQ(gpgpuTaskCount, static_cast<UltCommandStreamReceiver<FamilyType> *>(gpgpuCsr)->latestWaitForCompletionWithTimeoutTaskCount.load());
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@@ -55,7 +55,7 @@ HWTEST_F(CommandQueueHwTest, whenCallingIsCompletedThenTestTaskCountValue) {
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bcsCsr->setupContext(*osContext);
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bcsCsr->initializeTagAllocation();
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EngineControl control(bcsCsr.get(), osContext.get());
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CopyEngineState state{1, aub_stream::EngineType::ENGINE_BCS, false};
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CopyEngineState state{aub_stream::EngineType::ENGINE_BCS, 1, false};
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MockCommandQueueHw<FamilyType> cmdQ(context, pClDevice, nullptr);
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@@ -47,7 +47,7 @@ HWTEST_F(ClTbxCommandStreamTests, givenTbxCsrWhenDispatchBlitEnqueueThenProcessC
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cmdQ.clearBcsEngines();
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cmdQ.bcsEngines[0] = &engineControl1;
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cmdQ.bcsStates[0] = {0, aub_stream::ENGINE_BCS, false};
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cmdQ.bcsStates[0] = {aub_stream::ENGINE_BCS, 0, false};
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cl_int error = CL_SUCCESS;
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std::unique_ptr<Buffer> buffer(Buffer::create(&context, 0, 1, nullptr, error));
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@@ -619,7 +619,7 @@ HWTEST_TEMPLATED_F(BcsBufferTests, givenAllBcsEnginesReadyWhenWaitingForEventThe
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ultCsr2.initializeTagAllocation();
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ultCsr2.setupContext(osContext);
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CopyEngineState copyEngineState = {2, aub_stream::EngineType::ENGINE_BCS2, false};
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CopyEngineState copyEngineState = {aub_stream::EngineType::ENGINE_BCS2, 2, false};
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EngineControl engineControl = {&ultCsr2, &osContext};
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auto bcs2Index = EngineHelpers::getBcsIndex(aub_stream::EngineType::ENGINE_BCS2);
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mockCmdQ->bcsStates[bcs2Index] = copyEngineState;
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@@ -1559,7 +1559,7 @@ TEST(ImageConvertDescriptorTest, givenClImageDescWhenConvertedThenCorrectImageDe
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}
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TEST(ImageConvertDescriptorTest, givenImageDescriptorWhenConvertedThenCorrectClImageDescIsReturned) {
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ImageDescriptor desc = {16, 24, 1, 1, 1024, 2048, ImageType::image2D, 1, 3, false};
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ImageDescriptor desc = {ImageType::image2D, 16, 24, 1, 1, 1024, 2048, 1, 3, false};
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auto clDesc = Image::convertDescriptor(desc);
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EXPECT_EQ(clDesc.image_type, static_cast<cl_mem_object_type>(CL_MEM_OBJECT_IMAGE2D));
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@@ -25,10 +25,10 @@ class CommandStreamReceiverHw : public CommandStreamReceiver {
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using STATE_BASE_ADDRESS = typename GfxFamily::STATE_BASE_ADDRESS;
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struct ImmediateFlushData {
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void *endPtr = nullptr;
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size_t estimatedSize = 0;
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size_t csrStartOffset = 0;
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PipelineSelectArgs pipelineSelectArgs{};
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size_t estimatedSize = 0;
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void *endPtr = nullptr;
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size_t csrStartOffset = 0;
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bool pipelineSelectFullConfigurationNeeded = false;
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bool pipelineSelectDirty = false;
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@@ -81,12 +81,12 @@ class CommandStreamReceiverSimulatedCommonHw : public CommandStreamReceiverHw<Gf
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struct EngineInfo {
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void *pLRCA;
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void *pGlobalHWStatusPage;
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void *pRingBuffer;
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size_t sizeRingBuffer;
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uint32_t ggttLRCA;
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void *pGlobalHWStatusPage;
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uint32_t ggttHWSP;
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void *pRingBuffer;
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uint32_t ggttRingBuffer;
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size_t sizeRingBuffer;
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uint32_t tailRingBuffer;
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} engineInfo = {};
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@@ -99,11 +99,11 @@ NEO::BatchBuffer::BatchBuffer(GraphicsAllocation *commandBufferAllocation, size_
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size_t usedSize, LinearStream *stream, void *endCmdPtr, uint32_t numCsrClients, bool hasStallingCmds,
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bool hasRelaxedOrderingDependencies, bool dispatchMonitorFence, bool taskCountUpdateOnly)
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: commandBufferAllocation(commandBufferAllocation), startOffset(startOffset),
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chainedBatchBufferStartOffset(chainedBatchBufferStartOffset), taskStartAddress(taskStartAddress), stream(stream), endCmdPtr(endCmdPtr),
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numCsrClients(numCsrClients), hasStallingCmds(hasStallingCmds), hasRelaxedOrderingDependencies(hasRelaxedOrderingDependencies),
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dispatchMonitorFence(dispatchMonitorFence), taskCountUpdateOnly(taskCountUpdateOnly), lowPriority(lowPriority), throttle(throttle),
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chainedBatchBuffer(chainedBatchBuffer), sliceCount(sliceCount),
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usedSize(usedSize) {}
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chainedBatchBufferStartOffset(chainedBatchBufferStartOffset), taskStartAddress(taskStartAddress), chainedBatchBuffer(chainedBatchBuffer),
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lowPriority(lowPriority),
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throttle(throttle), sliceCount(sliceCount),
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usedSize(usedSize), stream(stream), endCmdPtr(endCmdPtr), numCsrClients(numCsrClients), hasStallingCmds(hasStallingCmds),
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hasRelaxedOrderingDependencies(hasRelaxedOrderingDependencies), dispatchMonitorFence(dispatchMonitorFence), taskCountUpdateOnly(taskCountUpdateOnly) {}
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NEO::CommandBuffer::CommandBuffer(Device &device) : device(device) {
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flushStamp.reset(new FlushStampTracker(false));
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@@ -46,31 +46,30 @@ struct BatchBuffer {
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bool dispatchMonitorFence,
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bool taskCountUpdateOnly);
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BatchBuffer() {}
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PagingFenceSemaphoreInfo pagingFenceSemInfo{};
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GraphicsAllocation *commandBufferAllocation = nullptr;
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ResidencyContainer *allocationsForResidency = nullptr;
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size_t startOffset = 0u;
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size_t chainedBatchBufferStartOffset = 0u;
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uint64_t taskStartAddress = 0; // if task not available, use CSR stream
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GraphicsAllocation *chainedBatchBuffer = nullptr;
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bool lowPriority = false;
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QueueThrottle throttle = QueueThrottle::MEDIUM;
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uint64_t sliceCount = QueueSliceCount::defaultSliceCount;
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size_t usedSize = 0u;
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// only used in drm csr in gem close worker active mode
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LinearStream *stream = nullptr;
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void *endCmdPtr = nullptr;
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uint32_t numCsrClients = 0;
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PagingFenceSemaphoreInfo pagingFenceSemInfo{};
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bool hasStallingCmds = false;
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bool hasRelaxedOrderingDependencies = false;
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bool disableFlatRingBuffer = false;
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bool dispatchMonitorFence = false;
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bool taskCountUpdateOnly = false;
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bool lowPriority = false;
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QueueThrottle throttle = QueueThrottle::MEDIUM;
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GraphicsAllocation *chainedBatchBuffer = nullptr;
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uint64_t sliceCount = QueueSliceCount::defaultSliceCount;
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size_t usedSize = 0u;
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};
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struct CommandBuffer : public IDNode<CommandBuffer> {
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@@ -634,12 +634,12 @@ inline constexpr BtiValueT btiValue = -1;
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} // namespace Defaults
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struct PayloadArgumentBaseT {
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ArgTypeT argType = argTypeUnknown;
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OffsetT offset = Defaults::offset;
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SourceOffseT sourceOffset = Defaults::sourceOffset;
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SizeT size = 0;
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ArgIndexT argIndex = Defaults::argIndex;
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BtiValueT btiValue = Defaults::btiValue;
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ArgTypeT argType = argTypeUnknown;
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AddrmodeT addrmode = memoryAddressingModeUnknown;
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AddrspaceT addrspace = addressSpaceUnknown;
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AccessTypeT accessType = accessTypeUnknown;
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@@ -692,9 +692,9 @@ inline constexpr Slot slot = 0U;
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} // namespace Defaults
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struct PerThreadMemoryBufferBaseT {
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SizeT size = 0U;
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AllocationType allocationType = AllocationTypeUnknown;
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MemoryUsageT memoryUsage = MemoryUsageUnknown;
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SizeT size = 0U;
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IsSimtThreadT isSimtThread = Defaults::isSimtThread;
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Slot slot = Defaults::slot;
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};
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@@ -732,8 +732,8 @@ inline constexpr NormalizedT normalized = false;
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struct InlineSamplerBaseT {
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SamplerIndexT samplerIndex = Defaults::samplerIndex;
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FilterModeT filterMode = Defaults::filterMode;
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AddrModeT addrMode = Defaults::addrMode;
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FilterModeT filterMode = Defaults::filterMode;
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NormalizedT normalized = Defaults::normalized;
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};
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} // namespace InlineSamplers
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@@ -218,13 +218,13 @@ enum class ImageType {
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};
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struct ImageDescriptor {
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ImageType imageType;
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size_t imageWidth;
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size_t imageHeight;
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size_t imageDepth;
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size_t imageArraySize;
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size_t imageRowPitch;
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size_t imageSlicePitch;
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ImageType imageType;
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uint32_t numMipLevels;
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uint32_t numSamples;
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bool fromParent;
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@@ -51,9 +51,9 @@ struct AllocationRequirements {
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struct FragmentStorage {
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const void *fragmentCpuPointer = nullptr;
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size_t fragmentSize = 0;
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int refCount = 0;
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OsHandle *osInternalStorage = nullptr;
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ResidencyData *residency = nullptr;
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int refCount = 0;
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bool driverAllocation = false;
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};
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@@ -190,9 +190,9 @@ class IoctlHelperXe : public IoctlHelper {
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std::unique_ptr<XeDrm::drm_xe_engine_class_instance> defaultEngine;
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struct DebugMetadata {
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DrmResourceClass type;
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uint64_t offset;
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uint64_t size;
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DrmResourceClass type;
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bool isCookie;
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};
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