From afd22999cc4ea7c3c4c5ef91ef9059060e8b8a0c Mon Sep 17 00:00:00 2001 From: "Vysochyn, Illia" Date: Thu, 28 Nov 2024 16:31:41 +0000 Subject: [PATCH] refactor: Adjust RENDER_SURFACE_STATE structures naming Performs minor renaming (mostly capitalization) in order to align with specification. Renames L1_CACHE_POLICY to L1_CACHE_CONTROL. Related-To: NEO-13147 Signed-off-by: Vysochyn, Illia --- level_zero/core/source/image/image_hw.inl | 12 ++-- .../sources/debugger/test_l0_debugger_1.cpp | 6 +- .../unit_tests/sources/image/test_image.cpp | 4 +- .../xe_hpg_core/dg2/test_kernel_dg2.cpp | 6 +- .../xe_hpg_core/dg2/test_module_dg2.cpp | 4 +- opencl/source/mem_obj/image.inl | 10 +-- .../unit_test/mem_obj/image_set_arg_tests.cpp | 44 ++++++------- .../test_cmds_programming_xe2_hpg_core.cpp | 6 +- .../test_cmds_programming_xe_hpc_core.cpp | 6 +- .../dg2/test_cmds_programming_dg2.cpp | 12 ++-- .../test_cmds_programming_xe_hpg_core.cpp | 6 +- .../command_encoder_xehp_and_later.inl | 8 +-- .../gen12lp/hw_cmds_generated_gen12lp.inl | 20 +++--- .../hw_cmds_generated_xe2_hpg_core.inl | 64 +++++++++---------- .../xe3_core/hw_cmds_generated_xe3_core.inl | 64 +++++++++---------- .../hw_cmds_generated_xe_hpc_core.inl | 64 +++++++++---------- .../hw_cmds_generated_xe_hpg_core.inl | 64 +++++++++---------- shared/source/gmm_helper/resource_info.h | 2 +- .../blit_commands_helper_xehp_and_later.inl | 2 +- .../helpers/cache_policy_dg2_and_later.inl | 10 +-- .../state_base_address_xehp_and_later.inl | 4 +- shared/source/image/image_skl_and_later.inl | 8 +-- shared/source/image/image_surface_state.h | 6 +- .../gfx_core_helper_xe2_hpg_core.cpp | 4 +- .../gfx_core_helper_xe_hpc_core.cpp | 4 +- .../source/xe_hpg_core/enable_xe_hpg_core.cpp | 6 +- .../gfx_core_helper_xe_hpg_core.cpp | 4 +- .../common/mocks/mock_gmm_resource_info.h | 4 +- ...nd_encoder_tests_xe_hpg_core_and_later.cpp | 12 ++-- .../encoders/test_encode_states_dg2.cpp | 6 +- .../image_surface_state_tests_gen12lp.cpp | 10 +-- .../blit_commands_helper_tests_gen12lp.cpp | 2 +- .../unit_test/helpers/cache_policy_tests.cpp | 6 +- .../helpers/gfx_core_helper_tests.cpp | 4 +- .../gfx_core_helper_tests_dg2_and_later.cpp | 6 +- .../helpers/state_base_address_tests.cpp | 46 ++++++------- ...st_blit_commands_helper_xehp_and_later.cpp | 2 +- .../image/image_surface_state_tests.cpp | 4 +- .../os_interface/product_helper_tests.cpp | 24 +++---- ...image_surface_state_tests_xe2_hpg_core.cpp | 8 +-- .../xe2_hpg_core/test_encode_xe2_hpg_core.cpp | 8 +-- .../image_surface_state_tests_xe_hpc_core.cpp | 10 +-- .../xe_hpc_core/test_encode_xe_hpc_core.cpp | 8 +-- .../dg2/cache_policy_tests_dg2.cpp | 6 +- .../xe_hpg_core/dg2/test_encode_dg2.cpp | 10 +-- .../xe_hpg_core/hw_cmds_xe_hpg_core_tests.cpp | 8 +-- .../image_surface_state_tests_xe_hpg_core.cpp | 10 +-- 47 files changed, 322 insertions(+), 322 deletions(-) diff --git a/level_zero/core/source/image/image_hw.inl b/level_zero/core/source/image/image_hw.inl index 29feb387f8..9e2b8947c3 100644 --- a/level_zero/core/source/image/image_hw.inl +++ b/level_zero/core/source/image/image_hw.inl @@ -197,9 +197,9 @@ ze_result_t ImageCoreFamily::initialize(Device *device, const ze_ isMediaFormatLayout, minArrayElement, renderTargetViewExtent); NEO::setImageSurfaceStateDimensions(&surfaceState, imgInfo, __GMM_NO_CUBE_MAP, surfaceType, depth); - surfaceState.setSurfaceMinLod(0u); - surfaceState.setMipCountLod(0u); - NEO::setMipTailStartLod(&surfaceState, gmm); + surfaceState.setSurfaceMinLOD(0u); + surfaceState.setMIPCountLOD(0u); + NEO::setMipTailStartLOD(&surfaceState, gmm); if (!isMediaFormatLayout) { surfaceState.setShaderChannelSelectRed( @@ -309,9 +309,9 @@ ze_result_t ImageCoreFamily::initialize(Device *device, const ze_ desc->format.layout == ZE_IMAGE_FORMAT_LAYOUT_NV12, minArrayElement, renderTargetViewExtent); NEO::setImageSurfaceStateDimensions(&redescribedSurfaceState, imgInfoRedescirebed, __GMM_NO_CUBE_MAP, surfaceType, depth); - redescribedSurfaceState.setSurfaceMinLod(0u); - redescribedSurfaceState.setMipCountLod(0u); - NEO::setMipTailStartLod(&redescribedSurfaceState, gmm); + redescribedSurfaceState.setSurfaceMinLOD(0u); + redescribedSurfaceState.setMIPCountLOD(0u); + NEO::setMipTailStartLOD(&redescribedSurfaceState, gmm); if (imgInfoRedescirebed.surfaceFormat->gmmSurfaceFormat == GMM_FORMAT_R8_UINT_TYPE || imgInfoRedescirebed.surfaceFormat->gmmSurfaceFormat == GMM_FORMAT_R16_UINT_TYPE || diff --git a/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_1.cpp b/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_1.cpp index 8a99677c47..d0af5f3d87 100644 --- a/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_1.cpp +++ b/level_zero/core/test/unit_tests/sources/debugger/test_l0_debugger_1.cpp @@ -657,8 +657,8 @@ HWTEST2_F(L0DebuggerTest, givenDebuggerEnabledAndL1CachePolicyWBWhenAppendingThe auto bindlessHeapsHelper = device->getNEODevice()->getExecutionEnvironment()->rootDeviceEnvironments[device->getNEODevice()->getRootDeviceIndex()]->bindlessHeapsHelper.get(); NEO::RAIIProductHelperFactory> raii(*device->getNEODevice()->getExecutionEnvironment()->rootDeviceEnvironments[0]); - raii.mockProductHelper->returnedL1CachePolicy = RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB; - raii.mockProductHelper->returnedL1CachePolicyIfDebugger = RENDER_SURFACE_STATE::L1_CACHE_POLICY_WBP; + raii.mockProductHelper->returnedL1CachePolicy = RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB; + raii.mockProductHelper->returnedL1CachePolicyIfDebugger = RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WBP; std::unique_ptr mockModule = std::make_unique(device, nullptr, ModuleType::builtin); Mock<::L0::KernelImp> kernel; @@ -684,7 +684,7 @@ HWTEST2_F(L0DebuggerTest, givenDebuggerEnabledAndL1CachePolicyWBWhenAppendingThe auto debugSurface = static_cast(device)->getDebugSurface(); ASSERT_NE(debugSurface, nullptr); ASSERT_EQ(debugSurface->getGpuAddress(), debugSurfaceState->getSurfaceBaseAddress()); - EXPECT_EQ(debugSurfaceState->getL1CachePolicyL1CacheControl(), RENDER_SURFACE_STATE::L1_CACHE_POLICY_WBP); + EXPECT_EQ(debugSurfaceState->getL1CacheControlCachePolicy(), RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WBP); } HWTEST2_F(L0DebuggerTest, givenNotXeHpOrXeHpgCoreAndDebugIsActiveThenDisableL3CacheInGmmHelperIsNotSet, IsNotXeHpOrXeHpgCore) { diff --git a/level_zero/core/test/unit_tests/sources/image/test_image.cpp b/level_zero/core/test/unit_tests/sources/image/test_image.cpp index 2adf31d9e6..5885780357 100644 --- a/level_zero/core/test/unit_tests/sources/image/test_image.cpp +++ b/level_zero/core/test/unit_tests/sources/image/test_image.cpp @@ -762,8 +762,8 @@ HWTEST2_P(TestImageFormats, givenValidLayoutAndTypeWhenCreateImageCoreFamilyThen EXPECT_EQ(rss.getXOffsetForUOrUvPlane(), 0u); } - EXPECT_EQ(rss.getSurfaceMinLod(), 0u); - EXPECT_EQ(rss.getMipCountLod(), 0u); + EXPECT_EQ(rss.getSurfaceMinLOD(), 0u); + EXPECT_EQ(rss.getMIPCountLOD(), 0u); if (!isMediaFormatLayout) { EXPECT_EQ(rss.getShaderChannelSelectRed(), FamilyType::RENDER_SURFACE_STATE::SHADER_CHANNEL_SELECT::SHADER_CHANNEL_SELECT_RED); diff --git a/level_zero/core/test/unit_tests/xe_hpg_core/dg2/test_kernel_dg2.cpp b/level_zero/core/test/unit_tests/xe_hpg_core/dg2/test_kernel_dg2.cpp index 90d0590480..bd673e818e 100644 --- a/level_zero/core/test/unit_tests/xe_hpg_core/dg2/test_kernel_dg2.cpp +++ b/level_zero/core/test/unit_tests/xe_hpg_core/dg2/test_kernel_dg2.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2022-2023 Intel Corporation + * Copyright (C) 2022-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -49,14 +49,14 @@ HWTEST2_F(KernelTestDG2, givenKernelImpWhenSetBufferSurfaceStateCalledThenProgra auto argInfo = kernelImp->getImmutableData()->getDescriptor().payloadMappings.explicitArgs[argIndex].as(); auto surfaceStateAddressRaw = ptrOffset(kernelImp->getSurfaceStateHeapData(), argInfo.bindful); auto surfaceStateAddress = reinterpret_cast(const_cast(surfaceStateAddressRaw)); - EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB, surfaceStateAddress->getL1CachePolicyL1CacheControl()); + EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB, surfaceStateAddress->getL1CacheControlCachePolicy()); auto debugger = MockDebuggerL0Hw::allocate(neoDevice); neoDevice->getExecutionEnvironment()->rootDeviceEnvironments[0]->debugger.reset(debugger); kernelImp->setBufferSurfaceState(argIndex, devicePtr, gpuAlloc); surfaceStateAddressRaw = ptrOffset(kernelImp->getSurfaceStateHeapData(), argInfo.bindful); surfaceStateAddress = reinterpret_cast(const_cast(surfaceStateAddressRaw)); - EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_POLICY_WBP, surfaceStateAddress->getL1CachePolicyL1CacheControl()); + EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WBP, surfaceStateAddress->getL1CacheControlCachePolicy()); Kernel::fromHandle(kernelHandle)->destroy(); diff --git a/level_zero/core/test/unit_tests/xe_hpg_core/dg2/test_module_dg2.cpp b/level_zero/core/test/unit_tests/xe_hpg_core/dg2/test_module_dg2.cpp index 622edc93cc..42197d4076 100644 --- a/level_zero/core/test/unit_tests/xe_hpg_core/dg2/test_module_dg2.cpp +++ b/level_zero/core/test/unit_tests/xe_hpg_core/dg2/test_module_dg2.cpp @@ -78,7 +78,7 @@ HWTEST2_F(KernelDebugSurfaceDG2Test, givenDebuggerWhenPatchWithImplicitSurfaceCa auto debugSurfaceState = reinterpret_cast(kernel.surfaceStateHeapData.get()); debugSurfaceState = ptrOffset(debugSurfaceState, sizeof(RENDER_SURFACE_STATE)); - EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_POLICY_WBP, debugSurfaceState->getL1CachePolicyL1CacheControl()); + EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WBP, debugSurfaceState->getL1CacheControlCachePolicy()); } HWTEST2_F(KernelDebugSurfaceDG2Test, givenNoDebuggerWhenPatchWithImplicitSurfaceCalledThenCachePolicyIsWB, IsDG2) { @@ -138,7 +138,7 @@ HWTEST2_F(KernelDebugSurfaceDG2Test, givenNoDebuggerWhenPatchWithImplicitSurface auto debugSurfaceState = reinterpret_cast(kernel.surfaceStateHeapData.get()); debugSurfaceState = ptrOffset(debugSurfaceState, sizeof(RENDER_SURFACE_STATE)); - EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB, debugSurfaceState->getL1CachePolicyL1CacheControl()); + EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB, debugSurfaceState->getL1CacheControlCachePolicy()); } } // namespace ult diff --git a/opencl/source/mem_obj/image.inl b/opencl/source/mem_obj/image.inl index f6dc9cab11..f71c520207 100644 --- a/opencl/source/mem_obj/image.inl +++ b/opencl/source/mem_obj/image.inl @@ -65,9 +65,9 @@ void ImageHw::setImageArg(void *memory, bool setAsMediaBlockImage, ui } uint32_t mipCount = this->mipCount > 0 ? this->mipCount - 1 : 0; - surfaceState->setSurfaceMinLod(this->baseMipLevel + mipLevel); - surfaceState->setMipCountLod(mipCount); - setMipTailStartLod(surfaceState, gmm); + surfaceState->setSurfaceMinLOD(this->baseMipLevel + mipLevel); + surfaceState->setMIPCountLOD(mipCount); + setMipTailStartLOD(surfaceState, gmm); cl_channel_order imgChannelOrder = getSurfaceFormatInfo().oclImageFormat.image_channel_order; int shaderChannelValue = ImageHw::getShaderChannelValue(RENDER_SURFACE_STATE::SHADER_CHANNEL_SELECT_RED, imgChannelOrder); @@ -117,7 +117,7 @@ void ImageHw::setAuxParamsForMultisamples(RENDER_SURFACE_STATE *surfa DEBUG_BREAK_IF(releaseHelper == nullptr); EncodeSurfaceState::setAuxParamsForMCSCCS(surfaceState, releaseHelper); surfaceState->setAuxiliarySurfacePitch(mcsGmm->getUnifiedAuxPitchTiles()); - surfaceState->setAuxiliarySurfaceQpitch(mcsGmm->getAuxQPitch()); + surfaceState->setAuxiliarySurfaceQPitch(mcsGmm->getAuxQPitch()); EncodeSurfaceState::setClearColorParams(surfaceState, mcsGmm); setUnifiedAuxBaseAddress(surfaceState, mcsGmm); } else if (mcsGmm->unifiedAuxTranslationCapable()) { @@ -125,7 +125,7 @@ void ImageHw::setAuxParamsForMultisamples(RENDER_SURFACE_STATE *surfa } else { surfaceState->setAuxiliarySurfaceMode((typename RENDER_SURFACE_STATE::AUXILIARY_SURFACE_MODE)1); surfaceState->setAuxiliarySurfacePitch(mcsSurfaceInfo.pitch); - surfaceState->setAuxiliarySurfaceQpitch(mcsSurfaceInfo.qPitch); + surfaceState->setAuxiliarySurfaceQPitch(mcsSurfaceInfo.qPitch); surfaceState->setAuxiliarySurfaceBaseAddress(mcsAllocation->getGpuAddress()); } } else if (isDepthFormat(imageFormat) && surfaceState->getSurfaceFormat() != SURFACE_FORMAT::SURFACE_FORMAT_R32_FLOAT_X8X24_TYPELESS) { diff --git a/opencl/test/unit_test/mem_obj/image_set_arg_tests.cpp b/opencl/test/unit_test/mem_obj/image_set_arg_tests.cpp index 9e0f9f6afd..7f49f5c5b2 100644 --- a/opencl/test/unit_test/mem_obj/image_set_arg_tests.cpp +++ b/opencl/test/unit_test/mem_obj/image_set_arg_tests.cpp @@ -157,7 +157,7 @@ HWTEST_F(ImageSetArgTest, GivenNormalImageWhenSettingImageArgThenCorrectValueIsS auto computedWidth = surfaceState.getWidth(); EXPECT_EQ(srcImage->getImageDesc().image_width, computedWidth); - EXPECT_EQ(0u, surfaceState.getMipCountLod()); + EXPECT_EQ(0u, surfaceState.getMIPCountLOD()); } HWTEST_F(ImageSetArgTest, givenImageWhenSettingMipTailStartLodThenProgramValueFromGmmResourceinfo) { @@ -170,17 +170,17 @@ HWTEST_F(ImageSetArgTest, givenImageWhenSettingMipTailStartLodThenProgramValueFr EXPECT_NE(nullptr, gmm); auto mockGmmResourceInfo = static_cast(gmm->gmmResourceInfo.get()); - mockGmmResourceInfo->setMipTailStartLod(mipTailStartLod); + mockGmmResourceInfo->setMipTailStartLOD(mipTailStartLod); srcImage->setImageArg(&surfaceState, false, 0, pClDevice->getRootDeviceIndex()); - EXPECT_EQ(mipTailStartLod, surfaceState.getMipTailStartLod()); + EXPECT_EQ(mipTailStartLod, surfaceState.getMipTailStartLOD()); // default value delete gmm; srcAllocation->setDefaultGmm(nullptr); srcImage->setImageArg(&surfaceState, false, 0, pClDevice->getRootDeviceIndex()); - EXPECT_EQ(0u, surfaceState.getMipTailStartLod()); + EXPECT_EQ(0u, surfaceState.getMipTailStartLOD()); } HWTEST_F(ImageSetArgTest, givenCubeMapIndexWhenSetKernelArgImageIsCalledThenModifySurfaceState) { @@ -369,7 +369,7 @@ HWTEST2_F(ImageSetArgTest, WhenSettingKernelArgThenPropertiesAreSetCorrectly, Ma EXPECT_EQ(srcImage->getImageDesc().image_depth, surfaceState->getDepth()); EXPECT_EQ(srcImage->getImageDesc().image_depth, surfaceState->getRenderTargetViewExtent()); EXPECT_EQ(rPitch, surfaceState->getSurfacePitch()); - EXPECT_EQ(0u, surfaceState->getSurfaceQpitch() % 4); + EXPECT_EQ(0u, surfaceState->getSurfaceQPitch() % 4); EXPECT_EQ(srcImage->getSurfaceFormatInfo().surfaceFormat.genxSurfaceFormat, (SurfaceFormat)surfaceState->getSurfaceFormat()); EXPECT_EQ(RENDER_SURFACE_STATE::SURFACE_TYPE_SURFTYPE_3D, surfaceState->getSurfaceType()); EXPECT_EQ(expectedChannelRed, surfaceState->getShaderChannelSelectRed()); @@ -410,8 +410,8 @@ HWTEST_F(ImageSetArgTest, givenImage2DWithMipMapsWhenSetKernelArgIsCalledThenMip auto surfaceState = reinterpret_cast( ptrOffset(pKernel->getSurfaceStateHeap(), pKernelInfo->argAsImg(0).bindful)); - EXPECT_EQ((uint32_t)mipLevel, surfaceState->getSurfaceMinLod()); - EXPECT_EQ((uint32_t)mipCount, surfaceState->getMipCountLod() + 1); + EXPECT_EQ((uint32_t)mipLevel, surfaceState->getSurfaceMinLOD()); + EXPECT_EQ((uint32_t)mipCount, surfaceState->getMIPCountLOD() + 1); } HWTEST_F(ImageSetArgTest, Given2dArrayWhenSettingKernelArgThenPropertiesAreSetCorrectly) { @@ -443,7 +443,7 @@ HWTEST_F(ImageSetArgTest, Given2dArrayWhenSettingKernelArgThenPropertiesAreSetCo EXPECT_EQ(image2Darray->getImageDesc().image_array_size, surfaceState->getDepth()); EXPECT_EQ(image2Darray->getImageDesc().image_array_size, surfaceState->getRenderTargetViewExtent()); EXPECT_EQ(rPitch, surfaceState->getSurfacePitch()); - EXPECT_EQ(0u, surfaceState->getSurfaceQpitch() % 4); + EXPECT_EQ(0u, surfaceState->getSurfaceQPitch() % 4); EXPECT_EQ(image2Darray->getSurfaceFormatInfo().surfaceFormat.genxSurfaceFormat, (SurfaceFormat)surfaceState->getSurfaceFormat()); EXPECT_EQ(RENDER_SURFACE_STATE::SURFACE_TYPE_SURFTYPE_2D, surfaceState->getSurfaceType()); EXPECT_TRUE((SurfaceFormat)surfaceState->getSurfaceArray()); @@ -489,8 +489,8 @@ HWTEST_F(ImageSetArgTest, Given1dArrayWhenSettingKernelArgThenPropertiesAreSetCo EXPECT_EQ(image1Darray->getImageDesc().image_array_size, surfaceState->getDepth()); EXPECT_EQ(image1Darray->getImageDesc().image_array_size, surfaceState->getRenderTargetViewExtent()); EXPECT_EQ(image1Darray->getImageDesc().image_row_pitch, surfaceState->getSurfacePitch()); - EXPECT_EQ(0u, surfaceState->getSurfaceQpitch() % 4); - EXPECT_EQ(graphicsAllocation->getDefaultGmm()->queryQPitch(GMM_RESOURCE_TYPE::RESOURCE_1D), surfaceState->getSurfaceQpitch()); + EXPECT_EQ(0u, surfaceState->getSurfaceQPitch() % 4); + EXPECT_EQ(graphicsAllocation->getDefaultGmm()->queryQPitch(GMM_RESOURCE_TYPE::RESOURCE_1D), surfaceState->getSurfaceQPitch()); EXPECT_EQ(image1Darray->getSurfaceFormatInfo().surfaceFormat.genxSurfaceFormat, (SurfaceFormat)surfaceState->getSurfaceFormat()); EXPECT_EQ(RENDER_SURFACE_STATE::SURFACE_TYPE_SURFTYPE_1D, surfaceState->getSurfaceType()); @@ -544,7 +544,7 @@ HWTEST_F(ImageSetArgTest, givenMcsAllocationWhenSetArgIsCalledWithoutUnifiedAuxC RENDER_SURFACE_STATE::MULTISAMPLED_SURFACE_STORAGE_FORMAT::MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS); EXPECT_TRUE(surfaceState->getAuxiliarySurfaceMode() == (typename RENDER_SURFACE_STATE::AUXILIARY_SURFACE_MODE)1); EXPECT_EQ(msi.pitch, surfaceState->getAuxiliarySurfacePitch()); - EXPECT_EQ(msi.qPitch, surfaceState->getAuxiliarySurfaceQpitch()); + EXPECT_EQ(msi.qPitch, surfaceState->getAuxiliarySurfaceQPitch()); EXPECT_EQ(msi.multisampleCount, static_cast(surfaceState->getNumberOfMultisamples())); EXPECT_EQ(mcsAlloc->getGpuAddress(), surfaceState->getAuxiliarySurfaceBaseAddress()); @@ -580,7 +580,7 @@ HWTEST_F(ImageSetArgTest, givenDepthFormatWhenSetArgIsCalledThenProgramAuxFields RENDER_SURFACE_STATE::MULTISAMPLED_SURFACE_STORAGE_FORMAT::MULTISAMPLED_SURFACE_STORAGE_FORMAT_DEPTH_STENCIL); EXPECT_TRUE(surfaceState->getAuxiliarySurfaceMode() == AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_NONE); EXPECT_EQ(1u, surfaceState->getAuxiliarySurfacePitch()); - EXPECT_EQ(0u, surfaceState->getAuxiliarySurfaceQpitch()); + EXPECT_EQ(0u, surfaceState->getAuxiliarySurfaceQPitch()); EXPECT_EQ(msi.multisampleCount, static_cast(surfaceState->getNumberOfMultisamples())); EXPECT_EQ(0u, surfaceState->getAuxiliarySurfaceBaseAddress()); @@ -640,7 +640,7 @@ HWTEST_F(ImageSetArgTest, givenMcsAllocationAndCompressionWhenSetArgOnMultisampl RENDER_SURFACE_STATE::MULTISAMPLED_SURFACE_STORAGE_FORMAT::MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS); EXPECT_TRUE(surfaceState->getAuxiliarySurfaceMode() == (typename RENDER_SURFACE_STATE::AUXILIARY_SURFACE_MODE)1); EXPECT_EQ(msi.pitch, surfaceState->getAuxiliarySurfacePitch()); - EXPECT_EQ(msi.qPitch, surfaceState->getAuxiliarySurfaceQpitch()); + EXPECT_EQ(msi.qPitch, surfaceState->getAuxiliarySurfaceQPitch()); EXPECT_EQ(msi.multisampleCount, static_cast(surfaceState->getNumberOfMultisamples())); EXPECT_EQ(mcsAlloc->getGpuAddress(), surfaceState->getAuxiliarySurfaceBaseAddress()); } @@ -671,7 +671,7 @@ HWTEST_F(ImageSetArgTest, givenDepthFormatAndCompressionWhenSetArgOnMultisampled RENDER_SURFACE_STATE::MULTISAMPLED_SURFACE_STORAGE_FORMAT::MULTISAMPLED_SURFACE_STORAGE_FORMAT_DEPTH_STENCIL); EXPECT_TRUE(surfaceState->getAuxiliarySurfaceMode() == AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_NONE); EXPECT_EQ(1u, surfaceState->getAuxiliarySurfacePitch()); - EXPECT_EQ(0u, surfaceState->getAuxiliarySurfaceQpitch()); + EXPECT_EQ(0u, surfaceState->getAuxiliarySurfaceQPitch()); EXPECT_EQ(msi.multisampleCount, static_cast(surfaceState->getNumberOfMultisamples())); EXPECT_EQ(0u, surfaceState->getAuxiliarySurfaceBaseAddress()); } @@ -707,7 +707,7 @@ HWTEST_F(ImageSetArgTest, givenMcsAllocationWhenSetArgIsCalledWithUnifiedAuxCapa EXPECT_TRUE(EncodeSurfaceState::isAuxModeEnabled(surfaceState, mcsAlloc->getDefaultGmm())); EXPECT_EQ(1u, surfaceState->getAuxiliarySurfacePitch()); - EXPECT_EQ(0u, surfaceState->getAuxiliarySurfaceQpitch()); + EXPECT_EQ(0u, surfaceState->getAuxiliarySurfaceQPitch()); } HWTEST_F(ImageSetArgTest, givenMcsAllocationWhenSetArgIsCalledWithUnifiedAuxCapabilityAndMcsThenAuxBaseAddressIsSet) { @@ -776,7 +776,7 @@ HWTEST_F(ImageSetArgTest, givenMcsAllocationWhenSetArgIsCalledWithUnifiedAuxCapa pKernelInfo->argAsImg(0).bindful)); EXPECT_EQ(pitchValue, surfaceState->getAuxiliarySurfacePitch()); - EXPECT_EQ(qPitchValue, surfaceState->getAuxiliarySurfaceQpitch()); + EXPECT_EQ(qPitchValue, surfaceState->getAuxiliarySurfaceQPitch()); } HWTEST_F(ImageSetArgTest, GivenImageFrom1dBufferWhenSettingKernelArgThenPropertiesAreSetCorrectly) { @@ -821,9 +821,9 @@ HWTEST_F(ImageSetArgTest, GivenImageFrom1dBufferWhenSettingKernelArgThenProperti EXPECT_EQ(1u, surfaceState->getDepth()); EXPECT_EQ(1u, surfaceState->getRenderTargetViewExtent()); - EXPECT_EQ(0u, surfaceState->getSurfaceQpitch() % 4); + EXPECT_EQ(0u, surfaceState->getSurfaceQPitch() % 4); - EXPECT_EQ(0u, surfaceState->getSurfaceQpitch()); + EXPECT_EQ(0u, surfaceState->getSurfaceQPitch()); EXPECT_EQ(image->getSurfaceFormatInfo().surfaceFormat.genxSurfaceFormat, (SurfaceFormat)surfaceState->getSurfaceFormat()); EXPECT_EQ(RENDER_SURFACE_STATE::SURFACE_TYPE_SURFTYPE_BUFFER, surfaceState->getSurfaceType()); EXPECT_FALSE((SurfaceFormat)surfaceState->getSurfaceArray()); @@ -897,7 +897,7 @@ HWTEST_F(ImageSetArgTest, givenCompressedResourceWhenSettingImgArgThenSetCorrect EXPECT_TRUE(EncodeSurfaceState::isAuxModeEnabled(&surfaceState, srcAllocation->getDefaultGmm())); EXPECT_EQ(1u, surfaceState.getAuxiliarySurfacePitch()); - EXPECT_EQ(0u, surfaceState.getAuxiliarySurfaceQpitch()); + EXPECT_EQ(0u, surfaceState.getAuxiliarySurfaceQPitch()); } HWTEST_F(ImageSetArgTest, givenNonCompressedResourceWhenSettingImgArgThenDontSetAuxParams) { @@ -910,14 +910,14 @@ HWTEST_F(ImageSetArgTest, givenNonCompressedResourceWhenSettingImgArgThenDontSet gmm->setCompressionEnabled(false); mockGmmResInfo->getUnifiedAuxSurfaceOffsetCalled = 0u; - EXPECT_EQ(0u, surfaceState.getAuxiliarySurfaceQpitch()); + EXPECT_EQ(0u, surfaceState.getAuxiliarySurfaceQPitch()); EXPECT_EQ(1u, surfaceState.getAuxiliarySurfacePitch()); srcImage->setImageArg(&surfaceState, false, 0, pClDevice->getRootDeviceIndex()); EXPECT_TRUE(surfaceState.getAuxiliarySurfaceMode() == AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_NONE); EXPECT_EQ(1u, surfaceState.getAuxiliarySurfacePitch()); - EXPECT_EQ(0u, surfaceState.getAuxiliarySurfaceQpitch()); + EXPECT_EQ(0u, surfaceState.getAuxiliarySurfaceQPitch()); EXPECT_EQ(0u, surfaceState.getAuxiliarySurfaceBaseAddress()); EXPECT_EQ(0u, mockGmmResInfo->getUnifiedAuxSurfaceOffsetCalled); } @@ -986,7 +986,7 @@ HWTEST_F(ImageMediaBlockSetArgTest, WhenSettingKernelArgImageThenPropertiesAreCo EXPECT_EQ(srcImage->getImageDesc().image_depth, surfaceState->getDepth()); EXPECT_EQ(srcImage->getImageDesc().image_depth, surfaceState->getRenderTargetViewExtent()); EXPECT_EQ(rPitch, surfaceState->getSurfacePitch()); - EXPECT_EQ(0u, surfaceState->getSurfaceQpitch() % 4); + EXPECT_EQ(0u, surfaceState->getSurfaceQPitch() % 4); EXPECT_EQ(srcImage->getSurfaceFormatInfo().surfaceFormat.genxSurfaceFormat, (SurfaceFormat)surfaceState->getSurfaceFormat()); EXPECT_EQ(RENDER_SURFACE_STATE::SURFACE_TYPE_SURFTYPE_3D, surfaceState->getSurfaceType()); EXPECT_EQ(expectedChannelRed, surfaceState->getShaderChannelSelectRed()); diff --git a/opencl/test/unit_test/xe2_hpg_core/test_cmds_programming_xe2_hpg_core.cpp b/opencl/test/unit_test/xe2_hpg_core/test_cmds_programming_xe2_hpg_core.cpp index ee969a0083..30c133214e 100644 --- a/opencl/test/unit_test/xe2_hpg_core/test_cmds_programming_xe2_hpg_core.cpp +++ b/opencl/test/unit_test/xe2_hpg_core/test_cmds_programming_xe2_hpg_core.cpp @@ -42,7 +42,7 @@ XE2_HPG_CORETEST_F(CmdsProgrammingTestsXe2HpgCore, givenL3ToL1DebugFlagWhenState auto stateBaseAddress = static_cast(hwParserCsr.cmdStateBaseAddress); - auto actualL1CachePolocy = static_cast(stateBaseAddress->getL1CachePolicyL1CacheControl()); + auto actualL1CachePolocy = static_cast(stateBaseAddress->getL1CacheControlCachePolicy()); const uint8_t expectedL1CachePolicy = 0; EXPECT_EQ(expectedL1CachePolicy, actualL1CachePolocy); @@ -75,7 +75,7 @@ XE2_HPG_CORETEST_F(CmdsProgrammingTestsXe2HpgCore, whenAppendingRssThenProgramWt EncodeSurfaceState::encodeBuffer(args); - EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WBP, rssCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WBP, rssCmd.getL1CacheControlCachePolicy()); } XE2_HPG_CORETEST_F(CmdsProgrammingTestsXe2HpgCore, givenAlignedCacheableReadOnlyBufferThenChoseOclBufferConstPolicy) { @@ -100,7 +100,7 @@ XE2_HPG_CORETEST_F(CmdsProgrammingTestsXe2HpgCore, givenAlignedCacheableReadOnly const auto actualMocs = surfaceState.getMemoryObjectControlState(); EXPECT_EQ(expectedMocs, actualMocs); - auto actualL1CachePolocy = static_cast(surfaceState.getL1CachePolicyL1CacheControl()); + auto actualL1CachePolocy = static_cast(surfaceState.getL1CacheControlCachePolicy()); const uint8_t expectedL1CachePolicy = 0; EXPECT_EQ(expectedL1CachePolicy, actualL1CachePolocy); diff --git a/opencl/test/unit_test/xe_hpc_core/test_cmds_programming_xe_hpc_core.cpp b/opencl/test/unit_test/xe_hpc_core/test_cmds_programming_xe_hpc_core.cpp index 98ee654742..4fe66d9e9f 100644 --- a/opencl/test/unit_test/xe_hpc_core/test_cmds_programming_xe_hpc_core.cpp +++ b/opencl/test/unit_test/xe_hpc_core/test_cmds_programming_xe_hpc_core.cpp @@ -42,7 +42,7 @@ XE_HPC_CORETEST_F(CmdsProgrammingTestsXeHpcCore, givenL3ToL1DebugFlagWhenStatele auto stateBaseAddress = static_cast(hwParserCsr.cmdStateBaseAddress); - auto actualL1CachePolocy = static_cast(stateBaseAddress->getL1CachePolicyL1CacheControl()); + auto actualL1CachePolocy = static_cast(stateBaseAddress->getL1CacheControlCachePolicy()); const uint8_t expectedL1CachePolicy = 0; EXPECT_EQ(expectedL1CachePolicy, actualL1CachePolocy); @@ -75,7 +75,7 @@ XE_HPC_CORETEST_F(CmdsProgrammingTestsXeHpcCore, whenAppendingRssThenProgramWtL1 EncodeSurfaceState::encodeBuffer(args); - EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WBP, rssCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WBP, rssCmd.getL1CacheControlCachePolicy()); } XE_HPC_CORETEST_F(CmdsProgrammingTestsXeHpcCore, givenAlignedCacheableReadOnlyBufferThenChoseOclBufferConstPolicy) { @@ -100,7 +100,7 @@ XE_HPC_CORETEST_F(CmdsProgrammingTestsXeHpcCore, givenAlignedCacheableReadOnlyBu const auto actualMocs = surfaceState.getMemoryObjectControlState(); EXPECT_EQ(expectedMocs, actualMocs); - auto actualL1CachePolocy = static_cast(surfaceState.getL1CachePolicyL1CacheControl()); + auto actualL1CachePolocy = static_cast(surfaceState.getL1CacheControlCachePolicy()); const uint8_t expectedL1CachePolicy = 0; EXPECT_EQ(expectedL1CachePolicy, actualL1CachePolocy); diff --git a/opencl/test/unit_test/xe_hpg_core/dg2/test_cmds_programming_dg2.cpp b/opencl/test/unit_test/xe_hpg_core/dg2/test_cmds_programming_dg2.cpp index d50a8e6fc7..0e058889b0 100644 --- a/opencl/test/unit_test/xe_hpg_core/dg2/test_cmds_programming_dg2.cpp +++ b/opencl/test/unit_test/xe_hpg_core/dg2/test_cmds_programming_dg2.cpp @@ -45,7 +45,7 @@ DG2TEST_F(CmdsProgrammingTestsDg2, givenL3ToL1DebugFlagWhenStatelessMocsIsProgra auto stateBaseAddress = static_cast(hwParserCsr.cmdStateBaseAddress); - EXPECT_EQ(stateBaseAddress->getL1CachePolicyL1CacheControl(), STATE_BASE_ADDRESS::L1_CACHE_POLICY_WB); + EXPECT_EQ(stateBaseAddress->getL1CacheControlCachePolicy(), STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WB); } DG2TEST_F(CmdsProgrammingTestsDg2, givenL3ToL1DebugFlagAndDebuggerInitializedWhenStatelessMocsIsProgrammedThenItHasCorrectL1CachingOn) { @@ -66,7 +66,7 @@ DG2TEST_F(CmdsProgrammingTestsDg2, givenL3ToL1DebugFlagAndDebuggerInitializedWhe auto stateBaseAddress = static_cast(hwParserCsr.cmdStateBaseAddress); - EXPECT_EQ(stateBaseAddress->getL1CachePolicyL1CacheControl(), STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP); + EXPECT_EQ(stateBaseAddress->getL1CacheControlCachePolicy(), STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP); } DG2TEST_F(CmdsProgrammingTestsDg2, whenAppendingRssThenProgramWBL1CachePolicyUnlessDebuggerIsActive) { @@ -95,11 +95,11 @@ DG2TEST_F(CmdsProgrammingTestsDg2, whenAppendingRssThenProgramWBL1CachePolicyUnl args.areMultipleSubDevicesInContext = true; EncodeSurfaceState::encodeBuffer(args); - EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB, rssCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB, rssCmd.getL1CacheControlCachePolicy()); args.isDebuggerActive = true; EncodeSurfaceState::encodeBuffer(args); - EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WBP, rssCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WBP, rssCmd.getL1CacheControlCachePolicy()); } DG2TEST_F(CmdsProgrammingTestsDg2, givenAlignedCacheableReadOnlyBufferThenChoseOclBufferConstPolicy) { @@ -124,7 +124,7 @@ DG2TEST_F(CmdsProgrammingTestsDg2, givenAlignedCacheableReadOnlyBufferThenChoseO const auto actualMocs = surfaceState.getMemoryObjectControlState(); EXPECT_EQ(expectedMocs, actualMocs); - EXPECT_EQ(surfaceState.getL1CachePolicyL1CacheControl(), FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB); + EXPECT_EQ(surfaceState.getL1CacheControlCachePolicy(), FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB); alignedFree(ptr); } @@ -154,7 +154,7 @@ DG2TEST_F(CmdsProgrammingTestsDg2, givenAlignedCacheableReadOnlyBufferAndDebugge const auto actualMocs = surfaceState.getMemoryObjectControlState(); EXPECT_EQ(expectedMocs, actualMocs); - EXPECT_EQ(surfaceState.getL1CachePolicyL1CacheControl(), FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WBP); + EXPECT_EQ(surfaceState.getL1CacheControlCachePolicy(), FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WBP); alignedFree(ptr); } diff --git a/opencl/test/unit_test/xe_hpg_core/test_cmds_programming_xe_hpg_core.cpp b/opencl/test/unit_test/xe_hpg_core/test_cmds_programming_xe_hpg_core.cpp index a81bc2f5fe..3dcdc553f1 100644 --- a/opencl/test/unit_test/xe_hpg_core/test_cmds_programming_xe_hpg_core.cpp +++ b/opencl/test/unit_test/xe_hpg_core/test_cmds_programming_xe_hpg_core.cpp @@ -45,7 +45,7 @@ XE_HPG_CORETEST_F(CmdsProgrammingTestsXeHpgCore, givenL3ToL1DebugFlagWhenStatele auto stateBaseAddress = static_cast(hwParserCsr.cmdStateBaseAddress); - auto actualL1CachePolocy = static_cast(stateBaseAddress->getL1CachePolicyL1CacheControl()); + auto actualL1CachePolocy = static_cast(stateBaseAddress->getL1CacheControlCachePolicy()); const uint8_t expectedL1CachePolicy = 0; EXPECT_EQ(expectedL1CachePolicy, actualL1CachePolocy); @@ -78,7 +78,7 @@ XE_HPG_CORETEST_F(CmdsProgrammingTestsXeHpgCore, whenAppendingRssThenProgramWBPL EncodeSurfaceState::encodeBuffer(args); - EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WBP, rssCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WBP, rssCmd.getL1CacheControlCachePolicy()); } XE_HPG_CORETEST_F(CmdsProgrammingTestsXeHpgCore, givenAlignedCacheableReadOnlyBufferThenChoseOclBufferConstPolicy) { @@ -103,7 +103,7 @@ XE_HPG_CORETEST_F(CmdsProgrammingTestsXeHpgCore, givenAlignedCacheableReadOnlyBu const auto actualMocs = surfaceState.getMemoryObjectControlState(); EXPECT_EQ(expectedMocs, actualMocs); - auto actualL1CachePolocy = static_cast(surfaceState.getL1CachePolicyL1CacheControl()); + auto actualL1CachePolocy = static_cast(surfaceState.getL1CacheControlCachePolicy()); const uint8_t expectedL1CachePolicy = 0; EXPECT_EQ(expectedL1CachePolicy, actualL1CachePolocy); diff --git a/shared/source/command_container/command_encoder_xehp_and_later.inl b/shared/source/command_container/command_encoder_xehp_and_later.inl index 0f0133ed78..b3888a454e 100644 --- a/shared/source/command_container/command_encoder_xehp_and_later.inl +++ b/shared/source/command_container/command_encoder_xehp_and_later.inl @@ -1165,15 +1165,15 @@ void EncodeDispatchKernel::encodeWalkerPostSyncFields(WalkerType &walker template void EncodeSurfaceState::encodeExtraCacheSettings(R_SURFACE_STATE *surfaceState, const EncodeSurfaceStateArgs &args) { - using L1_CACHE_POLICY = typename R_SURFACE_STATE::L1_CACHE_POLICY; + using L1_CACHE_CONTROL = typename R_SURFACE_STATE::L1_CACHE_CONTROL; auto &productHelper = args.gmmHelper->getRootDeviceEnvironment().getHelper(); - auto cachePolicy = static_cast(productHelper.getL1CachePolicy(args.isDebuggerActive)); + auto cachePolicy = static_cast(productHelper.getL1CachePolicy(args.isDebuggerActive)); if (debugManager.flags.OverrideL1CacheControlInSurfaceState.get() != -1 && debugManager.flags.ForceAllResourcesUncached.get() == false) { - cachePolicy = static_cast(debugManager.flags.OverrideL1CacheControlInSurfaceState.get()); + cachePolicy = static_cast(debugManager.flags.OverrideL1CacheControlInSurfaceState.get()); } - surfaceState->setL1CachePolicyL1CacheControl(cachePolicy); + surfaceState->setL1CacheControlCachePolicy(cachePolicy); } template diff --git a/shared/source/generated/gen12lp/hw_cmds_generated_gen12lp.inl b/shared/source/generated/gen12lp/hw_cmds_generated_gen12lp.inl index 0f0ff69fe5..a01397de40 100644 --- a/shared/source/generated/gen12lp/hw_cmds_generated_gen12lp.inl +++ b/shared/source/generated/gen12lp/hw_cmds_generated_gen12lp.inl @@ -2425,11 +2425,11 @@ typedef struct tagRENDER_SURFACE_STATE { SURFACEQPITCH_BIT_SHIFT = 0x2, SURFACEQPITCH_ALIGN_SIZE = 0x4, } SURFACEQPITCH; - inline void setSurfaceQpitch(const uint32_t value) { + inline void setSurfaceQPitch(const uint32_t value) { DEBUG_BREAK_IF(value > 0x7fff); TheStructure.Common.SurfaceQpitch = value >> SURFACEQPITCH_BIT_SHIFT; } - inline uint32_t getSurfaceQpitch() const { + inline uint32_t getSurfaceQPitch() const { return TheStructure.Common.SurfaceQpitch << SURFACEQPITCH_BIT_SHIFT; } inline void setSampleTapDiscardDisable(const SAMPLE_TAP_DISCARD_DISABLE value) { @@ -2569,25 +2569,25 @@ typedef struct tagRENDER_SURFACE_STATE { inline RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION getRenderTargetAndSampleUnormRotation() const { return static_cast(TheStructure.Common.RenderTargetAndSampleUnormRotation); } - inline void setMipCountLod(const uint32_t value) { + inline void setMIPCountLOD(const uint32_t value) { DEBUG_BREAK_IF(value > 0xf); TheStructure.Common.MipCountLod = value; } - inline uint32_t getMipCountLod() const { + inline uint32_t getMIPCountLOD() const { return TheStructure.Common.MipCountLod; } - inline void setSurfaceMinLod(const uint32_t value) { + inline void setSurfaceMinLOD(const uint32_t value) { DEBUG_BREAK_IF(value > 0xf0); TheStructure.Common.SurfaceMinLod = value; } - inline uint32_t getSurfaceMinLod() const { + inline uint32_t getSurfaceMinLOD() const { return TheStructure.Common.SurfaceMinLod; } - inline void setMipTailStartLod(const uint32_t value) { + inline void setMipTailStartLOD(const uint32_t value) { DEBUG_BREAK_IF(value > 0xf00); TheStructure.Common.MipTailStartLod = value; } - inline uint32_t getMipTailStartLod() const { + inline uint32_t getMipTailStartLOD() const { return TheStructure.Common.MipTailStartLod; } inline void setCoherencyType(const COHERENCY_TYPE value) { @@ -2786,11 +2786,11 @@ typedef struct tagRENDER_SURFACE_STATE { AUXILIARYSURFACEQPITCH_BIT_SHIFT = 0x2, AUXILIARYSURFACEQPITCH_ALIGN_SIZE = 0x4, } AUXILIARYSURFACEQPITCH; - inline void setAuxiliarySurfaceQpitch(const uint32_t value) { + inline void setAuxiliarySurfaceQPitch(const uint32_t value) { DEBUG_BREAK_IF(value > 0x7fff0000L); TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch = value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT; } - inline uint32_t getAuxiliarySurfaceQpitch() const { + inline uint32_t getAuxiliarySurfaceQPitch() const { return TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch << AUXILIARYSURFACEQPITCH_BIT_SHIFT; } typedef enum tagAUXILIARYSURFACEBASEADDRESS { diff --git a/shared/source/generated/xe2_hpg_core/hw_cmds_generated_xe2_hpg_core.inl b/shared/source/generated/xe2_hpg_core/hw_cmds_generated_xe2_hpg_core.inl index 191b26b755..eb67842032 100644 --- a/shared/source/generated/xe2_hpg_core/hw_cmds_generated_xe2_hpg_core.inl +++ b/shared/source/generated/xe2_hpg_core/hw_cmds_generated_xe2_hpg_core.inl @@ -1948,13 +1948,13 @@ typedef struct tagRENDER_SURFACE_STATE { COHERENCY_TYPE_IA_COHERENT = 0x1, // patched from COHERENCY_TYPE_SYSTEM_COHERENT COHERENCY_TYPE_MULTI_GPU_COHERENT = 0x2, } COHERENCY_TYPE; - typedef enum tagL1_CACHE_POLICY { - L1_CACHE_POLICY_WBP = 0x0, - L1_CACHE_POLICY_UC = 0x1, - L1_CACHE_POLICY_WB = 0x2, - L1_CACHE_POLICY_WT = 0x3, - L1_CACHE_POLICY_WS = 0x4, - } L1_CACHE_POLICY; + typedef enum tagL1_CACHE_CONTROL { + L1_CACHE_CONTROL_WBP = 0x0, + L1_CACHE_CONTROL_UC = 0x1, + L1_CACHE_CONTROL_WB = 0x2, + L1_CACHE_CONTROL_WT = 0x3, + L1_CACHE_CONTROL_WS = 0x4, + } L1_CACHE_CONTROL; typedef enum tagAUXILIARY_SURFACE_MODE { AUXILIARY_SURFACE_MODE_AUX_NONE = 0x0, AUXILIARY_SURFACE_MODE_AUX_APPEND = 0x1, @@ -2000,7 +2000,7 @@ typedef struct tagRENDER_SURFACE_STATE { TheStructure.Common.NumberOfMultisamples = NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_1; TheStructure.Common.MultisampledSurfaceStorageFormat = MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS; TheStructure.Common.RenderTargetAndSampleUnormRotation = RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG; - TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_POLICY_WBP; + TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_CONTROL_WBP; TheStructure.Common.AuxiliarySurfaceMode = AUXILIARY_SURFACE_MODE_AUX_NONE; TheStructure.Common.CompressionFormat = COMPRESSION_FORMAT_CMF_R8; TheStructure.Common.EnableSamplerRouteToLsc = true; @@ -2121,11 +2121,11 @@ typedef struct tagRENDER_SURFACE_STATE { SURFACEQPITCH_BIT_SHIFT = 0x2, SURFACEQPITCH_ALIGN_SIZE = 0x4, } SURFACEQPITCH; - inline void setSurfaceQpitch(const uint32_t value) { + inline void setSurfaceQPitch(const uint32_t value) { UNRECOVERABLE_IF((value >> SURFACEQPITCH_BIT_SHIFT) > 0x1ffff); TheStructure.Common.SurfaceQpitch = value >> SURFACEQPITCH_BIT_SHIFT; } - inline uint32_t getSurfaceQpitch() const { + inline uint32_t getSurfaceQPitch() const { return TheStructure.Common.SurfaceQpitch << SURFACEQPITCH_BIT_SHIFT; } inline void setSampleTapDiscardDisable(const SAMPLE_TAP_DISCARD_DISABLE value) { @@ -2234,32 +2234,32 @@ typedef struct tagRENDER_SURFACE_STATE { inline RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION getRenderTargetAndSampleUnormRotation() const { return static_cast(TheStructure.Common.RenderTargetAndSampleUnormRotation); } - inline void setMipCountLod(const uint32_t value) { + inline void setMIPCountLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.MipCountLod = value; } - inline uint32_t getMipCountLod() const { + inline uint32_t getMIPCountLOD() const { return TheStructure.Common.MipCountLod; } - inline void setSurfaceMinLod(const uint32_t value) { + inline void setSurfaceMinLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.SurfaceMinLod = value; } - inline uint32_t getSurfaceMinLod() const { + inline uint32_t getSurfaceMinLOD() const { return TheStructure.Common.SurfaceMinLod; } - inline void setMipTailStartLod(const uint32_t value) { + inline void setMipTailStartLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.MipTailStartLod = value; } - inline uint32_t getMipTailStartLod() const { + inline uint32_t getMipTailStartLOD() const { return TheStructure.Common.MipTailStartLod; } - inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) { + inline void setL1CacheControlCachePolicy(const L1_CACHE_CONTROL value) { TheStructure.Common.L1CacheControlCachePolicy = value; } - inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const { - return static_cast(TheStructure.Common.L1CacheControlCachePolicy); + inline L1_CACHE_CONTROL getL1CacheControlCachePolicy() const { + return static_cast(TheStructure.Common.L1CacheControlCachePolicy); } inline void setEwaDisableForCube(const bool value) { TheStructure.Common.EwaDisableForCube = value; @@ -2409,11 +2409,11 @@ typedef struct tagRENDER_SURFACE_STATE { AUXILIARYSURFACEQPITCH_BIT_SHIFT = 0x2, AUXILIARYSURFACEQPITCH_ALIGN_SIZE = 0x4, } AUXILIARYSURFACEQPITCH; - inline void setAuxiliarySurfaceQpitch(const uint32_t value) { + inline void setAuxiliarySurfaceQPitch(const uint32_t value) { UNRECOVERABLE_IF((value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT) > 0x1ffff); TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch = value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT; } - inline uint32_t getAuxiliarySurfaceQpitch() const { + inline uint32_t getAuxiliarySurfaceQPitch() const { return TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch << AUXILIARYSURFACEQPITCH_BIT_SHIFT; } typedef enum tagAUXILIARYSURFACEBASEADDRESS { @@ -2990,13 +2990,13 @@ typedef struct tagSTATE_BASE_ADDRESS { typedef enum tagCOMMAND_TYPE { COMMAND_TYPE_GFXPIPE = 0x3, } COMMAND_TYPE; - typedef enum tagL1_CACHE_POLICY { - L1_CACHE_POLICY_WBP = 0x0, - L1_CACHE_POLICY_UC = 0x1, - L1_CACHE_POLICY_WB = 0x2, - L1_CACHE_POLICY_WT = 0x3, - L1_CACHE_POLICY_WS = 0x4, - } L1_CACHE_POLICY; + typedef enum tagL1_CACHE_CONTROL { + L1_CACHE_CONTROL_WBP = 0x0, + L1_CACHE_CONTROL_UC = 0x1, + L1_CACHE_CONTROL_WB = 0x2, + L1_CACHE_CONTROL_WT = 0x3, + L1_CACHE_CONTROL_WS = 0x4, + } L1_CACHE_CONTROL; typedef enum tagPATCH_CONSTANTS { // patched GENERALSTATEBASEADDRESS_BYTEOFFSET = 0x4, GENERALSTATEBASEADDRESS_INDEX = 0x1, @@ -3018,7 +3018,7 @@ typedef struct tagSTATE_BASE_ADDRESS { TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_COMMON; TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; - TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_POLICY_WBP; + TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_CONTROL_WBP; } static tagSTATE_BASE_ADDRESS sInit() { STATE_BASE_ADDRESS state; @@ -3087,11 +3087,11 @@ typedef struct tagSTATE_BASE_ADDRESS { uint32_t mocs = getStatelessDataPortAccessMemoryObjectControlStateEncryptedData(); return (TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables << 1) | mocs; } - inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) { + inline void setL1CacheControlCachePolicy(const L1_CACHE_CONTROL value) { TheStructure.Common.L1CacheControlCachePolicy = value; } - inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const { - return static_cast(TheStructure.Common.L1CacheControlCachePolicy); + inline L1_CACHE_CONTROL getL1CacheControlCachePolicy() const { + return static_cast(TheStructure.Common.L1CacheControlCachePolicy); } inline void setSurfaceStateBaseAddressModifyEnable(const bool value) { TheStructure.Common.SurfaceStateBaseAddressModifyEnable = value; diff --git a/shared/source/generated/xe3_core/hw_cmds_generated_xe3_core.inl b/shared/source/generated/xe3_core/hw_cmds_generated_xe3_core.inl index 6742ac905f..8c59c03ead 100644 --- a/shared/source/generated/xe3_core/hw_cmds_generated_xe3_core.inl +++ b/shared/source/generated/xe3_core/hw_cmds_generated_xe3_core.inl @@ -1947,13 +1947,13 @@ typedef struct tagRENDER_SURFACE_STATE { COHERENCY_TYPE_IA_COHERENT = 0x1, // patched from COHERENCY_TYPE_SYSTEM_COHERENT COHERENCY_TYPE_MULTI_GPU_COHERENT = 0x2, } COHERENCY_TYPE; - typedef enum tagL1_CACHE_POLICY { - L1_CACHE_POLICY_WBP = 0x0, - L1_CACHE_POLICY_UC = 0x1, - L1_CACHE_POLICY_WB = 0x2, - L1_CACHE_POLICY_WT = 0x3, - L1_CACHE_POLICY_WS = 0x4, - } L1_CACHE_POLICY; + typedef enum tagL1_CACHE_CONTROL { + L1_CACHE_CONTROL_WBP = 0x0, + L1_CACHE_CONTROL_UC = 0x1, + L1_CACHE_CONTROL_WB = 0x2, + L1_CACHE_CONTROL_WT = 0x3, + L1_CACHE_CONTROL_WS = 0x4, + } L1_CACHE_CONTROL; typedef enum tagAUXILIARY_SURFACE_MODE { AUXILIARY_SURFACE_MODE_AUX_NONE = 0x0, AUXILIARY_SURFACE_MODE_AUX_APPEND = 0x1, @@ -1998,7 +1998,7 @@ typedef struct tagRENDER_SURFACE_STATE { TheStructure.Common.NumberOfMultisamples = NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_1; TheStructure.Common.MultisampledSurfaceStorageFormat = MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS; TheStructure.Common.RenderTargetAndSampleUnormRotation = RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG; - TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_POLICY_WBP; + TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_CONTROL_WBP; TheStructure.Common.AuxiliarySurfaceMode = AUXILIARY_SURFACE_MODE_AUX_NONE; TheStructure.Common.CompressionFormat = COMPRESSION_FORMAT_CMF_R8; TheStructure._SurfaceFormatIsPlanar.HalfPitchForChroma = HALF_PITCH_FOR_CHROMA_DISABLE; @@ -2118,11 +2118,11 @@ typedef struct tagRENDER_SURFACE_STATE { SURFACEQPITCH_BIT_SHIFT = 0x2, SURFACEQPITCH_ALIGN_SIZE = 0x4, } SURFACEQPITCH; - inline void setSurfaceQpitch(const uint32_t value) { + inline void setSurfaceQPitch(const uint32_t value) { UNRECOVERABLE_IF((value >> SURFACEQPITCH_BIT_SHIFT) > 0x1ffff); TheStructure.Common.SurfaceQpitch = value >> SURFACEQPITCH_BIT_SHIFT; } - inline uint32_t getSurfaceQpitch() const { + inline uint32_t getSurfaceQPitch() const { return TheStructure.Common.SurfaceQpitch << SURFACEQPITCH_BIT_SHIFT; } inline void setBaseMipLevel(const uint32_t value) { @@ -2219,32 +2219,32 @@ typedef struct tagRENDER_SURFACE_STATE { inline RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION getRenderTargetAndSampleUnormRotation() const { return static_cast(TheStructure.Common.RenderTargetAndSampleUnormRotation); } - inline void setMipCountLod(const uint32_t value) { + inline void setMIPCountLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.MipCountLod = value; } - inline uint32_t getMipCountLod() const { + inline uint32_t getMIPCountLOD() const { return TheStructure.Common.MipCountLod; } - inline void setSurfaceMinLod(const uint32_t value) { + inline void setSurfaceMinLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.SurfaceMinLod = value; } - inline uint32_t getSurfaceMinLod() const { + inline uint32_t getSurfaceMinLOD() const { return TheStructure.Common.SurfaceMinLod; } - inline void setMipTailStartLod(const uint32_t value) { + inline void setMipTailStartLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.MipTailStartLod = value; } - inline uint32_t getMipTailStartLod() const { + inline uint32_t getMipTailStartLOD() const { return TheStructure.Common.MipTailStartLod; } - inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) { + inline void setL1CacheControlCachePolicy(const L1_CACHE_CONTROL value) { TheStructure.Common.L1CacheControlCachePolicy = value; } - inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const { - return static_cast(TheStructure.Common.L1CacheControlCachePolicy); + inline L1_CACHE_CONTROL getL1CacheControlCachePolicy() const { + return static_cast(TheStructure.Common.L1CacheControlCachePolicy); } inline void setEwaDisableForCube(const bool value) { TheStructure.Common.EwaDisableForCube = value; @@ -2399,11 +2399,11 @@ typedef struct tagRENDER_SURFACE_STATE { AUXILIARYSURFACEQPITCH_BIT_SHIFT = 0x2, AUXILIARYSURFACEQPITCH_ALIGN_SIZE = 0x4, } AUXILIARYSURFACEQPITCH; - inline void setAuxiliarySurfaceQpitch(const uint32_t value) { + inline void setAuxiliarySurfaceQPitch(const uint32_t value) { UNRECOVERABLE_IF((value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT) > 0x1ffff); TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch = value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT; } - inline uint32_t getAuxiliarySurfaceQpitch() const { + inline uint32_t getAuxiliarySurfaceQPitch() const { return TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch << AUXILIARYSURFACEQPITCH_BIT_SHIFT; } typedef enum tagAUXILIARYSURFACEBASEADDRESS { @@ -2980,13 +2980,13 @@ typedef struct tagSTATE_BASE_ADDRESS { typedef enum tagCOMMAND_TYPE { COMMAND_TYPE_GFXPIPE = 0x3, } COMMAND_TYPE; - typedef enum tagL1_CACHE_POLICY { - L1_CACHE_POLICY_WBP = 0x0, - L1_CACHE_POLICY_UC = 0x1, - L1_CACHE_POLICY_WB = 0x2, - L1_CACHE_POLICY_WT = 0x3, - L1_CACHE_POLICY_WS = 0x4, - } L1_CACHE_POLICY; + typedef enum tagL1_CACHE_CONTROL { + L1_CACHE_CONTROL_WBP = 0x0, + L1_CACHE_CONTROL_UC = 0x1, + L1_CACHE_CONTROL_WB = 0x2, + L1_CACHE_CONTROL_WT = 0x3, + L1_CACHE_CONTROL_WS = 0x4, + } L1_CACHE_CONTROL; typedef enum tagPATCH_CONSTANTS { // patched GENERALSTATEBASEADDRESS_BYTEOFFSET = 0x4, GENERALSTATEBASEADDRESS_INDEX = 0x1, @@ -3008,7 +3008,7 @@ typedef struct tagSTATE_BASE_ADDRESS { TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_COMMON; TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; - TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_POLICY_WBP; + TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_CONTROL_WBP; } static tagSTATE_BASE_ADDRESS sInit() { STATE_BASE_ADDRESS state; @@ -3077,11 +3077,11 @@ typedef struct tagSTATE_BASE_ADDRESS { uint32_t mocs = getStatelessDataPortAccessMemoryObjectControlStateEncryptedData(); return (TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables << 1) | mocs; } - inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) { + inline void setL1CacheControlCachePolicy(const L1_CACHE_CONTROL value) { TheStructure.Common.L1CacheControlCachePolicy = value; } - inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const { - return static_cast(TheStructure.Common.L1CacheControlCachePolicy); + inline L1_CACHE_CONTROL getL1CacheControlCachePolicy() const { + return static_cast(TheStructure.Common.L1CacheControlCachePolicy); } inline void setSurfaceStateBaseAddressModifyEnable(const bool value) { TheStructure.Common.SurfaceStateBaseAddressModifyEnable = value; diff --git a/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl b/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl index 689b461a4e..4ababcd0ca 100644 --- a/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl +++ b/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl @@ -1931,13 +1931,13 @@ typedef struct tagRENDER_SURFACE_STATE { COHERENCY_TYPE_IA_COHERENT = 0x1, // patched from COHERENCY_TYPE_SYSTEM_COHERENT COHERENCY_TYPE_MULTI_GPU_COHERENT = 0x2, } COHERENCY_TYPE; - typedef enum tagL1_CACHE_POLICY { // patched - L1_CACHE_POLICY_WBP = 0x0, - L1_CACHE_POLICY_UC = 0x1, - L1_CACHE_POLICY_WB = 0x2, - L1_CACHE_POLICY_WT = 0x3, - L1_CACHE_POLICY_WS = 0x4, - } L1_CACHE_POLICY; + typedef enum tagL1_CACHE_CONTROL { // patched + L1_CACHE_CONTROL_WBP = 0x0, + L1_CACHE_CONTROL_UC = 0x1, + L1_CACHE_CONTROL_WB = 0x2, + L1_CACHE_CONTROL_WT = 0x3, + L1_CACHE_CONTROL_WS = 0x4, + } L1_CACHE_CONTROL; typedef enum tagAUXILIARY_SURFACE_MODE { AUXILIARY_SURFACE_MODE_AUX_NONE = 0x0, AUXILIARY_SURFACE_MODE_AUX_CCS_D = 0x1, @@ -1995,7 +1995,7 @@ typedef struct tagRENDER_SURFACE_STATE { TheStructure.Common.RenderTargetAndSampleUnormRotation = RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG; TheStructure.Common.DecompressInL3 = DECOMPRESS_IN_L3_DISABLE; TheStructure.Common.CoherencyType = COHERENCY_TYPE_GPU_COHERENT; - TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_POLICY_WBP; + TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_CONTROL_WBP; TheStructure.Common.MemoryCompressionMode = MEMORY_COMPRESSION_MODE_HORIZONTAL; TheStructure._SurfaceFormatIsPlanar.HalfPitchForChroma = HALF_PITCH_FOR_CHROMA_DISABLE; TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceMode = AUXILIARY_SURFACE_MODE_AUX_NONE; @@ -2115,11 +2115,11 @@ typedef struct tagRENDER_SURFACE_STATE { SURFACEQPITCH_BIT_SHIFT = 0x2, SURFACEQPITCH_ALIGN_SIZE = 0x4, } SURFACEQPITCH; - inline void setSurfaceQpitch(const uint32_t value) { + inline void setSurfaceQPitch(const uint32_t value) { UNRECOVERABLE_IF((value >> SURFACEQPITCH_BIT_SHIFT) > 0x1ffff); TheStructure.Common.SurfaceQpitch = value >> SURFACEQPITCH_BIT_SHIFT; } - inline uint32_t getSurfaceQpitch() const { + inline uint32_t getSurfaceQPitch() const { return TheStructure.Common.SurfaceQpitch << SURFACEQPITCH_BIT_SHIFT; } inline void setSampleTapDiscardDisable(const SAMPLE_TAP_DISCARD_DISABLE value) { @@ -2235,25 +2235,25 @@ typedef struct tagRENDER_SURFACE_STATE { inline DECOMPRESS_IN_L3 getDecompressInL3() const { return static_cast(TheStructure.Common.DecompressInL3); } - inline void setMipCountLod(const uint32_t value) { + inline void setMIPCountLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.MipCountLod = value; } - inline uint32_t getMipCountLod() const { + inline uint32_t getMIPCountLOD() const { return TheStructure.Common.MipCountLod; } - inline void setSurfaceMinLod(const uint32_t value) { + inline void setSurfaceMinLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.SurfaceMinLod = value; } - inline uint32_t getSurfaceMinLod() const { + inline uint32_t getSurfaceMinLOD() const { return TheStructure.Common.SurfaceMinLod; } - inline void setMipTailStartLod(const uint32_t value) { + inline void setMipTailStartLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.MipTailStartLod = value; } - inline uint32_t getMipTailStartLod() const { + inline uint32_t getMipTailStartLOD() const { return TheStructure.Common.MipTailStartLod; } inline void setCoherencyType(const COHERENCY_TYPE value) { @@ -2262,11 +2262,11 @@ typedef struct tagRENDER_SURFACE_STATE { inline COHERENCY_TYPE getCoherencyType() const { return static_cast(TheStructure.Common.CoherencyType); } - inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) { // patched + inline void setL1CacheControlCachePolicy(const L1_CACHE_CONTROL value) { // patched TheStructure.Common.L1CacheControlCachePolicy = value; } - inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const { // patched - return static_cast(TheStructure.Common.L1CacheControlCachePolicy); + inline L1_CACHE_CONTROL getL1CacheControlCachePolicy() const { // patched + return static_cast(TheStructure.Common.L1CacheControlCachePolicy); } inline void setEwaDisableForCube(const bool value) { TheStructure.Common.EwaDisableForCube = value; @@ -2457,11 +2457,11 @@ typedef struct tagRENDER_SURFACE_STATE { AUXILIARYSURFACEQPITCH_BIT_SHIFT = 0x2, AUXILIARYSURFACEQPITCH_ALIGN_SIZE = 0x4, } AUXILIARYSURFACEQPITCH; - inline void setAuxiliarySurfaceQpitch(const uint32_t value) { + inline void setAuxiliarySurfaceQPitch(const uint32_t value) { UNRECOVERABLE_IF((value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT) > 0x1ffff); TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch = value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT; } - inline uint32_t getAuxiliarySurfaceQpitch() const { + inline uint32_t getAuxiliarySurfaceQPitch() const { return TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch << AUXILIARYSURFACEQPITCH_BIT_SHIFT; } typedef enum tagAUXILIARYSURFACEBASEADDRESS { @@ -3001,13 +3001,13 @@ typedef struct tagSTATE_BASE_ADDRESS { ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_DISABLED = 0x0, ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_ENABLED = 0x1, } ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES; - typedef enum tagL1_CACHE_POLICY { - L1_CACHE_POLICY_WBP = 0x0, - L1_CACHE_POLICY_UC = 0x1, - L1_CACHE_POLICY_WB = 0x2, - L1_CACHE_POLICY_WT = 0x3, - L1_CACHE_POLICY_WS = 0x4, - } L1_CACHE_POLICY; + typedef enum tagL1_CACHE_CONTROL { + L1_CACHE_CONTROL_WBP = 0x0, + L1_CACHE_CONTROL_UC = 0x1, + L1_CACHE_CONTROL_WB = 0x2, + L1_CACHE_CONTROL_WT = 0x3, + L1_CACHE_CONTROL_WS = 0x4, + } L1_CACHE_CONTROL; typedef enum tagPATCH_CONSTANTS { // patched GENERALSTATEBASEADDRESS_BYTEOFFSET = 0x4, GENERALSTATEBASEADDRESS_INDEX = 0x1, @@ -3031,7 +3031,7 @@ typedef struct tagSTATE_BASE_ADDRESS { TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; TheStructure.Common.CoherencySettingModifyEnable = COHERENCY_SETTING_MODIFY_ENABLE_DISABLE_WRITE_TO_THIS_DW; TheStructure.Common.EnableMemoryCompressionForAllStatelessAccesses = ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_DISABLED; - TheStructure.Common.L1CachePolicyL1CacheControl = L1_CACHE_POLICY_WBP; + TheStructure.Common.L1CachePolicyL1CacheControl = L1_CACHE_CONTROL_WBP; } static tagSTATE_BASE_ADDRESS sInit() { STATE_BASE_ADDRESS state; @@ -3099,11 +3099,11 @@ typedef struct tagSTATE_BASE_ADDRESS { mocs |= (TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables << 1); return (mocs); } - inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) { + inline void setL1CacheControlCachePolicy(const L1_CACHE_CONTROL value) { TheStructure.Common.L1CachePolicyL1CacheControl = value; } - inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const { - return static_cast(TheStructure.Common.L1CachePolicyL1CacheControl); + inline L1_CACHE_CONTROL getL1CacheControlCachePolicy() const { + return static_cast(TheStructure.Common.L1CachePolicyL1CacheControl); } inline void setSurfaceStateBaseAddressModifyEnable(const bool value) { diff --git a/shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl b/shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl index be77091be5..bb4bcca68c 100644 --- a/shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl +++ b/shared/source/generated/xe_hpg_core/hw_cmds_generated_xe_hpg_core.inl @@ -1665,13 +1665,13 @@ typedef struct tagRENDER_SURFACE_STATE { COHERENCY_TYPE_IA_COHERENT = 0x1, // patched from COHERENCY_TYPE_SYSTEM_COHERENT COHERENCY_TYPE_MULTI_GPU_COHERENT = 0x2, } COHERENCY_TYPE; - typedef enum tagL1_CACHE_POLICY { // patched - L1_CACHE_POLICY_WBP = 0x0, - L1_CACHE_POLICY_UC = 0x1, - L1_CACHE_POLICY_WB = 0x2, - L1_CACHE_POLICY_WT = 0x3, - L1_CACHE_POLICY_WS = 0x4, - } L1_CACHE_POLICY; + typedef enum tagL1_CACHE_CONTROL { // patched + L1_CACHE_CONTROL_WBP = 0x0, + L1_CACHE_CONTROL_UC = 0x1, + L1_CACHE_CONTROL_WB = 0x2, + L1_CACHE_CONTROL_WT = 0x3, + L1_CACHE_CONTROL_WS = 0x4, + } L1_CACHE_CONTROL; typedef enum tagAUXILIARY_SURFACE_MODE { AUXILIARY_SURFACE_MODE_AUX_NONE = 0x0, AUXILIARY_SURFACE_MODE_AUX_CCS_D = 0x1, @@ -1726,7 +1726,7 @@ typedef struct tagRENDER_SURFACE_STATE { TheStructure.Common.RenderTargetAndSampleUnormRotation = RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG; TheStructure.Common.DecompressInL3 = DECOMPRESS_IN_L3_DISABLE; TheStructure.Common.CoherencyType = COHERENCY_TYPE_GPU_COHERENT; - TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_POLICY_WBP; + TheStructure.Common.L1CacheControlCachePolicy = L1_CACHE_CONTROL_WBP; TheStructure.Common.MemoryCompressionType = MEMORY_COMPRESSION_TYPE_MEDIA_COMPRESSION; TheStructure._SurfaceFormatIsPlanar.HalfPitchForChroma = HALF_PITCH_FOR_CHROMA_DISABLE; TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceMode = AUXILIARY_SURFACE_MODE_AUX_NONE; @@ -1847,11 +1847,11 @@ typedef struct tagRENDER_SURFACE_STATE { SURFACEQPITCH_BIT_SHIFT = 0x2, SURFACEQPITCH_ALIGN_SIZE = 0x4, } SURFACEQPITCH; - inline void setSurfaceQpitch(const uint32_t value) { + inline void setSurfaceQPitch(const uint32_t value) { UNRECOVERABLE_IF((value >> SURFACEQPITCH_BIT_SHIFT) > 0x1ffff); TheStructure.Common.SurfaceQpitch = value >> SURFACEQPITCH_BIT_SHIFT; } - inline uint32_t getSurfaceQpitch() const { + inline uint32_t getSurfaceQPitch() const { return TheStructure.Common.SurfaceQpitch << SURFACEQPITCH_BIT_SHIFT; } inline void setSampleTapDiscardDisable(const SAMPLE_TAP_DISCARD_DISABLE value) { @@ -1966,25 +1966,25 @@ typedef struct tagRENDER_SURFACE_STATE { inline DECOMPRESS_IN_L3 getDecompressInL3() const { return static_cast(TheStructure.Common.DecompressInL3); } - inline void setMipCountLod(const uint32_t value) { + inline void setMIPCountLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.MipCountLod = value; } - inline uint32_t getMipCountLod() const { + inline uint32_t getMIPCountLOD() const { return TheStructure.Common.MipCountLod; } - inline void setSurfaceMinLod(const uint32_t value) { + inline void setSurfaceMinLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.SurfaceMinLod = value; } - inline uint32_t getSurfaceMinLod() const { + inline uint32_t getSurfaceMinLOD() const { return TheStructure.Common.SurfaceMinLod; } - inline void setMipTailStartLod(const uint32_t value) { + inline void setMipTailStartLOD(const uint32_t value) { UNRECOVERABLE_IF(value > 0xf); TheStructure.Common.MipTailStartLod = value; } - inline uint32_t getMipTailStartLod() const { + inline uint32_t getMipTailStartLOD() const { return TheStructure.Common.MipTailStartLod; } inline void setCoherencyType(const COHERENCY_TYPE value) { @@ -1993,11 +1993,11 @@ typedef struct tagRENDER_SURFACE_STATE { inline COHERENCY_TYPE getCoherencyType() const { return static_cast(TheStructure.Common.CoherencyType); } - inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) { // patched + inline void setL1CacheControlCachePolicy(const L1_CACHE_CONTROL value) { // patched TheStructure.Common.L1CacheControlCachePolicy = value; } - inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const { // patched - return static_cast(TheStructure.Common.L1CacheControlCachePolicy); + inline L1_CACHE_CONTROL getL1CacheControlCachePolicy() const { // patched + return static_cast(TheStructure.Common.L1CacheControlCachePolicy); } inline void setEwaDisableForCube(const bool value) { TheStructure.Common.EwaDisableForCube = value; @@ -2194,11 +2194,11 @@ typedef struct tagRENDER_SURFACE_STATE { AUXILIARYSURFACEQPITCH_BIT_SHIFT = 0x2, AUXILIARYSURFACEQPITCH_ALIGN_SIZE = 0x4, } AUXILIARYSURFACEQPITCH; - inline void setAuxiliarySurfaceQpitch(const uint32_t value) { + inline void setAuxiliarySurfaceQPitch(const uint32_t value) { UNRECOVERABLE_IF((value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT) > 0x1ffff); TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch = value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT; } - inline uint32_t getAuxiliarySurfaceQpitch() const { + inline uint32_t getAuxiliarySurfaceQPitch() const { return TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch << AUXILIARYSURFACEQPITCH_BIT_SHIFT; } typedef enum tagAUXILIARYSURFACEBASEADDRESS { @@ -2747,13 +2747,13 @@ typedef struct tagSTATE_BASE_ADDRESS { ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_DISABLED = 0x0, ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_ENABLED = 0x1, } ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES; - typedef enum tagL1_CACHE_POLICY { - L1_CACHE_POLICY_WBP = 0x0, - L1_CACHE_POLICY_UC = 0x1, - L1_CACHE_POLICY_WB = 0x2, - L1_CACHE_POLICY_WT = 0x3, - L1_CACHE_POLICY_WS = 0x4, - } L1_CACHE_POLICY; + typedef enum tagL1_CACHE_CONTROL { + L1_CACHE_CONTROL_WBP = 0x0, + L1_CACHE_CONTROL_UC = 0x1, + L1_CACHE_CONTROL_WB = 0x2, + L1_CACHE_CONTROL_WT = 0x3, + L1_CACHE_CONTROL_WS = 0x4, + } L1_CACHE_CONTROL; typedef enum tagPATCH_CONSTANTS { GENERALSTATEBASEADDRESS_BYTEOFFSET = 0x4, GENERALSTATEBASEADDRESS_INDEX = 0x1, @@ -2776,7 +2776,7 @@ typedef struct tagSTATE_BASE_ADDRESS { TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_COMMON; TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; TheStructure.Common.EnableMemoryCompressionForAllStatelessAccesses = ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_DISABLED; - TheStructure.Common.L1CachePolicyL1CacheControl = L1_CACHE_POLICY_WBP; + TheStructure.Common.L1CachePolicyL1CacheControl = L1_CACHE_CONTROL_WBP; } static tagSTATE_BASE_ADDRESS sInit() { STATE_BASE_ADDRESS state; @@ -2839,11 +2839,11 @@ typedef struct tagSTATE_BASE_ADDRESS { inline uint32_t getStatelessDataPortAccessMemoryObjectControlStateReserved() const { return (TheStructure.Common.StatelessDataPortAccessMemoryObjectControlState_Reserved); } - inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) { + inline void setL1CacheControlCachePolicy(const L1_CACHE_CONTROL value) { TheStructure.Common.L1CachePolicyL1CacheControl = value; } - inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const { - return static_cast(TheStructure.Common.L1CachePolicyL1CacheControl); + inline L1_CACHE_CONTROL getL1CacheControlCachePolicy() const { + return static_cast(TheStructure.Common.L1CachePolicyL1CacheControl); } inline void setStatelessDataPortAccessMemoryObjectControlState(const uint32_t value) { TheStructure.Common.StatelessDataPortAccessMemoryObjectControlState_Reserved = value; diff --git a/shared/source/gmm_helper/resource_info.h b/shared/source/gmm_helper/resource_info.h index 3f17e4d43b..8e8b11e522 100644 --- a/shared/source/gmm_helper/resource_info.h +++ b/shared/source/gmm_helper/resource_info.h @@ -74,7 +74,7 @@ class GmmResourceInfo : NonCopyableOrMovableClass { MOCKABLE_VIRTUAL uint64_t getUnifiedAuxSurfaceOffset(GMM_UNIFIED_AUX_TYPE auxType) { return resourceInfo->GetUnifiedAuxSurfaceOffset(auxType); } - MOCKABLE_VIRTUAL uint32_t getMipTailStartLodSurfaceState() { return resourceInfo->GetMipTailStartLodSurfaceState(); } + MOCKABLE_VIRTUAL uint32_t getMipTailStartLODSurfaceState() { return resourceInfo->GetMipTailStartLodSurfaceState(); } MOCKABLE_VIRTUAL bool is64KBPageSuitable() const { return resourceInfo->Is64KBPageSuitable(); } diff --git a/shared/source/helpers/blit_commands_helper_xehp_and_later.inl b/shared/source/helpers/blit_commands_helper_xehp_and_later.inl index 55fdbc5ebe..c3467b3375 100644 --- a/shared/source/helpers/blit_commands_helper_xehp_and_later.inl +++ b/shared/source/helpers/blit_commands_helper_xehp_and_later.inl @@ -192,7 +192,7 @@ void BlitCommandsHelper::getBlitAllocationProperties(const GraphicsAl const RootDeviceEnvironment &rootDeviceEnvironment, GMM_YUV_PLANE_ENUM plane) { if (allocation.getDefaultGmm()) { auto gmmResourceInfo = allocation.getDefaultGmm()->gmmResourceInfo.get(); - mipTailLod = gmmResourceInfo->getMipTailStartLodSurfaceState(); + mipTailLod = gmmResourceInfo->getMipTailStartLODSurfaceState(); auto resInfo = gmmResourceInfo->getResourceFlags()->Info; if (resInfo.Tile4) { tileType = GMM_TILED_4; diff --git a/shared/source/helpers/cache_policy_dg2_and_later.inl b/shared/source/helpers/cache_policy_dg2_and_later.inl index edf551a731..99f37c33fe 100644 --- a/shared/source/helpers/cache_policy_dg2_and_later.inl +++ b/shared/source/helpers/cache_policy_dg2_and_later.inl @@ -20,11 +20,11 @@ const char *L1CachePolicyHelper::getCachingPolicyOptions(bool isDebu static constexpr const char *uncachedCachingPolicy = "-cl-store-cache-default=2 -cl-load-cache-default=2"; switch (L1CachePolicyHelper::getL1CachePolicy(isDebuggerActive)) { - case GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP: + case GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP: return writeByPassCachingPolicy; - case GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WB: + case GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WB: return writeBackCachingPolicy; - case GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_UC: + case GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_UC: return uncachedCachingPolicy; default: return nullptr; @@ -34,13 +34,13 @@ const char *L1CachePolicyHelper::getCachingPolicyOptions(bool isDebu template uint32_t L1CachePolicyHelper::getDefaultL1CachePolicy(bool isDebuggerActive) { using GfxFamily = typename HwMapper::GfxFamily; - return GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP; + return GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP; } template uint32_t L1CachePolicyHelper::getUncachedL1CachePolicy() { using GfxFamily = typename HwMapper::GfxFamily; - return GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_UC; + return GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_UC; } } // namespace NEO diff --git a/shared/source/helpers/state_base_address_xehp_and_later.inl b/shared/source/helpers/state_base_address_xehp_and_later.inl index 86d23ea9a6..18a7d1670a 100644 --- a/shared/source/helpers/state_base_address_xehp_and_later.inl +++ b/shared/source/helpers/state_base_address_xehp_and_later.inl @@ -134,11 +134,11 @@ uint32_t StateBaseAddressHelper::getMaxBindlessSurfaceStates() { template void StateBaseAddressHelper::appendExtraCacheSettings(StateBaseAddressHelperArgs &args) { auto cachePolicy = args.isDebuggerActive ? args.l1CachePolicyDebuggerActive : args.l1CachePolicy; - args.stateBaseAddressCmd->setL1CachePolicyL1CacheControl(static_cast(cachePolicy)); + args.stateBaseAddressCmd->setL1CacheControlCachePolicy(static_cast(cachePolicy)); if (debugManager.flags.ForceStatelessL1CachingPolicy.get() != -1 && debugManager.flags.ForceAllResourcesUncached.get() == false) { - args.stateBaseAddressCmd->setL1CachePolicyL1CacheControl(static_cast(debugManager.flags.ForceStatelessL1CachingPolicy.get())); + args.stateBaseAddressCmd->setL1CacheControlCachePolicy(static_cast(debugManager.flags.ForceStatelessL1CachingPolicy.get())); } } diff --git a/shared/source/image/image_skl_and_later.inl b/shared/source/image/image_skl_and_later.inl index 93158a6530..fd665bff9e 100644 --- a/shared/source/image/image_skl_and_later.inl +++ b/shared/source/image/image_skl_and_later.inl @@ -1,15 +1,15 @@ /* - * Copyright (C) 2020-2021 Intel Corporation + * Copyright (C) 2020-2024 Intel Corporation * * SPDX-License-Identifier: MIT * */ template <> -void setMipTailStartLod(Family::RENDER_SURFACE_STATE *surfaceState, Gmm *gmm) { - surfaceState->setMipTailStartLod(0); +void setMipTailStartLOD(Family::RENDER_SURFACE_STATE *surfaceState, Gmm *gmm) { + surfaceState->setMipTailStartLOD(0); if (gmm != nullptr) { - surfaceState->setMipTailStartLod(gmm->gmmResourceInfo->getMipTailStartLodSurfaceState()); + surfaceState->setMipTailStartLOD(gmm->gmmResourceInfo->getMipTailStartLODSurfaceState()); } } diff --git a/shared/source/image/image_surface_state.h b/shared/source/image/image_surface_state.h index 72131a3f14..c4bd681ecf 100644 --- a/shared/source/image/image_surface_state.h +++ b/shared/source/image/image_surface_state.h @@ -51,13 +51,13 @@ inline void setImageSurfaceState(typename GfxFamily::RENDER_SURFACE_STATE *surfa surfaceState->setAuxiliarySurfaceMode(AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_NONE); surfaceState->setAuxiliarySurfacePitch(1u); - surfaceState->setAuxiliarySurfaceQpitch(0u); + surfaceState->setAuxiliarySurfaceQPitch(0u); surfaceState->setAuxiliarySurfaceBaseAddress(0u); surfaceState->setRenderTargetViewExtent(renderTargetViewExtent); surfaceState->setMinimumArrayElement(minimumArrayElement); // SurfaceQpitch is in rows but must be a multiple of VALIGN - surfaceState->setSurfaceQpitch(imageInfo.qPitch); + surfaceState->setSurfaceQPitch(imageInfo.qPitch); surfaceState->setSurfaceArray(isImageArray); @@ -136,6 +136,6 @@ inline void setUnifiedAuxBaseAddress(typename GfxFamily::RENDER_SURFACE_STATE *s } template -void setMipTailStartLod(typename GfxFamily::RENDER_SURFACE_STATE *surfaceState, Gmm *gmm); +void setMipTailStartLOD(typename GfxFamily::RENDER_SURFACE_STATE *surfaceState, Gmm *gmm); } // namespace NEO diff --git a/shared/source/xe2_hpg_core/gfx_core_helper_xe2_hpg_core.cpp b/shared/source/xe2_hpg_core/gfx_core_helper_xe2_hpg_core.cpp index cbbcf349c0..f6711eb4fd 100644 --- a/shared/source/xe2_hpg_core/gfx_core_helper_xe2_hpg_core.cpp +++ b/shared/source/xe2_hpg_core/gfx_core_helper_xe2_hpg_core.cpp @@ -216,9 +216,9 @@ inline void MemorySynchronizationCommands::setBarrierExtraProperties(voi template <> void GfxCoreHelperHw::setL1CachePolicy(bool useL1Cache, typename Family::RENDER_SURFACE_STATE *surfaceState, const HardwareInfo *hwInfo) const { if (useL1Cache) { - surfaceState->setL1CachePolicyL1CacheControl(Family::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB); + surfaceState->setL1CacheControlCachePolicy(Family::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB); if (debugManager.flags.OverrideL1CacheControlInSurfaceStateForScratchSpace.get() != -1) { - surfaceState->setL1CachePolicyL1CacheControl(static_cast(debugManager.flags.OverrideL1CacheControlInSurfaceStateForScratchSpace.get())); + surfaceState->setL1CacheControlCachePolicy(static_cast(debugManager.flags.OverrideL1CacheControlInSurfaceStateForScratchSpace.get())); } } } diff --git a/shared/source/xe_hpc_core/gfx_core_helper_xe_hpc_core.cpp b/shared/source/xe_hpc_core/gfx_core_helper_xe_hpc_core.cpp index 4dd2fa31fc..c049d0ebda 100644 --- a/shared/source/xe_hpc_core/gfx_core_helper_xe_hpc_core.cpp +++ b/shared/source/xe_hpc_core/gfx_core_helper_xe_hpc_core.cpp @@ -199,9 +199,9 @@ size_t MemorySynchronizationCommands::getSizeForAdditonalSynchronization template <> void GfxCoreHelperHw::setL1CachePolicy(bool useL1Cache, typename Family::RENDER_SURFACE_STATE *surfaceState, const HardwareInfo *hwInfo) const { if (useL1Cache) { - surfaceState->setL1CachePolicyL1CacheControl(Family::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB); + surfaceState->setL1CacheControlCachePolicy(Family::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB); if (debugManager.flags.OverrideL1CacheControlInSurfaceStateForScratchSpace.get() != -1) { - surfaceState->setL1CachePolicyL1CacheControl(static_cast(debugManager.flags.OverrideL1CacheControlInSurfaceStateForScratchSpace.get())); + surfaceState->setL1CacheControlCachePolicy(static_cast(debugManager.flags.OverrideL1CacheControlInSurfaceStateForScratchSpace.get())); } } } diff --git a/shared/source/xe_hpg_core/enable_xe_hpg_core.cpp b/shared/source/xe_hpg_core/enable_xe_hpg_core.cpp index 626d14d906..dd6e5e2198 100644 --- a/shared/source/xe_hpg_core/enable_xe_hpg_core.cpp +++ b/shared/source/xe_hpg_core/enable_xe_hpg_core.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021-2023 Intel Corporation + * Copyright (C) 2021-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -17,9 +17,9 @@ template <> uint32_t L1CachePolicyHelper::getDefaultL1CachePolicy(bool isDebuggerActive) { using GfxFamily = HwMapper::GfxFamily; if (isDebuggerActive) { - return GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP; + return GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP; } - return GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WB; + return GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WB; } template struct L1CachePolicyHelper; diff --git a/shared/source/xe_hpg_core/gfx_core_helper_xe_hpg_core.cpp b/shared/source/xe_hpg_core/gfx_core_helper_xe_hpg_core.cpp index 6beb296879..09e7e693a5 100644 --- a/shared/source/xe_hpg_core/gfx_core_helper_xe_hpg_core.cpp +++ b/shared/source/xe_hpg_core/gfx_core_helper_xe_hpg_core.cpp @@ -64,9 +64,9 @@ bool GfxCoreHelperHw::is1MbAlignmentSupported(const HardwareInfo &hwInfo template <> void GfxCoreHelperHw::setL1CachePolicy(bool useL1Cache, typename Family::RENDER_SURFACE_STATE *surfaceState, const HardwareInfo *hwInfo) const { if (useL1Cache) { - surfaceState->setL1CachePolicyL1CacheControl(Family::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB); + surfaceState->setL1CacheControlCachePolicy(Family::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB); if (debugManager.flags.OverrideL1CacheControlInSurfaceStateForScratchSpace.get() != -1) { - surfaceState->setL1CachePolicyL1CacheControl(static_cast(debugManager.flags.OverrideL1CacheControlInSurfaceStateForScratchSpace.get())); + surfaceState->setL1CacheControlCachePolicy(static_cast(debugManager.flags.OverrideL1CacheControlInSurfaceStateForScratchSpace.get())); } } } diff --git a/shared/test/common/mocks/mock_gmm_resource_info.h b/shared/test/common/mocks/mock_gmm_resource_info.h index 37e43ab041..36f9422fd6 100644 --- a/shared/test/common/mocks/mock_gmm_resource_info.h +++ b/shared/test/common/mocks/mock_gmm_resource_info.h @@ -55,7 +55,7 @@ class MockGmmResourceInfo : public GmmResourceInfo { uint32_t getAuxQPitch() override { return auxQPitch; } - uint32_t getMipTailStartLodSurfaceState() override { return mipTailStartLod; } + uint32_t getMipTailStartLODSurfaceState() override { return mipTailStartLod; } GMM_RESOURCE_FORMAT getResourceFormat() override { return mockResourceCreateParams.Format; } @@ -104,7 +104,7 @@ class MockGmmResourceInfo : public GmmResourceInfo { void setUnifiedAuxPitchTiles(uint32_t value); void setAuxQPitch(uint32_t value); - void setMipTailStartLod(uint32_t newMipTailStartLod) { mipTailStartLod = newMipTailStartLod; } + void setMipTailStartLOD(uint32_t newMipTailStartLod) { mipTailStartLod = newMipTailStartLod; } void refreshHandle() override { refreshHandleCalled++; diff --git a/shared/test/unit_test/command_container/command_encoder_tests_xe_hpg_core_and_later.cpp b/shared/test/unit_test/command_container/command_encoder_tests_xe_hpg_core_and_later.cpp index 7f3b2c2d3c..4c47a7c40b 100644 --- a/shared/test/unit_test/command_container/command_encoder_tests_xe_hpg_core_and_later.cpp +++ b/shared/test/unit_test/command_container/command_encoder_tests_xe_hpg_core_and_later.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021-2023 Intel Corporation + * Copyright (C) 2021-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -28,7 +28,7 @@ HWTEST2_F(CommandEncoderXeHpgCorePlusTests, givenSpecifiedL1CacheControlWhenAppe auto rssCmd = FamilyType::cmdInitRenderSurfaceState; - auto l1CacheControl = FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WBP; + auto l1CacheControl = FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WBP; debugManager.flags.OverrideL1CacheControlInSurfaceState.set(l1CacheControl); NEO::EncodeSurfaceStateArgs args; @@ -43,18 +43,18 @@ HWTEST2_F(CommandEncoderXeHpgCorePlusTests, givenSpecifiedL1CacheControlWhenAppe EncodeSurfaceState::encodeBuffer(args); - EXPECT_EQ(static_cast(l1CacheControl), rssCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(static_cast(l1CacheControl), rssCmd.getL1CacheControlCachePolicy()); - l1CacheControl = FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB; + l1CacheControl = FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB; debugManager.flags.OverrideL1CacheControlInSurfaceState.set(l1CacheControl); EncodeSurfaceState::encodeBuffer(args); - EXPECT_EQ(static_cast(l1CacheControl), rssCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(static_cast(l1CacheControl), rssCmd.getL1CacheControlCachePolicy()); debugManager.flags.ForceAllResourcesUncached.set(true); EncodeSurfaceState::encodeBuffer(args); - EXPECT_EQ(static_cast(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_UC), rssCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(static_cast(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_UC), rssCmd.getL1CacheControlCachePolicy()); memoryManager->freeGraphicsMemory(allocation); } diff --git a/shared/test/unit_test/encoders/test_encode_states_dg2.cpp b/shared/test/unit_test/encoders/test_encode_states_dg2.cpp index 6c49e5d505..d989d66094 100644 --- a/shared/test/unit_test/encoders/test_encode_states_dg2.cpp +++ b/shared/test/unit_test/encoders/test_encode_states_dg2.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2022-2023 Intel Corporation + * Copyright (C) 2022-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -40,7 +40,7 @@ HWTEST2_F(CommandEncodeStatesDG2Test, givenCommandContainerWhenSetStateBaseAddre auto cmd = genCmdCast(*itorCmd); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WB, cmd->getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WB, cmd->getL1CacheControlCachePolicy()); } HWTEST2_F(CommandEncodeStatesDG2Test, givenCommandContainerAndDebuggerWhenSetStateBaseAddressCalledThenCachePolicyIsWBP, IsDG2) { @@ -64,5 +64,5 @@ HWTEST2_F(CommandEncodeStatesDG2Test, givenCommandContainerAndDebuggerWhenSetSta auto cmd = genCmdCast(*itorCmd); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP, cmd->getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP, cmd->getL1CacheControlCachePolicy()); } diff --git a/shared/test/unit_test/gen12lp/image_surface_state_tests_gen12lp.cpp b/shared/test/unit_test/gen12lp/image_surface_state_tests_gen12lp.cpp index f89c16818b..7ed036c90a 100644 --- a/shared/test/unit_test/gen12lp/image_surface_state_tests_gen12lp.cpp +++ b/shared/test/unit_test/gen12lp/image_surface_state_tests_gen12lp.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2020-2023 Intel Corporation + * Copyright (C) 2020-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -44,11 +44,11 @@ GEN12LPTEST_F(ImageSurfaceStateTestsGen12LP, givenGmmWithMediaCompressedWhenSetM auto surfaceState = std::make_unique(size); auto castSurfaceState = reinterpret_cast(surfaceState.get()); - setMipTailStartLod(castSurfaceState, nullptr); + setMipTailStartLOD(castSurfaceState, nullptr); - EXPECT_EQ(castSurfaceState->getMipTailStartLod(), 0u); + EXPECT_EQ(castSurfaceState->getMipTailStartLOD(), 0u); - setMipTailStartLod(castSurfaceState, mockGmm.get()); + setMipTailStartLOD(castSurfaceState, mockGmm.get()); - EXPECT_EQ(castSurfaceState->getMipTailStartLod(), mockGmm->gmmResourceInfo->getMipTailStartLodSurfaceState()); + EXPECT_EQ(castSurfaceState->getMipTailStartLOD(), mockGmm->gmmResourceInfo->getMipTailStartLODSurfaceState()); } diff --git a/shared/test/unit_test/helpers/blit_commands_helper_tests_gen12lp.cpp b/shared/test/unit_test/helpers/blit_commands_helper_tests_gen12lp.cpp index 11691ef97b..19c7dc2ffd 100644 --- a/shared/test/unit_test/helpers/blit_commands_helper_tests_gen12lp.cpp +++ b/shared/test/unit_test/helpers/blit_commands_helper_tests_gen12lp.cpp @@ -168,7 +168,7 @@ struct MyMockResourecInfo : public GmmResourceInfo { GMM_RESOURCE_FLAG *getResourceFlags() override { return &flags; } - uint32_t getMipTailStartLodSurfaceState() override { + uint32_t getMipTailStartLODSurfaceState() override { return 0; } size_t pitch = 0; diff --git a/shared/test/unit_test/helpers/cache_policy_tests.cpp b/shared/test/unit_test/helpers/cache_policy_tests.cpp index 1f8f0ca2fa..e9962b11f4 100644 --- a/shared/test/unit_test/helpers/cache_policy_tests.cpp +++ b/shared/test/unit_test/helpers/cache_policy_tests.cpp @@ -25,13 +25,13 @@ HWTEST2_F(ProductHelperTest, givenL1CachePolicyHelperWhenUnsupportedL1PoliciesAn HWTEST2_F(ProductHelperTest, givenAtLeastXeHpgCoreWhenGetL1CachePolicyThenReturnCorrectValue, IsAtLeastXeHpgCore) { using GfxFamily = typename HwMapper::GfxFamily; - EXPECT_EQ(L1CachePolicyHelper::getL1CachePolicy(false), GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP); - EXPECT_EQ(L1CachePolicyHelper::getL1CachePolicy(true), GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP); + EXPECT_EQ(L1CachePolicyHelper::getL1CachePolicy(false), GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP); + EXPECT_EQ(L1CachePolicyHelper::getL1CachePolicy(true), GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP); } HWTEST2_F(ProductHelperTest, givenAtLeastXeHpgCoreWhenGetUncached1CachePolicyThenReturnCorrectValue, IsAtLeastXeHpgCore) { using GfxFamily = typename HwMapper::GfxFamily; - EXPECT_EQ(L1CachePolicyHelper::getUncachedL1CachePolicy(), GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_UC); + EXPECT_EQ(L1CachePolicyHelper::getUncachedL1CachePolicy(), GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_UC); } HWTEST2_F(ProductHelperTest, givenAtLeastXeHpgCoreAndWriteBackPolicyWhenGetL1CachePolicyThenReturnCorrectValue, IsAtLeastXeHpgCore) { diff --git a/shared/test/unit_test/helpers/gfx_core_helper_tests.cpp b/shared/test/unit_test/helpers/gfx_core_helper_tests.cpp index 0201ad00d1..77f1cb0ae9 100644 --- a/shared/test/unit_test/helpers/gfx_core_helper_tests.cpp +++ b/shared/test/unit_test/helpers/gfx_core_helper_tests.cpp @@ -117,12 +117,12 @@ HWTEST2_F(GfxCoreHelperTest, WhenSettingRenderSurfaceStateForBufferThenL1CachePo gfxCoreHelper.setRenderSurfaceStateForScratchResource(rootDeviceEnvironment, stateBuffer, size, addr, offset, pitch, nullptr, false, type, false, false); - EXPECT_NE(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB, surfaceState->getL1CachePolicyL1CacheControl()); + EXPECT_NE(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB, surfaceState->getL1CacheControlCachePolicy()); gfxCoreHelper.setRenderSurfaceStateForScratchResource(rootDeviceEnvironment, stateBuffer, size, addr, offset, pitch, nullptr, false, type, false, true); - EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB, surfaceState->getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB, surfaceState->getL1CacheControlCachePolicy()); alignedFree(stateBuffer); } diff --git a/shared/test/unit_test/helpers/gfx_core_helper_tests_dg2_and_later.cpp b/shared/test/unit_test/helpers/gfx_core_helper_tests_dg2_and_later.cpp index 1f84d1f8a5..136a3c9ef2 100644 --- a/shared/test/unit_test/helpers/gfx_core_helper_tests_dg2_and_later.cpp +++ b/shared/test/unit_test/helpers/gfx_core_helper_tests_dg2_and_later.cpp @@ -33,7 +33,7 @@ HWTEST2_F(GfxCoreHelperDg2AndLaterTest, GivenUseL1CacheAsTrueWhenCallSetL1CacheP RENDER_SURFACE_STATE surfaceState = FamilyType::cmdInitRenderSurfaceState; bool useL1Cache = true; helper.setL1CachePolicy(useL1Cache, &surfaceState, defaultHwInfo.get()); - EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB, surfaceState.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB, surfaceState.getL1CacheControlCachePolicy()); } HWTEST2_F(GfxCoreHelperDg2AndLaterTest, GivenOverrideL1CacheControlInSurfaceStateForScratchSpaceWhenCallSetL1CachePolicyThenL1CachePolicyL1CacheControlIsSetProperly, IsAtLeastXeHpgCore) { @@ -49,7 +49,7 @@ HWTEST2_F(GfxCoreHelperDg2AndLaterTest, GivenOverrideL1CacheControlInSurfaceStat RENDER_SURFACE_STATE surfaceState = FamilyType::cmdInitRenderSurfaceState; bool useL1Cache = true; helper.setL1CachePolicy(useL1Cache, &surfaceState, defaultHwInfo.get()); - EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_POLICY_UC, surfaceState.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(RENDER_SURFACE_STATE::L1_CACHE_CONTROL_UC, surfaceState.getL1CacheControlCachePolicy()); } HWTEST2_F(GfxCoreHelperDg2AndLaterTest, GivenUseL1CacheAsFalseWhenCallSetL1CachePolicyThenL1CachePolicyL1CacheControlIsNotSet, IsAtLeastXeHpgCore) { @@ -61,7 +61,7 @@ HWTEST2_F(GfxCoreHelperDg2AndLaterTest, GivenUseL1CacheAsFalseWhenCallSetL1Cache RENDER_SURFACE_STATE surfaceState = FamilyType::cmdInitRenderSurfaceState; bool useL1Cache = false; helper.setL1CachePolicy(useL1Cache, &surfaceState, defaultHwInfo.get()); - EXPECT_NE(RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB, surfaceState.getL1CachePolicyL1CacheControl()); + EXPECT_NE(RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB, surfaceState.getL1CacheControlCachePolicy()); } using GfxCoreHelperWithLargeGrf = ::testing::Test; diff --git a/shared/test/unit_test/helpers/state_base_address_tests.cpp b/shared/test/unit_test/helpers/state_base_address_tests.cpp index 9d960d725a..e57e69f5c5 100644 --- a/shared/test/unit_test/helpers/state_base_address_tests.cpp +++ b/shared/test/unit_test/helpers/state_base_address_tests.cpp @@ -291,31 +291,31 @@ HWTEST2_F(SbaTest, givenStateBaseAddressAndDebugFlagSetWhenAppendExtraCacheSetti updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendExtraCacheSettings(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP, stateBaseAddress.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP, stateBaseAddress.getL1CacheControlCachePolicy()); debugManager.flags.ForceStatelessL1CachingPolicy.set(2); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendExtraCacheSettings(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WB, stateBaseAddress.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WB, stateBaseAddress.getL1CacheControlCachePolicy()); debugManager.flags.ForceStatelessL1CachingPolicy.set(3); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendExtraCacheSettings(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WT, stateBaseAddress.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WT, stateBaseAddress.getL1CacheControlCachePolicy()); debugManager.flags.ForceStatelessL1CachingPolicy.set(4); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendExtraCacheSettings(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WS, stateBaseAddress.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WS, stateBaseAddress.getL1CacheControlCachePolicy()); debugManager.flags.ForceAllResourcesUncached.set(true); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendExtraCacheSettings(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_UC, stateBaseAddress.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_UC, stateBaseAddress.getL1CacheControlCachePolicy()); } args.isDebuggerActive = true; { @@ -323,31 +323,31 @@ HWTEST2_F(SbaTest, givenStateBaseAddressAndDebugFlagSetWhenAppendExtraCacheSetti updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendExtraCacheSettings(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP, stateBaseAddress.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP, stateBaseAddress.getL1CacheControlCachePolicy()); debugManager.flags.ForceStatelessL1CachingPolicy.set(2); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendExtraCacheSettings(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WB, stateBaseAddress.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WB, stateBaseAddress.getL1CacheControlCachePolicy()); debugManager.flags.ForceStatelessL1CachingPolicy.set(3); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendExtraCacheSettings(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WT, stateBaseAddress.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WT, stateBaseAddress.getL1CacheControlCachePolicy()); debugManager.flags.ForceStatelessL1CachingPolicy.set(4); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendExtraCacheSettings(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WS, stateBaseAddress.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WS, stateBaseAddress.getL1CacheControlCachePolicy()); debugManager.flags.ForceAllResourcesUncached.set(true); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendExtraCacheSettings(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_UC, stateBaseAddress.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_UC, stateBaseAddress.getL1CacheControlCachePolicy()); } } @@ -356,12 +356,12 @@ HWTEST2_F(SbaTest, givenDebugFlagSetWhenAppendingSbaThenProgramCorrectL1CachePol struct { uint32_t option; - typename FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY cachePolicy; + typename FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL cachePolicy; } testInputs[] = { - {0, FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP}, - {2, FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WB}, - {3, FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WT}, - {4, FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WS}}; + {0, FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP}, + {2, FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WB}, + {3, FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WT}, + {4, FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WS}}; StateBaseAddressHelperArgs args = createSbaHelperArgs(&sbaCmd, pDevice->getRootDeviceEnvironment().getGmmHelper(), &ssh, nullptr, nullptr); args.setGeneralStateBaseAddress = true; @@ -375,13 +375,13 @@ HWTEST2_F(SbaTest, givenDebugFlagSetWhenAppendingSbaThenProgramCorrectL1CachePol StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(input.cachePolicy, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(input.cachePolicy, sbaCmd.getL1CacheControlCachePolicy()); debugManager.flags.ForceAllResourcesUncached.set(true); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_UC, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_UC, sbaCmd.getL1CacheControlCachePolicy()); } } @@ -408,18 +408,18 @@ HWTEST2_F(SbaTest, givenDebugFlagSetWhenAppendingRssThenProgramCorrectL1CachePol struct { uint32_t option; - typename FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY cachePolicy; + typename FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL cachePolicy; } testInputs[] = { - {0, FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WBP}, - {2, FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB}, - {3, FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WT}, - {4, FamilyType::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WS}}; + {0, FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WBP}, + {2, FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WB}, + {3, FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WT}, + {4, FamilyType::RENDER_SURFACE_STATE::L1_CACHE_CONTROL_WS}}; for (const auto &input : testInputs) { DebugManagerStateRestore restore; debugManager.flags.OverrideL1CachePolicyInSurfaceStateAndStateless.set(input.option); EncodeSurfaceState::encodeBuffer(args); - EXPECT_EQ(input.cachePolicy, rssCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(input.cachePolicy, rssCmd.getL1CacheControlCachePolicy()); } memoryManager->freeGraphicsMemory(allocation); } diff --git a/shared/test/unit_test/helpers/test_blit_commands_helper_xehp_and_later.cpp b/shared/test/unit_test/helpers/test_blit_commands_helper_xehp_and_later.cpp index a08abbda0b..48c5b827df 100644 --- a/shared/test/unit_test/helpers/test_blit_commands_helper_xehp_and_later.cpp +++ b/shared/test/unit_test/helpers/test_blit_commands_helper_xehp_and_later.cpp @@ -301,7 +301,7 @@ struct MyMockResourecInfo : public GmmResourceInfo { GMM_RESOURCE_FLAG *getResourceFlags() override { return &flags; } - uint32_t getMipTailStartLodSurfaceState() override { + uint32_t getMipTailStartLODSurfaceState() override { return 0; } size_t pitch = 0; diff --git a/shared/test/unit_test/image/image_surface_state_tests.cpp b/shared/test/unit_test/image/image_surface_state_tests.cpp index 60c1bebab2..b1271c645c 100644 --- a/shared/test/unit_test/image/image_surface_state_tests.cpp +++ b/shared/test/unit_test/image/image_surface_state_tests.cpp @@ -48,7 +48,7 @@ HWTEST2_F(ImageSurfaceStateTests, givenImageInfoWhenSetImageSurfaceStateThenProp EXPECT_EQ(castSurfaceState->getRenderTargetViewExtent(), 1u); EXPECT_EQ(castSurfaceState->getMinimumArrayElement(), cubeFaceIndex); - EXPECT_EQ(castSurfaceState->getSurfaceQpitch(), imageInfo.qPitch >> RENDER_SURFACE_STATE::tagSURFACEQPITCH::SURFACEQPITCH_BIT_SHIFT); + EXPECT_EQ(castSurfaceState->getSurfaceQPitch(), imageInfo.qPitch >> RENDER_SURFACE_STATE::tagSURFACEQPITCH::SURFACEQPITCH_BIT_SHIFT); EXPECT_EQ(castSurfaceState->getSurfaceArray(), true); EXPECT_EQ(castSurfaceState->getSurfaceHorizontalAlignment(), static_cast(mockGmm->gmmResourceInfo->getHAlignSurfaceState())); EXPECT_EQ(castSurfaceState->getSurfaceVerticalAlignment(), static_cast(mockGmm->gmmResourceInfo->getVAlignSurfaceState())); @@ -87,7 +87,7 @@ HWTEST2_F(ImageSurfaceStateTests, givenImageInfoWhenSetImageSurfaceStateThenProp EXPECT_EQ(castSurfaceState->getAuxiliarySurfaceMode(), AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_NONE); EXPECT_EQ(castSurfaceState->getAuxiliarySurfacePitch(), 1u); - EXPECT_EQ(castSurfaceState->getAuxiliarySurfaceQpitch(), 0u); + EXPECT_EQ(castSurfaceState->getAuxiliarySurfaceQPitch(), 0u); EXPECT_EQ(castSurfaceState->getAuxiliarySurfaceBaseAddress(), 0u); surfaceState = std::make_unique(size); diff --git a/shared/test/unit_test/os_interface/product_helper_tests.cpp b/shared/test/unit_test/os_interface/product_helper_tests.cpp index e649fa5f0e..6d702b2566 100644 --- a/shared/test/unit_test/os_interface/product_helper_tests.cpp +++ b/shared/test/unit_test/os_interface/product_helper_tests.cpp @@ -695,29 +695,29 @@ HWTEST2_F(ProductHelperTest, givenProductHelperAndDebugFlagWhenGetL1CachePolicyT DebugManagerStateRestore restorer; debugManager.flags.OverrideL1CachePolicyInSurfaceStateAndStateless.set(0); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP, productHelper->getL1CachePolicy(false)); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP, productHelper->getL1CachePolicy(true)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP, productHelper->getL1CachePolicy(false)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP, productHelper->getL1CachePolicy(true)); debugManager.flags.OverrideL1CachePolicyInSurfaceStateAndStateless.set(2); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WB, productHelper->getL1CachePolicy(false)); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WB, productHelper->getL1CachePolicy(true)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WB, productHelper->getL1CachePolicy(false)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WB, productHelper->getL1CachePolicy(true)); debugManager.flags.OverrideL1CachePolicyInSurfaceStateAndStateless.set(3); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WT, productHelper->getL1CachePolicy(false)); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WT, productHelper->getL1CachePolicy(true)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WT, productHelper->getL1CachePolicy(false)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WT, productHelper->getL1CachePolicy(true)); debugManager.flags.OverrideL1CachePolicyInSurfaceStateAndStateless.set(4); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WS, productHelper->getL1CachePolicy(false)); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WS, productHelper->getL1CachePolicy(true)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WS, productHelper->getL1CachePolicy(false)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WS, productHelper->getL1CachePolicy(true)); debugManager.flags.ForceAllResourcesUncached.set(true); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_UC, productHelper->getL1CachePolicy(false)); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_UC, productHelper->getL1CachePolicy(true)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_UC, productHelper->getL1CachePolicy(false)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_UC, productHelper->getL1CachePolicy(true)); } HWTEST2_F(ProductHelperTest, givenProductHelperWhenGetL1CachePolicyThenReturnWriteByPass, IsAtLeastXeHpgCore) { - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP, productHelper->getL1CachePolicy(false)); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP, productHelper->getL1CachePolicy(true)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP, productHelper->getL1CachePolicy(false)); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP, productHelper->getL1CachePolicy(true)); } HWTEST2_F(ProductHelperTest, givenPlatformWithUnsupportedL1CachePoliciesWhenGetL1CachePolicyThenReturnZero, IsAtMostXeHpCore) { diff --git a/shared/test/unit_test/xe2_hpg_core/image_surface_state_tests_xe2_hpg_core.cpp b/shared/test/unit_test/xe2_hpg_core/image_surface_state_tests_xe2_hpg_core.cpp index 5236346525..18230a474f 100644 --- a/shared/test/unit_test/xe2_hpg_core/image_surface_state_tests_xe2_hpg_core.cpp +++ b/shared/test/unit_test/xe2_hpg_core/image_surface_state_tests_xe2_hpg_core.cpp @@ -21,13 +21,13 @@ XE2_HPG_CORETEST_F(ImageSurfaceStateTestsXe2HpgCore, givenGmmWithMediaCompressed auto surfaceState = std::make_unique(size); auto castSurfaceState = reinterpret_cast(surfaceState.get()); - setMipTailStartLod(castSurfaceState, nullptr); + setMipTailStartLOD(castSurfaceState, nullptr); - EXPECT_EQ(castSurfaceState->getMipTailStartLod(), 0u); + EXPECT_EQ(castSurfaceState->getMipTailStartLOD(), 0u); - setMipTailStartLod(castSurfaceState, mockGmm.get()); + setMipTailStartLOD(castSurfaceState, mockGmm.get()); - EXPECT_EQ(castSurfaceState->getMipTailStartLod(), mockGmm->gmmResourceInfo->getMipTailStartLodSurfaceState()); + EXPECT_EQ(castSurfaceState->getMipTailStartLOD(), mockGmm->gmmResourceInfo->getMipTailStartLODSurfaceState()); } XE2_HPG_CORETEST_F(ImageSurfaceStateTestsXe2HpgCore, givenNotMediaCompressedImageWhenAppendingSurfaceStateParamsForCompressionThenCallAppriopriateFunction) { diff --git a/shared/test/unit_test/xe2_hpg_core/test_encode_xe2_hpg_core.cpp b/shared/test/unit_test/xe2_hpg_core/test_encode_xe2_hpg_core.cpp index 1793c21155..7a101ff006 100644 --- a/shared/test/unit_test/xe2_hpg_core/test_encode_xe2_hpg_core.cpp +++ b/shared/test/unit_test/xe2_hpg_core/test_encode_xe2_hpg_core.cpp @@ -654,7 +654,7 @@ XE2_HPG_CORETEST_F(Xe2HpgSbaTest, givenSpecificProductFamilyWhenAppendingSbaThen StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP, sbaCmd.getL1CacheControlCachePolicy()); } XE2_HPG_CORETEST_F(Xe2HpgSbaTest, givenL1CachingOverrideWhenStateBaseAddressIsProgrammedThenItMatchesTheOverrideValue) { @@ -669,19 +669,19 @@ XE2_HPG_CORETEST_F(Xe2HpgSbaTest, givenL1CachingOverrideWhenStateBaseAddressIsPr updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(0u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(0u, sbaCmd.getL1CacheControlCachePolicy()); debugManager.flags.ForceStatelessL1CachingPolicy.set(2u); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(2u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(2u, sbaCmd.getL1CacheControlCachePolicy()); debugManager.flags.ForceAllResourcesUncached.set(true); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(1u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(1u, sbaCmd.getL1CacheControlCachePolicy()); } diff --git a/shared/test/unit_test/xe_hpc_core/image_surface_state_tests_xe_hpc_core.cpp b/shared/test/unit_test/xe_hpc_core/image_surface_state_tests_xe_hpc_core.cpp index 85486063dc..cebfb98c7f 100644 --- a/shared/test/unit_test/xe_hpc_core/image_surface_state_tests_xe_hpc_core.cpp +++ b/shared/test/unit_test/xe_hpc_core/image_surface_state_tests_xe_hpc_core.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021-2023 Intel Corporation + * Copyright (C) 2021-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -47,13 +47,13 @@ XE_HPC_CORETEST_F(ImageSurfaceStateTestsXeHpcCore, givenGmmWithMediaCompressedWh auto surfaceState = std::make_unique(size); auto castSurfaceState = reinterpret_cast(surfaceState.get()); - setMipTailStartLod(castSurfaceState, nullptr); + setMipTailStartLOD(castSurfaceState, nullptr); - EXPECT_EQ(castSurfaceState->getMipTailStartLod(), 0u); + EXPECT_EQ(castSurfaceState->getMipTailStartLOD(), 0u); - setMipTailStartLod(castSurfaceState, mockGmm.get()); + setMipTailStartLOD(castSurfaceState, mockGmm.get()); - EXPECT_EQ(castSurfaceState->getMipTailStartLod(), mockGmm->gmmResourceInfo->getMipTailStartLodSurfaceState()); + EXPECT_EQ(castSurfaceState->getMipTailStartLOD(), mockGmm->gmmResourceInfo->getMipTailStartLODSurfaceState()); } XE_HPC_CORETEST_F(ImageSurfaceStateTestsXeHpcCore, givenSurfaceStateAndNullptrReleaseHelperWhenAuxParamsForMCSCCSAreSetThenCorrectAuxModeIsSet) { diff --git a/shared/test/unit_test/xe_hpc_core/test_encode_xe_hpc_core.cpp b/shared/test/unit_test/xe_hpc_core/test_encode_xe_hpc_core.cpp index 98b7fa8f81..4bd0e7cb07 100644 --- a/shared/test/unit_test/xe_hpc_core/test_encode_xe_hpc_core.cpp +++ b/shared/test/unit_test/xe_hpc_core/test_encode_xe_hpc_core.cpp @@ -498,7 +498,7 @@ XE_HPC_CORETEST_F(XeHpcSbaTest, givenSpecificProductFamilyWhenAppendingSbaThenPr StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP, sbaCmd.getL1CacheControlCachePolicy()); } XE_HPC_CORETEST_F(XeHpcSbaTest, givenL1CachingOverrideWhenStateBaseAddressIsProgrammedThenItMatchesTheOverrideValue) { @@ -513,19 +513,19 @@ XE_HPC_CORETEST_F(XeHpcSbaTest, givenL1CachingOverrideWhenStateBaseAddressIsProg StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(0u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(0u, sbaCmd.getL1CacheControlCachePolicy()); debugManager.flags.ForceStatelessL1CachingPolicy.set(2u); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(2u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(2u, sbaCmd.getL1CacheControlCachePolicy()); debugManager.flags.ForceAllResourcesUncached.set(true); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(1u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(1u, sbaCmd.getL1CacheControlCachePolicy()); } diff --git a/shared/test/unit_test/xe_hpg_core/dg2/cache_policy_tests_dg2.cpp b/shared/test/unit_test/xe_hpg_core/dg2/cache_policy_tests_dg2.cpp index 4b79651634..aa0a2c11f3 100644 --- a/shared/test/unit_test/xe_hpg_core/dg2/cache_policy_tests_dg2.cpp +++ b/shared/test/unit_test/xe_hpg_core/dg2/cache_policy_tests_dg2.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2022-2023 Intel Corporation + * Copyright (C) 2022-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -17,8 +17,8 @@ using namespace NEO; DG2TEST_F(ProductHelperTest, givenDG2WhenGetL1CachePolicyThenReturnWbPolicyUnlessDebuggerIsActive) { using GfxFamily = typename HwMapper::GfxFamily; - EXPECT_EQ(L1CachePolicyHelper::getL1CachePolicy(false), GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WB); - EXPECT_EQ(L1CachePolicyHelper::getL1CachePolicy(true), GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP); + EXPECT_EQ(L1CachePolicyHelper::getL1CachePolicy(false), GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WB); + EXPECT_EQ(L1CachePolicyHelper::getL1CachePolicy(true), GfxFamily::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP); } DG2TEST_F(ProductHelperTest, givenDG2WhenGetCachingPolicyOptionsThenReturnCorrectValue) { diff --git a/shared/test/unit_test/xe_hpg_core/dg2/test_encode_dg2.cpp b/shared/test/unit_test/xe_hpg_core/dg2/test_encode_dg2.cpp index e288d6bf9b..5d64befe97 100644 --- a/shared/test/unit_test/xe_hpg_core/dg2/test_encode_dg2.cpp +++ b/shared/test/unit_test/xe_hpg_core/dg2/test_encode_dg2.cpp @@ -76,11 +76,11 @@ DG2TEST_F(Dg2SbaTest, givenSpecificProductFamilyWhenAppendingSbaThenProgramCorre args.setGeneralStateBaseAddress = true; StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WB, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WB, sbaCmd.getL1CacheControlCachePolicy()); args.isDebuggerActive = true; StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP, sbaCmd.getL1CacheControlCachePolicy()); } DG2TEST_F(Dg2SbaTest, givenL1CachingOverrideWhenStateBaseAddressIsProgrammedThenItMatchesTheOverrideValue) { @@ -94,19 +94,19 @@ DG2TEST_F(Dg2SbaTest, givenL1CachingOverrideWhenStateBaseAddressIsProgrammedThen StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(0u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(0u, sbaCmd.getL1CacheControlCachePolicy()); debugManager.flags.ForceStatelessL1CachingPolicy.set(2u); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(2u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(2u, sbaCmd.getL1CacheControlCachePolicy()); debugManager.flags.ForceAllResourcesUncached.set(true); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(1u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(1u, sbaCmd.getL1CacheControlCachePolicy()); } diff --git a/shared/test/unit_test/xe_hpg_core/hw_cmds_xe_hpg_core_tests.cpp b/shared/test/unit_test/xe_hpg_core/hw_cmds_xe_hpg_core_tests.cpp index c492100550..827926e5a9 100644 --- a/shared/test/unit_test/xe_hpg_core/hw_cmds_xe_hpg_core_tests.cpp +++ b/shared/test/unit_test/xe_hpg_core/hw_cmds_xe_hpg_core_tests.cpp @@ -110,7 +110,7 @@ XE_HPG_CORETEST_F(XeHpgSbaTest, givenSpecificProductFamilyWhenAppendingSbaThenPr StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(FamilyType::STATE_BASE_ADDRESS::L1_CACHE_CONTROL_WBP, sbaCmd.getL1CacheControlCachePolicy()); } XE_HPG_CORETEST_F(XeHpgSbaTest, givenL1CachingOverrideWhenStateBaseAddressIsProgrammedThenItMatchesTheOverrideValue) { @@ -125,19 +125,19 @@ XE_HPG_CORETEST_F(XeHpgSbaTest, givenL1CachingOverrideWhenStateBaseAddressIsProg StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(0u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(0u, sbaCmd.getL1CacheControlCachePolicy()); debugManager.flags.ForceStatelessL1CachingPolicy.set(2u); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(2u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(2u, sbaCmd.getL1CacheControlCachePolicy()); debugManager.flags.ForceAllResourcesUncached.set(true); updateSbaHelperArgsL1CachePolicy(args, productHelper); StateBaseAddressHelper::appendStateBaseAddressParameters(args); - EXPECT_EQ(1u, sbaCmd.getL1CachePolicyL1CacheControl()); + EXPECT_EQ(1u, sbaCmd.getL1CacheControlCachePolicy()); } diff --git a/shared/test/unit_test/xe_hpg_core/image_surface_state_tests_xe_hpg_core.cpp b/shared/test/unit_test/xe_hpg_core/image_surface_state_tests_xe_hpg_core.cpp index 947843498e..e841d7e2d9 100644 --- a/shared/test/unit_test/xe_hpg_core/image_surface_state_tests_xe_hpg_core.cpp +++ b/shared/test/unit_test/xe_hpg_core/image_surface_state_tests_xe_hpg_core.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021-2023 Intel Corporation + * Copyright (C) 2021-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -47,13 +47,13 @@ XE_HPG_CORETEST_F(ImageSurfaceStateTestsXeHpgCore, givenGmmWithMediaCompressedWh auto surfaceState = std::make_unique(size); auto castSurfaceState = reinterpret_cast(surfaceState.get()); - setMipTailStartLod(castSurfaceState, nullptr); + setMipTailStartLOD(castSurfaceState, nullptr); - EXPECT_EQ(castSurfaceState->getMipTailStartLod(), 0u); + EXPECT_EQ(castSurfaceState->getMipTailStartLOD(), 0u); - setMipTailStartLod(castSurfaceState, mockGmm.get()); + setMipTailStartLOD(castSurfaceState, mockGmm.get()); - EXPECT_EQ(castSurfaceState->getMipTailStartLod(), mockGmm->gmmResourceInfo->getMipTailStartLodSurfaceState()); + EXPECT_EQ(castSurfaceState->getMipTailStartLOD(), mockGmm->gmmResourceInfo->getMipTailStartLODSurfaceState()); } XE_HPG_CORETEST_F(ImageSurfaceStateTestsXeHpgCore, givenSurfaceStateAndNullptrReleaseHelperWhenAuxParamsForMCSCCSAreSetThenCorrectAuxModeIsSet) {