mirror of
https://github.com/intel/compute-runtime.git
synced 2026-01-03 06:49:52 +08:00
Correct cross thread data GPU address in indirect dispatch programming
Related-To: NEO-5081 Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This commit is contained in:
Mateusz Jablonski
committed by
Compute-Runtime-Automation
Compute-Runtime-Automation
parent
5e201f40be
commit
b891ec2588
@@ -48,8 +48,18 @@ HWTEST_F(CommandListDualStorage, givenIndirectDispatchWithSharedDualStorageMemor
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using MI_LOAD_REGISTER_IMM = typename FamilyType::MI_LOAD_REGISTER_IMM;
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Mock<::L0::Kernel> kernel;
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kernel.descriptor.payloadMappings.dispatchTraits.numWorkGroups[0] = 2;
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kernel.descriptor.payloadMappings.dispatchTraits.globalWorkSize[0] = 2;
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uint32_t globalWorkSizeXOffset = 0x20u;
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uint32_t globalWorkSizeYOffset = 0x24u;
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uint32_t globalWorkSizeZOffset = 0x28u;
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uint32_t numWorkGroupXOffset = 0x30u;
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uint32_t numWorkGroupYOffset = 0x34u;
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uint32_t numWorkGroupZOffset = 0x38u;
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kernel.descriptor.payloadMappings.dispatchTraits.globalWorkSize[0] = globalWorkSizeXOffset;
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kernel.descriptor.payloadMappings.dispatchTraits.globalWorkSize[1] = globalWorkSizeYOffset;
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kernel.descriptor.payloadMappings.dispatchTraits.globalWorkSize[2] = globalWorkSizeZOffset;
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kernel.descriptor.payloadMappings.dispatchTraits.numWorkGroups[0] = numWorkGroupXOffset;
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kernel.descriptor.payloadMappings.dispatchTraits.numWorkGroups[1] = numWorkGroupYOffset;
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kernel.descriptor.payloadMappings.dispatchTraits.numWorkGroups[2] = numWorkGroupZOffset;
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ze_result_t returnValue;
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std::unique_ptr<L0::CommandList> commandList(L0::CommandList::create(productFamily, device, NEO::EngineGroupType::RenderCompute, 0u, returnValue));
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@@ -123,6 +133,36 @@ HWTEST_F(CommandListDualStorage, givenIndirectDispatchWithSharedDualStorageMemor
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} while (itor != cmdList.end() && cmd2->getRegisterAddress() != GPUGPU_DISPATCHDIMX);
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EXPECT_NE(cmdList.end(), itor);
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auto groupCountStoreRegisterMemCmd = FamilyType::cmdInitStoreRegisterMem;
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groupCountStoreRegisterMemCmd.setRegisterAddress(GPUGPU_DISPATCHDIMX);
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groupCountStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + numWorkGroupXOffset);
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EXPECT_EQ(cmd2->getRegisterAddress(), groupCountStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), groupCountStoreRegisterMemCmd.getMemoryAddress());
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd2 = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
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groupCountStoreRegisterMemCmd.setRegisterAddress(GPUGPU_DISPATCHDIMY);
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groupCountStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + numWorkGroupYOffset);
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EXPECT_EQ(cmd2->getRegisterAddress(), groupCountStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), groupCountStoreRegisterMemCmd.getMemoryAddress());
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd2 = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
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groupCountStoreRegisterMemCmd.setRegisterAddress(GPUGPU_DISPATCHDIMZ);
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groupCountStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + numWorkGroupZOffset);
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EXPECT_EQ(cmd2->getRegisterAddress(), groupCountStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), groupCountStoreRegisterMemCmd.getMemoryAddress());
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auto workSizeStoreRegisterMemCmd = FamilyType::cmdInitStoreRegisterMem;
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workSizeStoreRegisterMemCmd.setRegisterAddress(CS_GPR_R1);
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// Find workgroup size cmds
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itor = find<MI_LOAD_REGISTER_REG *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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@@ -131,7 +171,212 @@ HWTEST_F(CommandListDualStorage, givenIndirectDispatchWithSharedDualStorageMemor
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd2 = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
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EXPECT_EQ(CS_GPR_R1, cmd2->getRegisterAddress());
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workSizeStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + globalWorkSizeXOffset);
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EXPECT_EQ(cmd2->getRegisterAddress(), workSizeStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), workSizeStoreRegisterMemCmd.getMemoryAddress());
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itor = find<MI_LOAD_REGISTER_REG *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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itor = find<MI_LOAD_REGISTER_IMM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd2 = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
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workSizeStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + globalWorkSizeYOffset);
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EXPECT_EQ(cmd2->getRegisterAddress(), workSizeStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), workSizeStoreRegisterMemCmd.getMemoryAddress());
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EXPECT_EQ(cmd2->getRegisterAddress(), workSizeStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), workSizeStoreRegisterMemCmd.getMemoryAddress());
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itor = find<MI_LOAD_REGISTER_REG *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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itor = find<MI_LOAD_REGISTER_IMM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd2 = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
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workSizeStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + globalWorkSizeZOffset);
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EXPECT_EQ(cmd2->getRegisterAddress(), workSizeStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), workSizeStoreRegisterMemCmd.getMemoryAddress());
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context->freeMem(alloc);
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}
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HWCMDTEST_F(IGFX_XE_HP_CORE, CommandListDualStorage, givenIndirectDispatchWithSharedDualStorageMemoryAndInlineDataWhenAppendingThenWorkGroupCountAndGlobalWorkSizeIsSetInCrossThreadData) {
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using MI_STORE_REGISTER_MEM = typename FamilyType::MI_STORE_REGISTER_MEM;
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using MI_LOAD_REGISTER_MEM = typename FamilyType::MI_LOAD_REGISTER_MEM;
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using MI_LOAD_REGISTER_REG = typename FamilyType::MI_LOAD_REGISTER_REG;
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using MI_LOAD_REGISTER_IMM = typename FamilyType::MI_LOAD_REGISTER_IMM;
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using INLINE_DATA = typename FamilyType::INLINE_DATA;
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Mock<::L0::Kernel> kernel;
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kernel.crossThreadDataSize = 0x60u;
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kernel.descriptor.kernelAttributes.flags.passInlineData = true;
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uint32_t globalWorkSizeXOffset = 0x40u;
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uint32_t globalWorkSizeYOffset = 0x44u;
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uint32_t globalWorkSizeZOffset = 0x48u;
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uint32_t numWorkGroupXOffset = 0x30u;
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uint32_t numWorkGroupYOffset = 0x34u;
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uint32_t numWorkGroupZOffset = 0x38u;
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kernel.descriptor.payloadMappings.dispatchTraits.globalWorkSize[0] = globalWorkSizeXOffset;
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kernel.descriptor.payloadMappings.dispatchTraits.globalWorkSize[1] = globalWorkSizeYOffset;
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kernel.descriptor.payloadMappings.dispatchTraits.globalWorkSize[2] = globalWorkSizeZOffset;
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kernel.descriptor.payloadMappings.dispatchTraits.numWorkGroups[0] = numWorkGroupXOffset;
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kernel.descriptor.payloadMappings.dispatchTraits.numWorkGroups[1] = numWorkGroupYOffset;
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kernel.descriptor.payloadMappings.dispatchTraits.numWorkGroups[2] = numWorkGroupZOffset;
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ze_result_t returnValue;
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std::unique_ptr<L0::CommandList> commandList(L0::CommandList::create(productFamily, device, NEO::EngineGroupType::RenderCompute, 0u, returnValue));
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void *alloc = nullptr;
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ze_device_mem_alloc_desc_t deviceDesc = {};
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ze_host_mem_alloc_desc_t hostDesc = {};
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auto result = context->allocSharedMem(device->toHandle(), &deviceDesc, &hostDesc, 16384u, 4096u, &alloc);
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ASSERT_EQ(ZE_RESULT_SUCCESS, result);
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ze_group_count_t *pThreadGroupDimensions = static_cast<ze_group_count_t *>(ptrOffset(alloc, sizeof(ze_group_count_t)));
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pThreadGroupDimensions->groupCountX = 3;
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pThreadGroupDimensions->groupCountY = 4;
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pThreadGroupDimensions->groupCountZ = 5;
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result = commandList->appendLaunchKernelIndirect(kernel.toHandle(),
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pThreadGroupDimensions,
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nullptr, 0, nullptr);
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EXPECT_EQ(ZE_RESULT_SUCCESS, result);
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auto allocData = device->getDriverHandle()->getSvmAllocsManager()->getSVMAlloc(pThreadGroupDimensions);
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ASSERT_NE(nullptr, allocData->cpuAllocation);
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auto gpuAllocation = allocData->gpuAllocations.getGraphicsAllocation(device->getNEODevice()->getRootDeviceIndex());
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ASSERT_NE(nullptr, gpuAllocation);
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GenCmdList cmdList;
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ASSERT_TRUE(FamilyType::PARSE::parseCommandBuffer(
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cmdList, ptrOffset(commandList->commandContainer.getCommandStream()->getCpuBase(), 0), commandList->commandContainer.getCommandStream()->getUsed()));
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uint32_t regAddress = 0;
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uint64_t gpuAddress = 0;
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auto expectedXAddress = reinterpret_cast<uint64_t>(ptrOffset(pThreadGroupDimensions, offsetof(ze_group_count_t, groupCountX)));
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auto expectedYAddress = reinterpret_cast<uint64_t>(ptrOffset(pThreadGroupDimensions, offsetof(ze_group_count_t, groupCountY)));
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auto expectedZAddress = reinterpret_cast<uint64_t>(ptrOffset(pThreadGroupDimensions, offsetof(ze_group_count_t, groupCountZ)));
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auto itor = find<MI_LOAD_REGISTER_MEM *>(cmdList.begin(), cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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auto cmd = genCmdCast<MI_LOAD_REGISTER_MEM *>(*itor);
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regAddress = cmd->getRegisterAddress();
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gpuAddress = cmd->getMemoryAddress();
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EXPECT_EQ(GPUGPU_DISPATCHDIMX, regAddress);
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EXPECT_EQ(expectedXAddress, gpuAddress);
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itor = find<MI_LOAD_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd = genCmdCast<MI_LOAD_REGISTER_MEM *>(*itor);
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regAddress = cmd->getRegisterAddress();
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gpuAddress = cmd->getMemoryAddress();
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EXPECT_EQ(GPUGPU_DISPATCHDIMY, regAddress);
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EXPECT_EQ(expectedYAddress, gpuAddress);
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itor = find<MI_LOAD_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd = genCmdCast<MI_LOAD_REGISTER_MEM *>(*itor);
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regAddress = cmd->getRegisterAddress();
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gpuAddress = cmd->getMemoryAddress();
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EXPECT_EQ(GPUGPU_DISPATCHDIMZ, regAddress);
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EXPECT_EQ(expectedZAddress, gpuAddress);
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MI_STORE_REGISTER_MEM *cmd2 = nullptr;
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// Find group count cmds
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do {
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, cmdList.end());
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cmd2 = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
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} while (itor != cmdList.end() && cmd2->getRegisterAddress() != GPUGPU_DISPATCHDIMX);
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EXPECT_NE(cmdList.end(), itor);
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auto groupCountStoreRegisterMemCmd = FamilyType::cmdInitStoreRegisterMem;
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groupCountStoreRegisterMemCmd.setRegisterAddress(GPUGPU_DISPATCHDIMX);
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groupCountStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + numWorkGroupXOffset - sizeof(INLINE_DATA));
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EXPECT_EQ(cmd2->getRegisterAddress(), groupCountStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), groupCountStoreRegisterMemCmd.getMemoryAddress());
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd2 = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
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groupCountStoreRegisterMemCmd.setRegisterAddress(GPUGPU_DISPATCHDIMY);
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groupCountStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + numWorkGroupYOffset - sizeof(INLINE_DATA));
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EXPECT_EQ(cmd2->getRegisterAddress(), groupCountStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), groupCountStoreRegisterMemCmd.getMemoryAddress());
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd2 = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
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groupCountStoreRegisterMemCmd.setRegisterAddress(GPUGPU_DISPATCHDIMZ);
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groupCountStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + numWorkGroupZOffset - sizeof(INLINE_DATA));
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EXPECT_EQ(cmd2->getRegisterAddress(), groupCountStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), groupCountStoreRegisterMemCmd.getMemoryAddress());
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auto workSizeStoreRegisterMemCmd = FamilyType::cmdInitStoreRegisterMem;
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workSizeStoreRegisterMemCmd.setRegisterAddress(CS_GPR_R1);
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// Find workgroup size cmds
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itor = find<MI_LOAD_REGISTER_REG *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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itor = find<MI_LOAD_REGISTER_IMM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd2 = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
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workSizeStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + globalWorkSizeXOffset - sizeof(INLINE_DATA));
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EXPECT_EQ(cmd2->getRegisterAddress(), workSizeStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), workSizeStoreRegisterMemCmd.getMemoryAddress());
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itor = find<MI_LOAD_REGISTER_REG *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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itor = find<MI_LOAD_REGISTER_IMM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd2 = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
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workSizeStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + globalWorkSizeYOffset - sizeof(INLINE_DATA));
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EXPECT_EQ(cmd2->getRegisterAddress(), workSizeStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), workSizeStoreRegisterMemCmd.getMemoryAddress());
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EXPECT_EQ(cmd2->getRegisterAddress(), workSizeStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), workSizeStoreRegisterMemCmd.getMemoryAddress());
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itor = find<MI_LOAD_REGISTER_REG *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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itor = find<MI_LOAD_REGISTER_IMM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, cmdList.end());
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EXPECT_NE(cmdList.end(), itor);
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cmd2 = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
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workSizeStoreRegisterMemCmd.setMemoryAddress(commandList->commandContainer.getIndirectHeap(HeapType::INDIRECT_OBJECT)->getGraphicsAllocation()->getGpuAddress() + globalWorkSizeZOffset - sizeof(INLINE_DATA));
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EXPECT_EQ(cmd2->getRegisterAddress(), workSizeStoreRegisterMemCmd.getRegisterAddress());
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EXPECT_EQ(cmd2->getMemoryAddress(), workSizeStoreRegisterMemCmd.getMemoryAddress());
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context->freeMem(alloc);
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}
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