feature: add support for cache reservation

Resolves: NEO-7849

Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>

level_zero/core/source/cache/linux/CMakeLists.txt

@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2021-2023 Intel Corporation
+# Copyright (C) 2021-2024 Intel Corporation
 #
 # SPDX-License-Identifier: MIT
 #
@@ -8,7 +8,19 @@ if(UNIX)
   target_sources(${L0_STATIC_LIB_NAME}
                  PRIVATE
                  ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
-                 ${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}cache_reservation_impl.cpp
-                 ${CMAKE_CURRENT_SOURCE_DIR}${BRANCH_DIR_SUFFIX}cache_reservation_impl.h
   )
+
+  if(NEO_ENABLE_i915_PRELIM_DETECTION)
+    target_sources(${L0_STATIC_LIB_NAME}
+                   PRIVATE
+                   ${CMAKE_CURRENT_SOURCE_DIR}/cache_reservation_impl_prelim.cpp
+                   ${CMAKE_CURRENT_SOURCE_DIR}/cache_reservation_impl_prelim.h
+    )
+  else()
+    target_sources(${L0_STATIC_LIB_NAME}
+                   PRIVATE
+                   ${CMAKE_CURRENT_SOURCE_DIR}/cache_reservation_impl_upstream.cpp
+                   ${CMAKE_CURRENT_SOURCE_DIR}/cache_reservation_impl_upstream.h
+    )
+  endif()
 endif()

level_zero/core/source/cache/linux/cache_reservation_impl_prelim.cpp

@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2021-2024 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/cache/linux/cache_reservation_impl_prelim.h"
+
+#include "shared/source/memory_manager/unified_memory_manager.h"
+#include "shared/source/os_interface/linux/cache_info.h"
+#include "shared/source/os_interface/linux/drm_allocation.h"
+#include "shared/source/os_interface/linux/drm_neo.h"
+
+#include "level_zero/core/source/device/device.h"
+#include "level_zero/core/source/driver/driver_handle.h"
+
+namespace L0 {
+
+std::unique_ptr<CacheReservation> CacheReservation::create(Device &device) {
+    return std::make_unique<CacheReservationImpl>(device);
+}
+
+bool CacheReservationImpl::reserveCache(size_t cacheLevel, size_t cacheReservationSize) {
+    auto drm = device.getOsInterface().getDriverModel()->as<NEO::Drm>();
+
+    auto cacheInfo = drm->getCacheInfo();
+
+    if (cacheReservationSize == 0) {
+        cacheInfo->freeCacheRegion(this->reservedCacheRegion);
+        this->reservedCacheRegion = NEO::CacheRegion::none;
+        this->reservedCacheSize = 0;
+        return true;
+    }
+
+    auto cacheRegion = cacheInfo->reserveCacheRegion(cacheReservationSize);
+    if (cacheRegion == NEO::CacheRegion::none) {
+        return false;
+    }
+
+    this->reservedCacheRegion = cacheRegion;
+    this->reservedCacheSize = cacheReservationSize;
+
+    return true;
+}
+
+bool CacheReservationImpl::setCacheAdvice(void *ptr, [[maybe_unused]] size_t regionSize, ze_cache_ext_region_t cacheRegion) {
+    auto cacheRegionIdx = NEO::CacheRegion::defaultRegion;
+    size_t cacheRegionSize = 0;
+
+    if (cacheRegion == ze_cache_ext_region_t::ZE_CACHE_EXT_REGION_ZE_CACHE_RESERVE_REGION) {
+        cacheRegionIdx = this->reservedCacheRegion;
+        cacheRegionSize = this->reservedCacheSize;
+    }
+
+    auto allocData = device.getDriverHandle()->getSvmAllocsManager()->getSVMAlloc(ptr);
+    if (allocData == nullptr) {
+        return false;
+    }
+
+    auto drm = device.getOsInterface().getDriverModel()->as<NEO::Drm>();
+
+    auto gpuAllocation = allocData->gpuAllocations.getGraphicsAllocation(device.getRootDeviceIndex());
+    auto drmAllocation = static_cast<NEO::DrmAllocation *>(gpuAllocation);
+
+    return drmAllocation->setCacheAdvice(drm, cacheRegionSize, cacheRegionIdx, !drmAllocation->isAllocatedInLocalMemoryPool());
+}
+
+size_t CacheReservationImpl::getMaxCacheReservationSize() {
+    auto drm = device.getOsInterface().getDriverModel()->as<NEO::Drm>();
+
+    auto cacheInfo = drm->getCacheInfo();
+    return cacheInfo->getMaxReservationCacheSize();
+}
+
+} // namespace L0

level_zero/core/source/cache/linux/cache_reservation_impl_prelim.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2021-2024 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#pragma once
+#include "shared/source/helpers/common_types.h"
+#include "shared/source/os_interface/linux/cache_info.h"
+
+#include "level_zero/core/source/cache/cache_reservation.h"
+
+namespace L0 {
+
+class CacheReservationImpl : public CacheReservation {
+  public:
+    ~CacheReservationImpl() override = default;
+    CacheReservationImpl(Device &device) : device(device){};
+
+    bool reserveCache(size_t cacheLevel, size_t cacheReservationSize) override;
+    bool setCacheAdvice(void *ptr, size_t regionSize, ze_cache_ext_region_t cacheRegion) override;
+    size_t getMaxCacheReservationSize() override;
+
+  protected:
+    Device &device;
+    NEO::CacheRegion reservedCacheRegion = NEO::CacheRegion::none;
+    size_t reservedCacheSize = 0;
+};
+
+} // namespace L0

level_zero/core/source/cache/linux/cache_reservation_impl_upstream.cpp

@@ -1,11 +1,11 @@
 /*
- * Copyright (C) 2021 Intel Corporation
+ * Copyright (C) 2021-2024 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
  */
 
-#include "level_zero/core/source/cache/linux/cache_reservation_impl.h"
+#include "level_zero/core/source/cache/linux/cache_reservation_impl_upstream.h"
 
 namespace L0 {
 

level_zero/core/source/cache/linux/cache_reservation_impl_upstream.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2021 Intel Corporation
+ * Copyright (C) 2021-2024 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -20,4 +20,4 @@ class CacheReservationImpl : public CacheReservation {
     size_t getMaxCacheReservationSize() override;
 };
 
-} // namespace L0
+} // namespace L0