From c595cccf5d74c2faaec9f0cecfb94b8f3256d177 Mon Sep 17 00:00:00 2001 From: Szymon Morek Date: Tue, 12 Oct 2021 23:03:47 +0000 Subject: [PATCH] Revert "Enable xe_hp_sdv i915 config" This reverts commit 2809462660ed3f0dec01ce148c307e6d347e17bf. Signed-off-by: Szymon Morek --- CMakeLists.txt | 8 +- .../os_interface/linux/CMakeLists.txt | 15 +- .../linux/device_command_stream_fixture_exp.h | 9 +- .../linux/drm_memory_info_tests_exp.cpp | 23 +- .../drm_memory_manager_localmem_tests.cpp | 34 +- .../linux/drm_mock_dg1_internal.h | 78 - .../os_interface/linux/drm_mock_drm_tip.cpp | 54 + .../os_interface/linux/drm_mock_exp.h | 67 +- .../linux/local_memory_helper_tests_dg1.cpp | 106 - .../local_memory_helper_tests_xe_hp_sdv.cpp | 62 - .../source/os_interface/linux/CMakeLists.txt | 3 +- .../os_interface/linux/drm_query_exp.cpp | 34 +- shared/source/os_interface/linux/drm_tip.h | 2 +- .../linux/gem_create_ext_memory_regions.cpp | 31 + .../os_interface/linux/local/CMakeLists.txt | 7 - .../linux/local/dg1/CMakeLists.txt | 18 - .../linux/local/dg1/drm_tip_helper.cpp | 60 - .../dg1/enable_local_memory_helper_dg1.cpp | 14 - .../local/dg1/local_memory_helper_dg1.cpp | 68 - .../linux/local/xe_hp_sdv/CMakeLists.txt | 17 - .../enable_local_memory_helper_xe_hp_sdv.cpp | 14 - .../local_memory_helper_xe_hp_sdv.cpp | 53 - .../linux/local_memory_helper.cpp | 20 - .../os_interface/linux/local_memory_helper.h | 56 - .../os_interface/linux/memory_info_impl.cpp | 44 +- .../os_interface/linux/memory_info_impl.h | 1 + shared/test/common/libult/CMakeLists.txt | 4 - third_party/uapi/drm_tip/{drm => }/drm.h | 0 .../uapi/drm_tip/{drm => }/drm_fourcc.h | 1 - third_party/uapi/drm_tip/{drm => }/drm_mode.h | 0 third_party/uapi/drm_tip/{drm => }/i915_drm.h | 0 third_party/uapi/xe_hp_sdv/drm/drm.h | 1201 ------- third_party/uapi/xe_hp_sdv/drm/drm_fourcc.h | 836 ----- third_party/uapi/xe_hp_sdv/drm/drm_mode.h | 1032 ------ third_party/uapi/xe_hp_sdv/drm/i915_drm.h | 3047 ----------------- 35 files changed, 249 insertions(+), 6770 deletions(-) delete mode 100644 opencl/test/unit_test/os_interface/linux/drm_mock_dg1_internal.h create mode 100644 opencl/test/unit_test/os_interface/linux/drm_mock_drm_tip.cpp delete mode 100644 opencl/test/unit_test/os_interface/linux/local_memory_helper_tests_dg1.cpp delete mode 100644 opencl/test/unit_test/os_interface/linux/local_memory_helper_tests_xe_hp_sdv.cpp create mode 100644 shared/source/os_interface/linux/gem_create_ext_memory_regions.cpp delete mode 100644 shared/source/os_interface/linux/local/CMakeLists.txt delete mode 100644 shared/source/os_interface/linux/local/dg1/CMakeLists.txt delete mode 100644 shared/source/os_interface/linux/local/dg1/drm_tip_helper.cpp delete mode 100644 shared/source/os_interface/linux/local/dg1/enable_local_memory_helper_dg1.cpp delete mode 100644 shared/source/os_interface/linux/local/dg1/local_memory_helper_dg1.cpp delete mode 100644 shared/source/os_interface/linux/local/xe_hp_sdv/CMakeLists.txt delete mode 100644 shared/source/os_interface/linux/local/xe_hp_sdv/enable_local_memory_helper_xe_hp_sdv.cpp delete mode 100644 shared/source/os_interface/linux/local/xe_hp_sdv/local_memory_helper_xe_hp_sdv.cpp delete mode 100644 shared/source/os_interface/linux/local_memory_helper.cpp delete mode 100644 shared/source/os_interface/linux/local_memory_helper.h rename third_party/uapi/drm_tip/{drm => }/drm.h (100%) rename third_party/uapi/drm_tip/{drm => }/drm_fourcc.h (99%) rename third_party/uapi/drm_tip/{drm => }/drm_mode.h (100%) rename third_party/uapi/drm_tip/{drm => }/i915_drm.h (100%) delete mode 100644 third_party/uapi/xe_hp_sdv/drm/drm.h delete mode 100644 third_party/uapi/xe_hp_sdv/drm/drm_fourcc.h delete mode 100644 third_party/uapi/xe_hp_sdv/drm/drm_mode.h delete mode 100644 third_party/uapi/xe_hp_sdv/drm/i915_drm.h diff --git a/CMakeLists.txt b/CMakeLists.txt index c8ecc64f8a..a36d8ae701 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -339,15 +339,9 @@ else() message(FATAL_ERROR "Metrics Discovery headers not available!") endif() -if(SUPPORT_XE_HP_SDV AND "${BRANCH_TYPE}" STREQUAL "") - set(I915_LOCAL_MEM_EXP TRUE) -endif() if(SUPPORT_DG1 AND "${BRANCH_TYPE}" STREQUAL "") + get_filename_component(I915_INCLUDES_DIR "${NEO_SOURCE_DIR}/third_party/uapi/dg1" ABSOLUTE) set(I915_LOCAL_MEM_EXP TRUE) -endif() - -if(I915_LOCAL_MEM_EXP) - get_filename_component(I915_INCLUDES_DIR "${NEO_SOURCE_DIR}/third_party/uapi/drm_tip" ABSOLUTE) else() get_filename_component(I915_INCLUDES_DIR "${NEO_SOURCE_DIR}/third_party${BRANCH_DIR_SUFFIX}uapi" ABSOLUTE) endif() diff --git a/opencl/test/unit_test/os_interface/linux/CMakeLists.txt b/opencl/test/unit_test/os_interface/linux/CMakeLists.txt index c7325d6395..785d1b8d4c 100644 --- a/opencl/test/unit_test/os_interface/linux/CMakeLists.txt +++ b/opencl/test/unit_test/os_interface/linux/CMakeLists.txt @@ -49,6 +49,7 @@ if(I915_LOCAL_MEM_EXP) list(APPEND IGDRCL_SRCS_tests_os_interface_linux ${CMAKE_CURRENT_SOURCE_DIR}/drm_memory_info_tests_exp.cpp ${CMAKE_CURRENT_SOURCE_DIR}/drm_memory_manager_localmem_tests.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/drm_mock_drm_tip.cpp ) else() list(APPEND IGDRCL_SRCS_tests_os_interface_linux @@ -60,20 +61,6 @@ if(NEO__LIBVA_FOUND) ${CMAKE_CURRENT_SOURCE_DIR}/drm_va_sharing_tests.cpp ) endif() - -if(SUPPORT_DG1 AND "${BRANCH_TYPE}" STREQUAL "") - list(APPEND IGDRCL_SRCS_tests_os_interface_linux - ${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper_tests_dg1.cpp - ${CMAKE_CURRENT_SOURCE_DIR}/drm_mock_dg1_internal.h - ) -endif() - -if(SUPPORT_XE_HP_SDV AND "${BRANCH_TYPE}" STREQUAL "") - list(APPEND IGDRCL_SRCS_tests_os_interface_linux - ${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper_tests_xe_hp_sdv.cpp - ) -endif() - if(UNIX) target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_os_interface_linux}) endif() diff --git a/opencl/test/unit_test/os_interface/linux/device_command_stream_fixture_exp.h b/opencl/test/unit_test/os_interface/linux/device_command_stream_fixture_exp.h index 10d7e3dc5a..af9c567d62 100644 --- a/opencl/test/unit_test/os_interface/linux/device_command_stream_fixture_exp.h +++ b/opencl/test/unit_test/os_interface/linux/device_command_stream_fixture_exp.h @@ -68,13 +68,18 @@ class DrmMockCustomExp : public DrmMockCustom { } } break; default: { - std::cout << "unexpected IOCTL: " << std::hex << request << std::endl; - UNRECOVERABLE_IF(true); + auto ret = ioctlGemCreateExt(request, arg); + if (ret != 0) { + std::cout << "unexpected IOCTL: " << std::hex << request << std::endl; + UNRECOVERABLE_IF(true); + } } break; } return 0; } + int ioctlGemCreateExt(unsigned long request, void *arg); + DrmMockCustomExp() : DrmMockCustom() { ioctlExp_cnt.reset(); ioctlExp_expected.reset(); diff --git a/opencl/test/unit_test/os_interface/linux/drm_memory_info_tests_exp.cpp b/opencl/test/unit_test/os_interface/linux/drm_memory_info_tests_exp.cpp index af84c11584..bca4edafcd 100644 --- a/opencl/test/unit_test/os_interface/linux/drm_memory_info_tests_exp.cpp +++ b/opencl/test/unit_test/os_interface/linux/drm_memory_info_tests_exp.cpp @@ -21,15 +21,20 @@ TEST(MemoryInfo, givenMemoryRegionQuerySupportedWhenQueryingMemoryInfoThenMemory auto executionEnvironment = std::make_unique(); executionEnvironment->prepareRootDeviceEnvironments(1); - auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); - ASSERT_NE(nullptr, drm); + for (auto onDrmTip : {false, true}) { + auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); + ASSERT_NE(nullptr, drm); - drm->queryMemoryInfo(); + drm->queryMemoryRegionOnDrmTip = onDrmTip; - EXPECT_EQ(2u, drm->ioctlCallsCount); - auto memoryInfo = static_cast(drm->getMemoryInfo()); - ASSERT_NE(nullptr, memoryInfo); - EXPECT_EQ(2u, memoryInfo->getDrmRegionInfos().size()); + drm->queryMemoryInfo(); + EXPECT_EQ(2u, drm->ioctlCallsCount); + + auto memoryInfo = static_cast(drm->getMemoryInfo()); + + ASSERT_NE(nullptr, memoryInfo); + EXPECT_EQ(2u, memoryInfo->getDrmRegionInfos().size()); + } } TEST(MemoryInfo, givenMemoryRegionQueryNotSupportedWhenQueryingMemoryInfoThenMemoryInfoIsNotCreated) { @@ -239,7 +244,7 @@ TEST(MemoryInfo, givenMemoryInfoWithRegionsWhenCreatingGemWithExtensionsThenRetu auto ret = memoryInfo->createGemExt(drm.get(), ®ionInfo, 2, 1024, handle); EXPECT_EQ(1u, handle); EXPECT_EQ(0u, ret); - EXPECT_EQ(1u, drm->ioctlCallsCount); + EXPECT_EQ(2u, drm->ioctlCallsCount); EXPECT_EQ(1024u, drm->createExt.size); } @@ -262,7 +267,7 @@ TEST(MemoryInfo, givenMemoryInfoWithRegionsWhenCreatingGemExtWithSingleRegionThe auto ret = memoryInfo->createGemExtWithSingleRegion(drm.get(), 1, 1024, handle); EXPECT_EQ(1u, handle); EXPECT_EQ(0u, ret); - EXPECT_EQ(1u, drm->ioctlCallsCount); + EXPECT_EQ(2u, drm->ioctlCallsCount); EXPECT_EQ(I915_MEMORY_CLASS_DEVICE, drm->memRegions.memory_class); EXPECT_EQ(1024u, drm->createExt.size); } diff --git a/opencl/test/unit_test/os_interface/linux/drm_memory_manager_localmem_tests.cpp b/opencl/test/unit_test/os_interface/linux/drm_memory_manager_localmem_tests.cpp index 53d3d5705f..73e3c66d7b 100644 --- a/opencl/test/unit_test/os_interface/linux/drm_memory_manager_localmem_tests.cpp +++ b/opencl/test/unit_test/os_interface/linux/drm_memory_manager_localmem_tests.cpp @@ -148,11 +148,19 @@ TEST_F(DrmMemoryManagerLocalMemoryTest, givenDrmMemoryManagerWhenCreateBufferObj (1 << (MemoryBanks::getBankForLocalMemory(0) - 1)), 1)); ASSERT_NE(nullptr, bo); - EXPECT_EQ(1u, mock->ioctlCallsCount); + + EXPECT_EQ(2u, mock->ioctlCallsCount); + EXPECT_EQ(1u, mock->createExt.handle); EXPECT_EQ(size, mock->createExt.size); - EXPECT_EQ(1u, mock->numRegions); + EXPECT_EQ(I915_GEM_CREATE_EXT_SETPARAM, mock->setparamRegion.base.name); + + auto regionParam = mock->setparamRegion.param; + EXPECT_EQ(0u, regionParam.handle); + EXPECT_EQ(1u, regionParam.size); + EXPECT_EQ(I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS, regionParam.param); + auto memRegions = mock->memRegions; EXPECT_EQ(I915_MEMORY_CLASS_DEVICE, memRegions.memory_class); EXPECT_EQ(0u, memRegions.memory_instance); @@ -1076,6 +1084,28 @@ TEST_F(DrmMemoryManagerLocalMemoryTest, givenAllocationWithUnifiedMemoryAllocati memoryManager->freeGraphicsMemory(allocation); } +TEST_F(DrmMemoryManagerLocalMemoryTest, whenPrintBOCreateDestroyResultFlagIsSetWhileCreatingBufferObjectInMemoryRegionThenDebugInformationIsPrinted) { + DebugManagerStateRestore stateRestore; + DebugManager.flags.PrintBOCreateDestroyResult.set(true); + DebugManager.flags.EnableLocalMemory.set(1); + + drm_i915_memory_region_info regionInfo[2] = {}; + regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0}; + regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; + + mock->memoryInfo.reset(new MemoryInfoImpl(regionInfo, 2)); + auto gpuAddress = 0x1234u; + auto size = MemoryConstants::pageSize64k; + + testing::internal::CaptureStdout(); + auto bo = std::unique_ptr(memoryManager->createBufferObjectInMemoryRegion(&memoryManager->getDrm(0), gpuAddress, size, (1 << (MemoryBanks::getBankForLocalMemory(0) - 1)), 1)); + ASSERT_NE(nullptr, bo); + + std::string output = testing::internal::GetCapturedStdout(); + std::string expectedOutput("Performing GEM_CREATE_EXT with { size: 65536, memory class: 1, memory instance: 0 }\nGEM_CREATE_EXT with EXT_SETPARAM has returned: 0 BO-1 with size: 65536\n"); + EXPECT_EQ(expectedOutput, output); +} + TEST(ResidencyTests, whenBuffersIsCreatedWithMakeResidentFlagThenItSuccessfulyCreates) { VariableBackup backup(&ultHwConfig); ultHwConfig.useMockedPrepareDeviceEnvironmentsFunc = false; diff --git a/opencl/test/unit_test/os_interface/linux/drm_mock_dg1_internal.h b/opencl/test/unit_test/os_interface/linux/drm_mock_dg1_internal.h deleted file mode 100644 index 9af0000fea..0000000000 --- a/opencl/test/unit_test/os_interface/linux/drm_mock_dg1_internal.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2020-2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#pragma once - -#include "opencl/test/unit_test/os_interface/linux/drm_mock_exp.h" - -namespace DG1_INTERNAL { -#undef DRM_IOCTL_I915_GEM_CREATE_EXT -#undef __I915_EXEC_UNKNOWN_FLAGS -#include "third_party/uapi/dg1/drm/i915_drm.h" -} // namespace DG1_INTERNAL - -using namespace NEO; - -class DrmMockDg1Internal : public DrmMockExp { - public: - DrmMockDg1Internal(RootDeviceEnvironment &rootDeviceEnvironment) : DrmMockDg1Internal(rootDeviceEnvironment, defaultHwInfo.get()) {} - DrmMockDg1Internal(RootDeviceEnvironment &rootDeviceEnvironment, const HardwareInfo *inputHwInfo) : DrmMockExp(rootDeviceEnvironment) { - rootDeviceEnvironment.setHwInfo(inputHwInfo); - } - - void handleQueryItem(drm_i915_query_item *queryItem) override { - switch (queryItem->query_id) { - case DRM_I915_QUERY_MEMORY_REGIONS: - if (queryMemoryRegionInfoSuccessCount == 0) { - queryItem->length = -EINVAL; - } else { - queryMemoryRegionInfoSuccessCount--; - auto numberOfLocalMemories = 1u; - auto numberOfRegions = 1u + numberOfLocalMemories; - int regionInfoSize = sizeof(DG1_INTERNAL::drm_i915_query_memory_regions) + numberOfRegions * sizeof(DG1_INTERNAL::drm_i915_memory_region_info); - if (queryItem->length == 0) { - queryItem->length = regionInfoSize; - } else { - EXPECT_EQ(regionInfoSize, queryItem->length); - auto queryMemoryRegionInfo = reinterpret_cast(queryItem->data_ptr); - EXPECT_EQ(0u, queryMemoryRegionInfo->num_regions); - queryMemoryRegionInfo->num_regions = numberOfRegions; - queryMemoryRegionInfo->regions[0].region.memory_class = I915_MEMORY_CLASS_SYSTEM; - queryMemoryRegionInfo->regions[0].region.memory_instance = 1; - queryMemoryRegionInfo->regions[0].probed_size = 2 * MemoryConstants::gigaByte; - queryMemoryRegionInfo->regions[1].region.memory_class = I915_MEMORY_CLASS_DEVICE; - queryMemoryRegionInfo->regions[1].region.memory_instance = 1; - queryMemoryRegionInfo->regions[1].probed_size = 2 * MemoryConstants::gigaByte; - } - } - break; - } - } - - int handleKernelSpecificRequests(unsigned long request, void *arg) override { - if (request == DRM_IOCTL_I915_GEM_CREATE_EXT) { - auto createExtParams = static_cast(arg); - if (createExtParams->size == 0) { - return EINVAL; - } - createExtParams->handle = 1u; - this->createExt = *createExtParams; - auto setparamRegion = reinterpret_cast(createExtParams->extensions); - if (setparamRegion->base.name != I915_GEM_CREATE_EXT_SETPARAM) { - return EINVAL; - } - auto regionParam = reinterpret_cast(&setparamRegion->param); - if (regionParam->param != (I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS)) { - return EINVAL; - } - numRegions = regionParam->size; - memRegions = *reinterpret_cast(regionParam->data); - return gemCreateExtRetVal; - } - return -1; - } -}; diff --git a/opencl/test/unit_test/os_interface/linux/drm_mock_drm_tip.cpp b/opencl/test/unit_test/os_interface/linux/drm_mock_drm_tip.cpp new file mode 100644 index 0000000000..ccffa3d44e --- /dev/null +++ b/opencl/test/unit_test/os_interface/linux/drm_mock_drm_tip.cpp @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "opencl/test/unit_test/os_interface/linux/device_command_stream_fixture_exp.h" +#include "opencl/test/unit_test/os_interface/linux/drm_mock_exp.h" + +// clang-format off +#include "shared/source/os_interface/linux/drm_tip.h" +// clang-format on + +void DrmMockExp::handleQueryItemOnDrmTip(drm_i915_query_item *queryItem) { + switch (queryItem->query_id) { + case DRM_I915_QUERY_MEMORY_REGIONS: + if (queryMemoryRegionInfoSuccessCount == 0) { + queryItem->length = -EINVAL; + } else { + queryMemoryRegionInfoSuccessCount--; + auto numberOfLocalMemories = 1u; + auto numberOfRegions = 1u + numberOfLocalMemories; + int regionInfoSize = sizeof(DRM_TIP::drm_i915_query_memory_regions) + numberOfRegions * sizeof(DRM_TIP::drm_i915_memory_region_info); + if (queryItem->length == 0) { + queryItem->length = regionInfoSize; + } else { + EXPECT_EQ(regionInfoSize, queryItem->length); + auto queryMemoryRegionInfo = reinterpret_cast(queryItem->data_ptr); + EXPECT_EQ(0u, queryMemoryRegionInfo->num_regions); + queryMemoryRegionInfo->num_regions = numberOfRegions; + queryMemoryRegionInfo->regions[0].region.memory_class = I915_MEMORY_CLASS_SYSTEM; + queryMemoryRegionInfo->regions[0].region.memory_instance = 1; + queryMemoryRegionInfo->regions[0].probed_size = 2 * MemoryConstants::gigaByte; + queryMemoryRegionInfo->regions[1].region.memory_class = I915_MEMORY_CLASS_DEVICE; + queryMemoryRegionInfo->regions[1].region.memory_instance = 1; + queryMemoryRegionInfo->regions[1].probed_size = 2 * MemoryConstants::gigaByte; + } + } + break; + } +} + +int DrmMockCustomExp::ioctlGemCreateExt(unsigned long request, void *arg) { + if (request == DRM_IOCTL_I915_GEM_CREATE_EXT) { + auto createExtParams = reinterpret_cast(arg); + createExtSize = createExtParams->size; + createExtHandle = createExtParams->handle; + createExtExtensions = createExtParams->extensions; + ioctlExp_cnt.gemCreateExt++; + return 0; + } + return -1; +} diff --git a/opencl/test/unit_test/os_interface/linux/drm_mock_exp.h b/opencl/test/unit_test/os_interface/linux/drm_mock_exp.h index d72523bc36..7c00e3ba74 100644 --- a/opencl/test/unit_test/os_interface/linux/drm_mock_exp.h +++ b/opencl/test/unit_test/os_interface/linux/drm_mock_exp.h @@ -23,11 +23,12 @@ class DrmMockExp : public DrmMock { uint32_t i915QuerySuccessCount = std::numeric_limits::max(); uint32_t queryMemoryRegionInfoSuccessCount = std::numeric_limits::max(); + bool queryMemoryRegionOnDrmTip = false; //DRM_IOCTL_I915_GEM_CREATE_EXT drm_i915_gem_create_ext createExt{}; + drm_i915_gem_create_ext_setparam setparamRegion{}; drm_i915_gem_memory_class_instance memRegions{}; - uint32_t numRegions = 0; int gemCreateExtRetVal = 0; //DRM_IOCTL_I915_GEM_MMAP_OFFSET @@ -46,19 +47,52 @@ class DrmMockExp : public DrmMock { return EINVAL; } for (auto i = 0u; i < query->num_items; i++) { - handleQueryItem(reinterpret_cast(query->items_ptr) + i); + if (queryMemoryRegionOnDrmTip) { + handleQueryItemOnDrmTip(reinterpret_cast(query->items_ptr) + i); + } else { + handleQueryItem(reinterpret_cast(query->items_ptr) + i); + } } return 0; + } else if (request == DRM_IOCTL_I915_GEM_CREATE_EXT) { + auto createExtParams = static_cast(arg); + if (createExtParams->size == 0) { + return EINVAL; + } + this->createExt.size = createExtParams->size; + this->createExt.handle = createExtParams->handle = 1u; + auto extensions = reinterpret_cast(createExtParams->extensions); + if (extensions == nullptr) { + return EINVAL; + } + this->setparamRegion = *extensions; + if (this->setparamRegion.base.name != I915_GEM_CREATE_EXT_SETPARAM) { + return EINVAL; + } + if ((this->setparamRegion.param.size == 0) || + (this->setparamRegion.param.param != (I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS))) { + return EINVAL; + } + auto data = reinterpret_cast(this->setparamRegion.param.data); + if (data == nullptr) { + return EINVAL; + } + this->memRegions = *data; + if ((this->memRegions.memory_class != I915_MEMORY_CLASS_SYSTEM) && (this->memRegions.memory_class != I915_MEMORY_CLASS_DEVICE)) { + return EINVAL; + } + return gemCreateExtRetVal; + } else if (request == DRM_IOCTL_I915_GEM_MMAP_OFFSET) { auto mmap_arg = static_cast(arg); mmapOffsetFlagsReceived = mmap_arg->flags; mmap_arg->offset = offset; return mmapOffsetRetVal; } - return handleKernelSpecificRequests(request, arg); + return -1; } - virtual void handleQueryItem(drm_i915_query_item *queryItem) { + void handleQueryItem(drm_i915_query_item *queryItem) { switch (queryItem->query_id) { case DRM_I915_QUERY_MEMORY_REGIONS: if (queryMemoryRegionInfoSuccessCount == 0) { @@ -87,28 +121,5 @@ class DrmMockExp : public DrmMock { } } - virtual int handleKernelSpecificRequests(unsigned long request, void *arg) { - if (request == DRM_IOCTL_I915_GEM_CREATE_EXT) { - auto createExtParams = static_cast(arg); - if (createExtParams->size == 0) { - return EINVAL; - } - createExtParams->handle = 1u; - this->createExt = *createExtParams; - auto extMemRegions = reinterpret_cast(createExt.extensions); - if (extMemRegions->base.name != I915_GEM_CREATE_EXT_MEMORY_REGIONS) { - return EINVAL; - } - this->numRegions = extMemRegions->num_regions; - this->memRegions = *reinterpret_cast(extMemRegions->regions); - if (this->numRegions == 0) { - return EINVAL; - } - if ((this->memRegions.memory_class != I915_MEMORY_CLASS_SYSTEM) && (this->memRegions.memory_class != I915_MEMORY_CLASS_DEVICE)) { - return EINVAL; - } - return gemCreateExtRetVal; - } - return -1; - } + void handleQueryItemOnDrmTip(drm_i915_query_item *queryItem); }; diff --git a/opencl/test/unit_test/os_interface/linux/local_memory_helper_tests_dg1.cpp b/opencl/test/unit_test/os_interface/linux/local_memory_helper_tests_dg1.cpp deleted file mode 100644 index 174e043ad2..0000000000 --- a/opencl/test/unit_test/os_interface/linux/local_memory_helper_tests_dg1.cpp +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#include "shared/source/execution_environment/execution_environment.h" -#include "shared/source/os_interface/linux/local_memory_helper.h" -#include "shared/source/os_interface/linux/memory_info_impl.h" -#include "shared/test/common/helpers/debug_manager_state_restore.h" -#include "shared/test/common/helpers/default_hw_info.h" - -#include "opencl/test/unit_test/os_interface/linux/drm_mock_dg1_internal.h" -#include "opencl/test/unit_test/os_interface/linux/drm_mock_exp.h" -#include "test.h" - -using namespace NEO; - -using LocalMemoryHelperTestsDg1 = ::testing::Test; - -DG1TEST_F(LocalMemoryHelperTestsDg1, givenDg1WhenCreateGemExtThenReturnCorrectValue) { - auto executionEnvironment = std::make_unique(); - executionEnvironment->prepareRootDeviceEnvironments(1); - auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); - - drm_i915_memory_region_info regionInfo[2] = {}; - regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0}; - regionInfo[0].probed_size = 8 * GB; - regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; - regionInfo[1].probed_size = 16 * GB; - - auto localMemHelper = LocalMemoryHelper::get(defaultHwInfo->platform.eProductFamily); - uint32_t handle = 0; - auto ret = localMemHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); - - EXPECT_EQ(0u, ret); - EXPECT_EQ(1u, handle); - EXPECT_EQ(1u, drm->numRegions); - EXPECT_EQ(1024u, drm->createExt.size); - EXPECT_EQ(I915_MEMORY_CLASS_DEVICE, drm->memRegions.memory_class); -} - -DG1TEST_F(LocalMemoryHelperTestsDg1, givenDg1WithDrmTipWhenCreateGemExtWithDebugFlagThenPrintDebugInfo) { - DebugManagerStateRestore stateRestore; - DebugManager.flags.PrintBOCreateDestroyResult.set(true); - - auto executionEnvironment = std::make_unique(); - executionEnvironment->prepareRootDeviceEnvironments(1); - auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); - drm_i915_memory_region_info regionInfo[2] = {}; - regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0}; - regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; - - testing::internal::CaptureStdout(); - auto localMemHelper = LocalMemoryHelper::get(defaultHwInfo->platform.eProductFamily); - uint32_t handle = 0; - - auto ret = localMemHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); - - std::string output = testing::internal::GetCapturedStdout(); - std::string expectedOutput("Performing GEM_CREATE_EXT with { size: 1024, memory class: 1, memory instance: 0 }\nGEM_CREATE_EXT with EXT_MEMORY_REGIONS has returned: 0 BO-1 with size: 1024\n"); - EXPECT_EQ(expectedOutput, output); - EXPECT_EQ(1u, drm->ioctlCallsCount); - EXPECT_EQ(0u, ret); -} - -DG1TEST_F(LocalMemoryHelperTestsDg1, givenDg1WhenCreateGemExtWithDebugFlagThenPrintDebugInfo) { - DebugManagerStateRestore stateRestore; - DebugManager.flags.PrintBOCreateDestroyResult.set(true); - - auto executionEnvironment = std::make_unique(); - executionEnvironment->prepareRootDeviceEnvironments(1); - auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); - drm_i915_memory_region_info regionInfo[2] = {}; - regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0}; - regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; - - testing::internal::CaptureStdout(); - auto localMemHelper = LocalMemoryHelper::get(defaultHwInfo->platform.eProductFamily); - uint32_t handle = 0; - - auto ret = localMemHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); - - std::string output = testing::internal::GetCapturedStdout(); - std::string expectedOutput("Performing GEM_CREATE_EXT with { size: 1024, memory class: 1, memory instance: 0 }\nGEM_CREATE_EXT with EXT_SETPARAM has returned: 0 BO-1 with size: 1024\n"); - EXPECT_EQ(expectedOutput, output); - EXPECT_EQ(2u, drm->ioctlCallsCount); - EXPECT_EQ(0u, ret); -} - -DG1TEST_F(LocalMemoryHelperTestsDg1, givenDg1AndMemoryRegionQuerySupportedWhenQueryingMemoryInfoThenMemoryInfoIsCreatedWithRegions) { - auto executionEnvironment = std::make_unique(); - executionEnvironment->prepareRootDeviceEnvironments(1); - - auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); - ASSERT_NE(nullptr, drm); - - drm->queryMemoryInfo(); - EXPECT_EQ(2u, drm->ioctlCallsCount); - - auto memoryInfo = static_cast(drm->getMemoryInfo()); - - ASSERT_NE(nullptr, memoryInfo); - EXPECT_EQ(2u, memoryInfo->getDrmRegionInfos().size()); -} diff --git a/opencl/test/unit_test/os_interface/linux/local_memory_helper_tests_xe_hp_sdv.cpp b/opencl/test/unit_test/os_interface/linux/local_memory_helper_tests_xe_hp_sdv.cpp deleted file mode 100644 index 3a0327ad38..0000000000 --- a/opencl/test/unit_test/os_interface/linux/local_memory_helper_tests_xe_hp_sdv.cpp +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#include "shared/source/execution_environment/execution_environment.h" -#include "shared/source/os_interface/linux/local_memory_helper.h" -#include "shared/test/common/helpers/debug_manager_state_restore.h" -#include "shared/test/common/helpers/default_hw_info.h" - -#include "opencl/test/unit_test/os_interface/linux/drm_mock_exp.h" -#include "test.h" - -using namespace NEO; - -using LocalMemoryHelperTestsXeHpSdv = ::testing::Test; - -XEHPTEST_F(LocalMemoryHelperTestsXeHpSdv, givenXeHpSdvWhenCreateGemExtThenReturnCorrectValue) { - auto executionEnvironment = std::make_unique(); - executionEnvironment->prepareRootDeviceEnvironments(1); - auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); - - drm_i915_memory_region_info regionInfo[2] = {}; - regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0}; - regionInfo[0].probed_size = 8 * GB; - regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; - regionInfo[1].probed_size = 16 * GB; - - auto localMemHelper = LocalMemoryHelper::get(defaultHwInfo->platform.eProductFamily); - uint32_t handle = 0; - auto ret = localMemHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); - - EXPECT_EQ(0u, ret); - EXPECT_EQ(1u, handle); - EXPECT_EQ(1u, drm->numRegions); - EXPECT_EQ(1024u, drm->createExt.size); - EXPECT_EQ(I915_MEMORY_CLASS_DEVICE, drm->memRegions.memory_class); -} - -XEHPTEST_F(LocalMemoryHelperTestsXeHpSdv, givenXeHpSdvWhenCreateGemExtWithDebugFlagThenPrintDebugInfo) { - DebugManagerStateRestore stateRestore; - DebugManager.flags.PrintBOCreateDestroyResult.set(true); - - auto executionEnvironment = std::make_unique(); - executionEnvironment->prepareRootDeviceEnvironments(1); - auto drm = std::make_unique(*executionEnvironment->rootDeviceEnvironments[0]); - - drm_i915_memory_region_info regionInfo[2] = {}; - regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0}; - regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0}; - - testing::internal::CaptureStdout(); - auto localMemHelper = LocalMemoryHelper::get(defaultHwInfo->platform.eProductFamily); - uint32_t handle = 0; - localMemHelper->createGemExt(drm.get(), ®ionInfo[1], 1, 1024, handle); - - std::string output = testing::internal::GetCapturedStdout(); - std::string expectedOutput("Performing GEM_CREATE_EXT with { size: 1024, memory class: 1, memory instance: 0 }\nGEM_CREATE_EXT with EXT_MEMORY_REGIONS has returned: 0 BO-1 with size: 1024\n"); - EXPECT_EQ(expectedOutput, output); -} \ No newline at end of file diff --git a/shared/source/os_interface/linux/CMakeLists.txt b/shared/source/os_interface/linux/CMakeLists.txt index 6f09091795..6a73e86ade 100644 --- a/shared/source/os_interface/linux/CMakeLists.txt +++ b/shared/source/os_interface/linux/CMakeLists.txt @@ -100,8 +100,7 @@ if(I915_LOCAL_MEM_EXP) ${CMAKE_CURRENT_SOURCE_DIR}/drm_query_exp.cpp ${CMAKE_CURRENT_SOURCE_DIR}/drm_tip.h ${CMAKE_CURRENT_SOURCE_DIR}/memory_info_impl.cpp - ${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper.h - ${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/gem_create_ext_memory_regions.cpp ) else() list(APPEND NEO_CORE_OS_INTERFACE_LINUX diff --git a/shared/source/os_interface/linux/drm_query_exp.cpp b/shared/source/os_interface/linux/drm_query_exp.cpp index 1de2a05fcb..efd78403b3 100644 --- a/shared/source/os_interface/linux/drm_query_exp.cpp +++ b/shared/source/os_interface/linux/drm_query_exp.cpp @@ -9,12 +9,12 @@ #include "shared/source/helpers/string.h" #include "shared/source/os_interface/linux/drm_engine_mapper.h" #include "shared/source/os_interface/linux/engine_info_impl.h" -#include "shared/source/os_interface/linux/local_memory_helper.h" #include "shared/source/os_interface/linux/memory_info_impl.h" #include "shared/source/os_interface/linux/sys_calls.h" #include "drm_neo.h" #include "drm_query_flags.h" +#include "drm_tip.h" #include @@ -30,6 +30,25 @@ std::string getIoctlParamStringRemaining(int param) { return std::to_string(param); } +std::unique_ptr translateDataQueryOnDrmTip(uint8_t *dataQuery, int32_t &length) { + auto dataOnDrmTip = reinterpret_cast(dataQuery); + auto lengthOnDrmTrip = static_cast(sizeof(DRM_TIP::drm_i915_query_memory_regions) + dataOnDrmTip->num_regions * sizeof(DRM_TIP::drm_i915_memory_region_info)); + if (length == lengthOnDrmTrip) { + auto lengthTranslated = static_cast(sizeof(drm_i915_query_memory_regions) + dataOnDrmTip->num_regions * sizeof(drm_i915_memory_region_info)); + auto dataQueryTranslated = std::make_unique(lengthTranslated); + auto dataTranslated = reinterpret_cast(dataQueryTranslated.get()); + dataTranslated->num_regions = dataOnDrmTip->num_regions; + for (uint32_t i = 0; i < dataTranslated->num_regions; i++) { + dataTranslated->regions[i].region.memory_class = dataOnDrmTip->regions[i].region.memory_class; + dataTranslated->regions[i].region.memory_instance = dataOnDrmTip->regions[i].region.memory_instance; + dataTranslated->regions[i].probed_size = dataOnDrmTip->regions[i].probed_size; + dataTranslated->regions[i].unallocated_size = dataOnDrmTip->regions[i].unallocated_size; + } + length = lengthTranslated; + return dataQueryTranslated; + } + return nullptr; +} } // namespace IoctlHelper bool Drm::queryEngineInfo(bool isSysmanEnabled) { @@ -47,12 +66,13 @@ bool Drm::queryMemoryInfo() { auto length = 0; auto dataQuery = this->query(DRM_I915_QUERY_MEMORY_REGIONS, DrmQueryItemFlags::empty, length); if (dataQuery) { - auto pHwInfo = getRootDeviceEnvironment().getHardwareInfo(); - auto localMemHelper = LocalMemoryHelper::get(pHwInfo->platform.eProductFamily); - auto data = localMemHelper->translateIfRequired(dataQuery.release(), length); - auto memRegions = reinterpret_cast(data.get()); - DEBUG_BREAK_IF(static_cast(length) != sizeof(drm_i915_query_memory_regions) + memRegions->num_regions * sizeof(drm_i915_memory_region_info)); - this->memoryInfo.reset(new MemoryInfoImpl(memRegions->regions, memRegions->num_regions)); + auto dataQueryTranslated = IoctlHelper::translateDataQueryOnDrmTip(dataQuery.get(), length); + if (dataQueryTranslated) { + dataQuery.reset(dataQueryTranslated.release()); + } + auto data = reinterpret_cast(dataQuery.get()); + DEBUG_BREAK_IF(static_cast(length) != sizeof(drm_i915_query_memory_regions) + data->num_regions * sizeof(drm_i915_memory_region_info)); + this->memoryInfo.reset(new MemoryInfoImpl(data->regions, data->num_regions)); return true; } return false; diff --git a/shared/source/os_interface/linux/drm_tip.h b/shared/source/os_interface/linux/drm_tip.h index 515ae98cd1..10703a168e 100644 --- a/shared/source/os_interface/linux/drm_tip.h +++ b/shared/source/os_interface/linux/drm_tip.h @@ -10,5 +10,5 @@ namespace DRM_TIP { #undef DRM_IOCTL_I915_GEM_CREATE_EXT #undef __I915_EXEC_UNKNOWN_FLAGS -#include "third_party/uapi/drm_tip/drm/i915_drm.h" +#include "third_party/uapi/drm_tip/i915_drm.h" } // namespace DRM_TIP diff --git a/shared/source/os_interface/linux/gem_create_ext_memory_regions.cpp b/shared/source/os_interface/linux/gem_create_ext_memory_regions.cpp new file mode 100644 index 0000000000..0fbf6853c3 --- /dev/null +++ b/shared/source/os_interface/linux/gem_create_ext_memory_regions.cpp @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/debug_helpers.h" +#include "shared/source/os_interface/linux/memory_info_impl.h" + +#include "drm_tip.h" + +namespace NEO { + +uint32_t MemoryInfoImpl::createGemExtMemoryRegions(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) { + DRM_TIP::drm_i915_gem_create_ext_memory_regions extRegions{}; + extRegions.base.name = I915_GEM_CREATE_EXT_MEMORY_REGIONS; + extRegions.num_regions = dataSize; + extRegions.regions = reinterpret_cast(data); + + drm_i915_gem_create_ext createExt{}; + createExt.size = allocSize; + createExt.extensions = reinterpret_cast(&extRegions); + + auto ret = drm->ioctl(DRM_IOCTL_I915_GEM_CREATE_EXT, &createExt); + + handle = createExt.handle; + return ret; +} + +} // namespace NEO diff --git a/shared/source/os_interface/linux/local/CMakeLists.txt b/shared/source/os_interface/linux/local/CMakeLists.txt deleted file mode 100644 index cef68e2de8..0000000000 --- a/shared/source/os_interface/linux/local/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) 2021 Intel Corporation -# -# SPDX-License-Identifier: MIT -# - -add_subdirectories() diff --git a/shared/source/os_interface/linux/local/dg1/CMakeLists.txt b/shared/source/os_interface/linux/local/dg1/CMakeLists.txt deleted file mode 100644 index 96d4c3c669..0000000000 --- a/shared/source/os_interface/linux/local/dg1/CMakeLists.txt +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (C) 2021 Intel Corporation -# -# SPDX-License-Identifier: MIT -# - -if(SUPPORT_DG1 AND "${BRANCH_TYPE}" STREQUAL "") - set(NEO_CORE_OS_INTERFACE_LINUX_LOCAL_DG1 - ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt - ${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper_dg1.cpp - ${CMAKE_CURRENT_SOURCE_DIR}/drm_tip_helper.cpp - ) - set(CORE_SRCS_LINK_LINUX_LOCAL_DG1 - ${CMAKE_CURRENT_SOURCE_DIR}/enable_local_memory_helper_dg1.cpp - ) - set_property(GLOBAL APPEND PROPERTY NEO_CORE_OS_INTERFACE_LINUX ${NEO_CORE_OS_INTERFACE_LINUX_LOCAL_DG1}) - set_property(GLOBAL APPEND PROPERTY NEO_CORE_SRCS_LINK ${CORE_SRCS_LINK_LINUX_LOCAL_DG1}) -endif() diff --git a/shared/source/os_interface/linux/local/dg1/drm_tip_helper.cpp b/shared/source/os_interface/linux/local/dg1/drm_tip_helper.cpp deleted file mode 100644 index 21b96e8d0a..0000000000 --- a/shared/source/os_interface/linux/local/dg1/drm_tip_helper.cpp +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#include "shared/source/os_interface/linux/local_memory_helper.h" - -#include "third_party/uapi/drm_tip/drm/i915_drm.h" - -#include - -namespace NEO { - -uint32_t createGemExtMemoryRegions(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) { - drm_i915_gem_create_ext_memory_regions extRegions{}; - extRegions.base.name = I915_GEM_CREATE_EXT_MEMORY_REGIONS; - extRegions.num_regions = dataSize; - extRegions.regions = reinterpret_cast(data); - - drm_i915_gem_create_ext createExt{}; - createExt.size = allocSize; - createExt.extensions = reinterpret_cast(&extRegions); - - auto ret = LocalMemoryHelper::ioctl(drm, DRM_IOCTL_I915_GEM_CREATE_EXT, &createExt); - - handle = createExt.handle; - return ret; -} - -bool isQueryDrmTip(uint8_t *dataQuery, int32_t length) { - auto dataOnDrmTip = reinterpret_cast(dataQuery); - auto lengthOnDrmTip = static_cast(sizeof(drm_i915_query_memory_regions) + dataOnDrmTip->num_regions * sizeof(drm_i915_memory_region_info)); - return length == lengthOnDrmTip; -} - -namespace DG1_INTERNAL { -#undef DRM_IOCTL_I915_GEM_CREATE_EXT -#undef __I915_EXEC_UNKNOWN_FLAGS -#include "third_party/uapi/dg1/drm/i915_drm.h" -} // namespace DG1_INTERNAL - -std::unique_ptr translateToDrmTip(uint8_t *dataQuery, int32_t &length) { - auto dataOnInternalDrm = reinterpret_cast(dataQuery); - auto lengthTranslated = static_cast(sizeof(drm_i915_query_memory_regions) + dataOnInternalDrm->num_regions * sizeof(drm_i915_memory_region_info)); - auto dataQueryTranslated = std::make_unique(lengthTranslated); - auto dataTranslated = reinterpret_cast(dataQueryTranslated.get()); - dataTranslated->num_regions = dataOnInternalDrm->num_regions; - for (uint32_t i = 0; i < dataTranslated->num_regions; i++) { - dataTranslated->regions[i].region.memory_class = dataOnInternalDrm->regions[i].region.memory_class; - dataTranslated->regions[i].region.memory_instance = dataOnInternalDrm->regions[i].region.memory_instance; - dataTranslated->regions[i].probed_size = dataOnInternalDrm->regions[i].probed_size; - dataTranslated->regions[i].unallocated_size = dataOnInternalDrm->regions[i].unallocated_size; - } - length = lengthTranslated; - return dataQueryTranslated; -} - -} // namespace NEO diff --git a/shared/source/os_interface/linux/local/dg1/enable_local_memory_helper_dg1.cpp b/shared/source/os_interface/linux/local/dg1/enable_local_memory_helper_dg1.cpp deleted file mode 100644 index cc5efd9619..0000000000 --- a/shared/source/os_interface/linux/local/dg1/enable_local_memory_helper_dg1.cpp +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#include "shared/source/os_interface/linux/local_memory_helper.h" - -namespace NEO { - -static EnableProductLocalMemoryHelper enableLocalMemHelperDG1; - -} // namespace NEO diff --git a/shared/source/os_interface/linux/local/dg1/local_memory_helper_dg1.cpp b/shared/source/os_interface/linux/local/dg1/local_memory_helper_dg1.cpp deleted file mode 100644 index 7770d24154..0000000000 --- a/shared/source/os_interface/linux/local/dg1/local_memory_helper_dg1.cpp +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#include "shared/source/debug_settings/debug_settings_manager.h" -#include "shared/source/os_interface/linux/local_memory_helper.h" - -#include "third_party/uapi/dg1/drm/i915_drm.h" - -namespace NEO { -constexpr static auto gfxProduct = IGFX_DG1; - -extern uint32_t createGemExtMemoryRegions(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle); -extern bool isQueryDrmTip(uint8_t *dataQuery, int32_t length); -extern std::unique_ptr translateToDrmTip(uint8_t *dataQuery, int32_t &length); - -template <> -uint32_t LocalMemoryHelperImpl::createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) { - printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "Performing GEM_CREATE_EXT with { size: %lu", allocSize); - - if (DebugManager.flags.PrintBOCreateDestroyResult.get()) { - for (uint32_t i = 0; i < dataSize; i++) { - auto region = reinterpret_cast(data)[i]; - printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, ", memory class: %d, memory instance: %d", - region.memory_class, region.memory_instance); - } - printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "%s", " }\n"); - } - - if (createGemExtMemoryRegions(drm, data, dataSize, allocSize, handle) == 0) { - printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "GEM_CREATE_EXT with EXT_MEMORY_REGIONS has returned: %d BO-%u with size: %lu\n", 0, handle, allocSize); - return 0; - } - handle = 0u; - - drm_i915_gem_object_param regionParam{}; - regionParam.size = dataSize; - regionParam.data = reinterpret_cast(data); - regionParam.param = I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS; - - drm_i915_gem_create_ext_setparam setparamRegion{}; - setparamRegion.base.name = I915_GEM_CREATE_EXT_SETPARAM; - setparamRegion.param = regionParam; - - drm_i915_gem_create_ext createExt{}; - createExt.size = allocSize; - createExt.extensions = reinterpret_cast(&setparamRegion); - - auto ret = LocalMemoryHelper::ioctl(drm, DRM_IOCTL_I915_GEM_CREATE_EXT, &createExt); - - handle = createExt.handle; - printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "GEM_CREATE_EXT with EXT_SETPARAM has returned: %d BO-%u with size: %lu\n", ret, createExt.handle, createExt.size); - return ret; -} - -template <> -std::unique_ptr LocalMemoryHelperImpl::translateIfRequired(uint8_t *dataQuery, int32_t length) { - if (isQueryDrmTip(dataQuery, length)) { - return std::unique_ptr(dataQuery); - } - auto data = std::unique_ptr(dataQuery); - return translateToDrmTip(data.get(), length); -} - -} // namespace NEO diff --git a/shared/source/os_interface/linux/local/xe_hp_sdv/CMakeLists.txt b/shared/source/os_interface/linux/local/xe_hp_sdv/CMakeLists.txt deleted file mode 100644 index ed0e62483a..0000000000 --- a/shared/source/os_interface/linux/local/xe_hp_sdv/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (C) 2021 Intel Corporation -# -# SPDX-License-Identifier: MIT -# - -if(SUPPORT_XE_HP_SDV AND "${BRANCH_TYPE}" STREQUAL "") - set(NEO_CORE_OS_INTERFACE_LINUX_LOCAL_XE_HP_SDV - ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt - ${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper_xe_hp_sdv.cpp - ) - set(CORE_SRCS_LINK_LINUX_LOCAL_XE_HP_SDV - ${CMAKE_CURRENT_SOURCE_DIR}/enable_local_memory_helper_xe_hp_sdv.cpp - ) - set_property(GLOBAL APPEND PROPERTY NEO_CORE_OS_INTERFACE_LINUX ${NEO_CORE_OS_INTERFACE_LINUX_LOCAL_XE_HP_SDV}) - set_property(GLOBAL APPEND PROPERTY NEO_CORE_SRCS_LINK ${CORE_SRCS_LINK_LINUX_LOCAL_XE_HP_SDV}) -endif() diff --git a/shared/source/os_interface/linux/local/xe_hp_sdv/enable_local_memory_helper_xe_hp_sdv.cpp b/shared/source/os_interface/linux/local/xe_hp_sdv/enable_local_memory_helper_xe_hp_sdv.cpp deleted file mode 100644 index aa25c5d6e6..0000000000 --- a/shared/source/os_interface/linux/local/xe_hp_sdv/enable_local_memory_helper_xe_hp_sdv.cpp +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#include "shared/source/os_interface/linux/local_memory_helper.h" - -namespace NEO { - -static EnableProductLocalMemoryHelper enableLocalMemHelperXeHpSdv; - -} // namespace NEO diff --git a/shared/source/os_interface/linux/local/xe_hp_sdv/local_memory_helper_xe_hp_sdv.cpp b/shared/source/os_interface/linux/local/xe_hp_sdv/local_memory_helper_xe_hp_sdv.cpp deleted file mode 100644 index 8e4ef4f55b..0000000000 --- a/shared/source/os_interface/linux/local/xe_hp_sdv/local_memory_helper_xe_hp_sdv.cpp +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#include "shared/source/debug_settings/debug_settings_manager.h" -#include "shared/source/os_interface/linux/local_memory_helper.h" - -#include "third_party/uapi/xe_hp_sdv/drm/i915_drm.h" - -namespace NEO { -constexpr static auto gfxProduct = IGFX_XE_HP_SDV; - -template <> -uint32_t LocalMemoryHelperImpl::createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) { - drm_i915_gem_create_ext_memory_regions memRegions; - memRegions.num_regions = dataSize; - memRegions.regions = reinterpret_cast(data); - memRegions.base.name = I915_GEM_CREATE_EXT_MEMORY_REGIONS; - - drm_i915_gem_create_ext createExt{}; - createExt.size = allocSize; - createExt.extensions = reinterpret_cast(&memRegions); - - printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "Performing GEM_CREATE_EXT with { size: %lu", - allocSize); - - if (DebugManager.flags.PrintBOCreateDestroyResult.get()) { - for (uint32_t i = 0; i < dataSize; i++) { - auto region = reinterpret_cast(data)[i]; - printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, ", memory class: %d, memory instance: %d", - region.memory_class, region.memory_instance); - } - printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "%s", " }\n"); - } - - auto ret = ioctl(drm, DRM_IOCTL_I915_GEM_CREATE_EXT, &createExt); - - printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "GEM_CREATE_EXT with EXT_MEMORY_REGIONS has returned: %d BO-%u with size: %lu\n", ret, createExt.handle, createExt.size); - handle = createExt.handle; - return ret; -} - -template <> -std::unique_ptr LocalMemoryHelperImpl::translateIfRequired(uint8_t *dataQuery, int32_t length) { - return std::unique_ptr(dataQuery); -} - -template class LocalMemoryHelperImpl; - -} // namespace NEO diff --git a/shared/source/os_interface/linux/local_memory_helper.cpp b/shared/source/os_interface/linux/local_memory_helper.cpp deleted file mode 100644 index 7a6e1f09a6..0000000000 --- a/shared/source/os_interface/linux/local_memory_helper.cpp +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#include "shared/source/os_interface/linux/local_memory_helper.h" - -#include "shared/source/os_interface/linux/drm_neo.h" - -namespace NEO { - -LocalMemoryHelper *localMemoryHelperFactory[IGFX_MAX_PRODUCT] = {}; - -uint32_t LocalMemoryHelper::ioctl(Drm *drm, unsigned long request, void *arg) { - return drm->ioctl(request, arg); -} - -} // namespace NEO diff --git a/shared/source/os_interface/linux/local_memory_helper.h b/shared/source/os_interface/linux/local_memory_helper.h deleted file mode 100644 index 67dd7847f4..0000000000 --- a/shared/source/os_interface/linux/local_memory_helper.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2021 Intel Corporation - * - * SPDX-License-Identifier: MIT - * - */ - -#pragma once -#include "igfxfmid.h" - -#include -#include -#include - -struct drm_i915_gem_create_ext; -struct drm_i915_gem_memory_class_instance; - -namespace NEO { -class Drm; -class LocalMemoryHelper; - -extern LocalMemoryHelper *localMemoryHelperFactory[IGFX_MAX_PRODUCT]; - -class LocalMemoryHelper { - public: - static LocalMemoryHelper *get(PRODUCT_FAMILY product) { - auto localMemHelper = localMemoryHelperFactory[product]; - if (!localMemHelper) { - return localMemoryHelperFactory[IGFX_DG1]; - } - return localMemHelper; - } - static uint32_t ioctl(Drm *drm, unsigned long request, void *arg); - virtual uint32_t createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) = 0; - virtual std::unique_ptr translateIfRequired(uint8_t *dataQuery, int32_t length) = 0; -}; - -template -class LocalMemoryHelperImpl : public LocalMemoryHelper { - public: - static LocalMemoryHelper *get() { - static LocalMemoryHelperImpl instance; - return &instance; - } - uint32_t createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) override; - std::unique_ptr translateIfRequired(uint8_t *dataQuery, int32_t length); -}; - -template -struct EnableProductLocalMemoryHelper { - EnableProductLocalMemoryHelper() { - LocalMemoryHelper *plocalMemHelper = LocalMemoryHelperImpl::get(); - localMemoryHelperFactory[gfxProduct] = plocalMemHelper; - } -}; -} // namespace NEO diff --git a/shared/source/os_interface/linux/memory_info_impl.cpp b/shared/source/os_interface/linux/memory_info_impl.cpp index c92c998c3c..1da88abab5 100644 --- a/shared/source/os_interface/linux/memory_info_impl.cpp +++ b/shared/source/os_interface/linux/memory_info_impl.cpp @@ -7,11 +7,15 @@ #include "shared/source/os_interface/linux/memory_info_impl.h" -#include "shared/source/helpers/hw_info.h" -#include "shared/source/os_interface/linux/local_memory_helper.h" +#include "shared/source/helpers/basic_math.h" +#include "shared/source/helpers/debug_helpers.h" +#include "shared/source/os_interface/linux/drm_neo.h" #include "drm/i915_drm.h" +#include +#include + namespace NEO { MemoryInfoImpl::MemoryInfoImpl(const drm_i915_memory_region_info *regionInfo, size_t count) @@ -24,8 +28,40 @@ MemoryInfoImpl::MemoryInfoImpl(const drm_i915_memory_region_info *regionInfo, si } uint32_t MemoryInfoImpl::createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) { - auto pHwInfo = drm->getRootDeviceEnvironment().getHardwareInfo(); - return LocalMemoryHelper::get(pHwInfo->platform.eProductFamily)->createGemExt(drm, data, dataSize, allocSize, handle); + printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "Performing GEM_CREATE_EXT with { size: %lu", allocSize); + + if (DebugManager.flags.PrintBOCreateDestroyResult.get()) { + for (uint32_t i = 0; i < dataSize; i++) { + auto region = reinterpret_cast(data)[i]; + printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, ", memory class: %d, memory instance: %d", + region.memory_class, region.memory_instance); + } + printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "%s", " }\n"); + } + + if (createGemExtMemoryRegions(drm, data, dataSize, allocSize, handle) == 0) { + printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "GEM_CREATE_EXT with EXT_MEMORY_REGIONS has returned: %d BO-%u with size: %lu\n", 0, handle, allocSize); + return 0; + } + + drm_i915_gem_object_param regionParam{}; + regionParam.size = dataSize; + regionParam.data = reinterpret_cast(data); + regionParam.param = I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS; + + drm_i915_gem_create_ext_setparam setparamRegion{}; + setparamRegion.base.name = I915_GEM_CREATE_EXT_SETPARAM; + setparamRegion.param = regionParam; + + drm_i915_gem_create_ext createExt{}; + createExt.size = allocSize; + createExt.extensions = reinterpret_cast(&setparamRegion); + + auto ret = drm->ioctl(DRM_IOCTL_I915_GEM_CREATE_EXT, &createExt); + + printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "GEM_CREATE_EXT with EXT_SETPARAM has returned: %d BO-%u with size: %lu\n", ret, createExt.handle, createExt.size); + handle = createExt.handle; + return ret; } void MemoryInfoImpl::assignRegionsFromDistances(const void *distanceInfosPtr, size_t size) { diff --git a/shared/source/os_interface/linux/memory_info_impl.h b/shared/source/os_interface/linux/memory_info_impl.h index 60ae69e2df..893feb5692 100644 --- a/shared/source/os_interface/linux/memory_info_impl.h +++ b/shared/source/os_interface/linux/memory_info_impl.h @@ -31,6 +31,7 @@ class MemoryInfoImpl : public MemoryInfo { void assignRegionsFromDistances(const void *distanceInfosPtr, size_t size); uint32_t createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) override; + uint32_t createGemExtMemoryRegions(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle); drm_i915_gem_memory_class_instance getMemoryRegionClassAndInstance(uint32_t memoryBank, const HardwareInfo &hwInfo) { auto &hwHelper = HwHelper::get(hwInfo.platform.eRenderCoreFamily); diff --git a/shared/test/common/libult/CMakeLists.txt b/shared/test/common/libult/CMakeLists.txt index b2cec64935..253c0a6979 100644 --- a/shared/test/common/libult/CMakeLists.txt +++ b/shared/test/common/libult/CMakeLists.txt @@ -13,10 +13,6 @@ macro(macro_for_each_platform) if(EXISTS ${SRC_FILE}) list(APPEND igdrcl_libult_common_SRCS_ENABLE_TESTED_HW ${SRC_FILE}) endif() - set(SRC_FILE ${NEO_SHARED_DIRECTORY}/os_interface/linux/local${BRANCH_DIR_SUFFIX}${PLATFORM_IT_LOWER}/enable_local_memory_helper_${PLATFORM_IT_LOWER}.cpp) - if(EXISTS ${SRC_FILE}) - list(APPEND igdrcl_libult_common_SRCS_ENABLE_TESTED_HW ${SRC_FILE}) - endif() set(SRC_FILE ${NEO_SHARED_DIRECTORY}/ail${BRANCH_DIR}${GEN_TYPE_LOWER}${BRANCH}${PLATFORM_IT_LOWER}/ail_configuration_${PLATFORM_IT_LOWER}.cpp) if(EXISTS ${SRC_FILE}) list(APPEND igdrcl_libult_common_SRCS_ENABLE_TESTED_HW ${SRC_FILE}) diff --git a/third_party/uapi/drm_tip/drm/drm.h b/third_party/uapi/drm_tip/drm.h similarity index 100% rename from third_party/uapi/drm_tip/drm/drm.h rename to third_party/uapi/drm_tip/drm.h diff --git a/third_party/uapi/drm_tip/drm/drm_fourcc.h b/third_party/uapi/drm_tip/drm_fourcc.h similarity index 99% rename from third_party/uapi/drm_tip/drm/drm_fourcc.h rename to third_party/uapi/drm_tip/drm_fourcc.h index d195dd9480..45a914850b 100644 --- a/third_party/uapi/drm_tip/drm/drm_fourcc.h +++ b/third_party/uapi/drm_tip/drm_fourcc.h @@ -24,7 +24,6 @@ #ifndef DRM_FOURCC_H #define DRM_FOURCC_H -#define __user #include "drm.h" #if defined(__cplusplus) diff --git a/third_party/uapi/drm_tip/drm/drm_mode.h b/third_party/uapi/drm_tip/drm_mode.h similarity index 100% rename from third_party/uapi/drm_tip/drm/drm_mode.h rename to third_party/uapi/drm_tip/drm_mode.h diff --git a/third_party/uapi/drm_tip/drm/i915_drm.h b/third_party/uapi/drm_tip/i915_drm.h similarity index 100% rename from third_party/uapi/drm_tip/drm/i915_drm.h rename to third_party/uapi/drm_tip/i915_drm.h diff --git a/third_party/uapi/xe_hp_sdv/drm/drm.h b/third_party/uapi/xe_hp_sdv/drm/drm.h deleted file mode 100644 index 3b810b53ba..0000000000 --- a/third_party/uapi/xe_hp_sdv/drm/drm.h +++ /dev/null @@ -1,1201 +0,0 @@ -/* - * Header for the Direct Rendering Manager - * - * Author: Rickard E. (Rik) Faith - * - * Acknowledgments: - * Dec 1999, Richard Henderson , move to generic cmpxchg. - */ - -/* - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DRM_H_ -#define _DRM_H_ - -#if defined(__KERNEL__) - -#include -#include -typedef unsigned int drm_handle_t; - -#elif defined(__linux__) - -#include -#include -typedef unsigned int drm_handle_t; - -#else /* One of the BSDs */ - -#include -#include -#include -typedef int8_t __s8; -typedef uint8_t __u8; -typedef int16_t __s16; -typedef uint16_t __u16; -typedef int32_t __s32; -typedef uint32_t __u32; -typedef int64_t __s64; -typedef uint64_t __u64; -typedef size_t __kernel_size_t; -typedef unsigned long drm_handle_t; - -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ -#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ -#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ -#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ - -#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ -#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ -#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) -#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) -#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) - -typedef unsigned int drm_context_t; -typedef unsigned int drm_drawable_t; -typedef unsigned int drm_magic_t; - -/* - * Cliprect. - * - * \warning: If you change this structure, make sure you change - * XF86DRIClipRectRec in the server as well - * - * \note KW: Actually it's illegal to change either for - * backwards-compatibility reasons. - */ -struct drm_clip_rect { - unsigned short x1; - unsigned short y1; - unsigned short x2; - unsigned short y2; -}; - -/* - * Drawable information. - */ -struct drm_drawable_info { - unsigned int num_rects; - struct drm_clip_rect *rects; -}; - -/* - * Texture region, - */ -struct drm_tex_region { - unsigned char next; - unsigned char prev; - unsigned char in_use; - unsigned char padding; - unsigned int age; -}; - -/* - * Hardware lock. - * - * The lock structure is a simple cache-line aligned integer. To avoid - * processor bus contention on a multiprocessor system, there should not be any - * other data stored in the same cache line. - */ -struct drm_hw_lock { - __volatile__ unsigned int lock; /**< lock variable */ - char padding[60]; /**< Pad to cache line */ -}; - -/* - * DRM_IOCTL_VERSION ioctl argument type. - * - * \sa drmGetVersion(). - */ -struct drm_version { - int version_major; /**< Major version */ - int version_minor; /**< Minor version */ - int version_patchlevel; /**< Patch level */ - __kernel_size_t name_len; /**< Length of name buffer */ - char __user *name; /**< Name of driver */ - __kernel_size_t date_len; /**< Length of date buffer */ - char __user *date; /**< User-space buffer to hold date */ - __kernel_size_t desc_len; /**< Length of desc buffer */ - char __user *desc; /**< User-space buffer to hold desc */ -}; - -/* - * DRM_IOCTL_GET_UNIQUE ioctl argument type. - * - * \sa drmGetBusid() and drmSetBusId(). - */ -struct drm_unique { - __kernel_size_t unique_len; /**< Length of unique */ - char __user *unique; /**< Unique name for driver instantiation */ -}; - -struct drm_list { - int count; /**< Length of user-space structures */ - struct drm_version __user *version; -}; - -struct drm_block { - int unused; -}; - -/* - * DRM_IOCTL_CONTROL ioctl argument type. - * - * \sa drmCtlInstHandler() and drmCtlUninstHandler(). - */ -struct drm_control { - enum { - DRM_ADD_COMMAND, - DRM_RM_COMMAND, - DRM_INST_HANDLER, - DRM_UNINST_HANDLER - } func; - int irq; -}; - -/* - * Type of memory to map. - */ -enum drm_map_type { - _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ - _DRM_REGISTERS = 1, /**< no caching, no core dump */ - _DRM_SHM = 2, /**< shared, cached */ - _DRM_AGP = 3, /**< AGP/GART */ - _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ - _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ -}; - -/* - * Memory mapping flags. - */ -enum drm_map_flags { - _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ - _DRM_READ_ONLY = 0x02, - _DRM_LOCKED = 0x04, /**< shared, cached, locked */ - _DRM_KERNEL = 0x08, /**< kernel requires access */ - _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ - _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ - _DRM_REMOVABLE = 0x40, /**< Removable mapping */ - _DRM_DRIVER = 0x80 /**< Managed by driver */ -}; - -struct drm_ctx_priv_map { - unsigned int ctx_id; /**< Context requesting private mapping */ - void *handle; /**< Handle of map */ -}; - -/* - * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls - * argument type. - * - * \sa drmAddMap(). - */ -struct drm_map { - unsigned long offset; /**< Requested physical address (0 for SAREA)*/ - unsigned long size; /**< Requested physical size (bytes) */ - enum drm_map_type type; /**< Type of memory to map */ - enum drm_map_flags flags; /**< Flags */ - void *handle; /**< User-space: "Handle" to pass to mmap() */ - /**< Kernel-space: kernel-virtual address */ - int mtrr; /**< MTRR slot used */ - /* Private data */ -}; - -/* - * DRM_IOCTL_GET_CLIENT ioctl argument type. - */ -struct drm_client { - int idx; /**< Which client desired? */ - int auth; /**< Is client authenticated? */ - unsigned long pid; /**< Process ID */ - unsigned long uid; /**< User ID */ - unsigned long magic; /**< Magic */ - unsigned long iocs; /**< Ioctl count */ -}; - -enum drm_stat_type { - _DRM_STAT_LOCK, - _DRM_STAT_OPENS, - _DRM_STAT_CLOSES, - _DRM_STAT_IOCTLS, - _DRM_STAT_LOCKS, - _DRM_STAT_UNLOCKS, - _DRM_STAT_VALUE, /**< Generic value */ - _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ - _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ - - _DRM_STAT_IRQ, /**< IRQ */ - _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ - _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ - _DRM_STAT_DMA, /**< DMA */ - _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ - _DRM_STAT_MISSED /**< Missed DMA opportunity */ - /* Add to the *END* of the list */ -}; - -/* - * DRM_IOCTL_GET_STATS ioctl argument type. - */ -struct drm_stats { - unsigned long count; - struct { - unsigned long value; - enum drm_stat_type type; - } data[15]; -}; - -/* - * Hardware locking flags. - */ -enum drm_lock_flags { - _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ - _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ - _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ - _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ - /* These *HALT* flags aren't supported yet - -- they will be used to support the - full-screen DGA-like mode. */ - _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ - _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ -}; - -/* - * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. - * - * \sa drmGetLock() and drmUnlock(). - */ -struct drm_lock { - int context; - enum drm_lock_flags flags; -}; - -/* - * DMA flags - * - * \warning - * These values \e must match xf86drm.h. - * - * \sa drm_dma. - */ -enum drm_dma_flags { - /* Flags for DMA buffer dispatch */ - _DRM_DMA_BLOCK = 0x01, /**< - * Block until buffer dispatched. - * - * \note The buffer may not yet have - * been processed by the hardware -- - * getting a hardware lock with the - * hardware quiescent will ensure - * that the buffer has been - * processed. - */ - _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ - _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ - - /* Flags for DMA buffer request */ - _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ - _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ - _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ -}; - -/* - * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. - * - * \sa drmAddBufs(). - */ -struct drm_buf_desc { - int count; /**< Number of buffers of this size */ - int size; /**< Size in bytes */ - int low_mark; /**< Low water mark */ - int high_mark; /**< High water mark */ - enum { - _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ - _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ - _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ - _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ - _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ - } flags; - unsigned long agp_start; /**< - * Start address of where the AGP buffers are - * in the AGP aperture - */ -}; - -/* - * DRM_IOCTL_INFO_BUFS ioctl argument type. - */ -struct drm_buf_info { - int count; /**< Entries in list */ - struct drm_buf_desc __user *list; -}; - -/* - * DRM_IOCTL_FREE_BUFS ioctl argument type. - */ -struct drm_buf_free { - int count; - int __user *list; -}; - -/* - * Buffer information - * - * \sa drm_buf_map. - */ -struct drm_buf_pub { - int idx; /**< Index into the master buffer list */ - int total; /**< Buffer size */ - int used; /**< Amount of buffer in use (for DMA) */ - void __user *address; /**< Address of buffer */ -}; - -/* - * DRM_IOCTL_MAP_BUFS ioctl argument type. - */ -struct drm_buf_map { - int count; /**< Length of the buffer list */ -#ifdef __cplusplus - void __user *virt; -#else - void __user *virtual; /**< Mmap'd area in user-virtual */ -#endif - struct drm_buf_pub __user *list; /**< Buffer information */ -}; - -/* - * DRM_IOCTL_DMA ioctl argument type. - * - * Indices here refer to the offset into the buffer list in drm_buf_get. - * - * \sa drmDMA(). - */ -struct drm_dma { - int context; /**< Context handle */ - int send_count; /**< Number of buffers to send */ - int __user *send_indices; /**< List of handles to buffers */ - int __user *send_sizes; /**< Lengths of data to send */ - enum drm_dma_flags flags; /**< Flags */ - int request_count; /**< Number of buffers requested */ - int request_size; /**< Desired size for buffers */ - int __user *request_indices; /**< Buffer information */ - int __user *request_sizes; - int granted_count; /**< Number of buffers granted */ -}; - -enum drm_ctx_flags { - _DRM_CONTEXT_PRESERVED = 0x01, - _DRM_CONTEXT_2DONLY = 0x02 -}; - -/* - * DRM_IOCTL_ADD_CTX ioctl argument type. - * - * \sa drmCreateContext() and drmDestroyContext(). - */ -struct drm_ctx { - drm_context_t handle; - enum drm_ctx_flags flags; -}; - -/* - * DRM_IOCTL_RES_CTX ioctl argument type. - */ -struct drm_ctx_res { - int count; - struct drm_ctx __user *contexts; -}; - -/* - * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. - */ -struct drm_draw { - drm_drawable_t handle; -}; - -/* - * DRM_IOCTL_UPDATE_DRAW ioctl argument type. - */ -typedef enum { - DRM_DRAWABLE_CLIPRECTS -} drm_drawable_info_type_t; - -struct drm_update_draw { - drm_drawable_t handle; - unsigned int type; - unsigned int num; - unsigned long long data; -}; - -/* - * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. - */ -struct drm_auth { - drm_magic_t magic; -}; - -/* - * DRM_IOCTL_IRQ_BUSID ioctl argument type. - * - * \sa drmGetInterruptFromBusID(). - */ -struct drm_irq_busid { - int irq; /**< IRQ number */ - int busnum; /**< bus number */ - int devnum; /**< device number */ - int funcnum; /**< function number */ -}; - -enum drm_vblank_seq_type { - _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ - _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ - /* bits 1-6 are reserved for high crtcs */ - _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, - _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ - _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ - _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ - _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ - _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ -}; -#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 - -#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) -#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ - _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) - -struct drm_wait_vblank_request { - enum drm_vblank_seq_type type; - unsigned int sequence; - unsigned long signal; -}; - -struct drm_wait_vblank_reply { - enum drm_vblank_seq_type type; - unsigned int sequence; - long tval_sec; - long tval_usec; -}; - -/* - * DRM_IOCTL_WAIT_VBLANK ioctl argument type. - * - * \sa drmWaitVBlank(). - */ -union drm_wait_vblank { - struct drm_wait_vblank_request request; - struct drm_wait_vblank_reply reply; -}; - -#define _DRM_PRE_MODESET 1 -#define _DRM_POST_MODESET 2 - -/* - * DRM_IOCTL_MODESET_CTL ioctl argument type - * - * \sa drmModesetCtl(). - */ -struct drm_modeset_ctl { - __u32 crtc; - __u32 cmd; -}; - -/* - * DRM_IOCTL_AGP_ENABLE ioctl argument type. - * - * \sa drmAgpEnable(). - */ -struct drm_agp_mode { - unsigned long mode; /**< AGP mode */ -}; - -/* - * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. - * - * \sa drmAgpAlloc() and drmAgpFree(). - */ -struct drm_agp_buffer { - unsigned long size; /**< In bytes -- will round to page boundary */ - unsigned long handle; /**< Used for binding / unbinding */ - unsigned long type; /**< Type of memory to allocate */ - unsigned long physical; /**< Physical used by i810 */ -}; - -/* - * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. - * - * \sa drmAgpBind() and drmAgpUnbind(). - */ -struct drm_agp_binding { - unsigned long handle; /**< From drm_agp_buffer */ - unsigned long offset; /**< In bytes -- will round to page boundary */ -}; - -/* - * DRM_IOCTL_AGP_INFO ioctl argument type. - * - * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), - * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), - * drmAgpVendorId() and drmAgpDeviceId(). - */ -struct drm_agp_info { - int agp_version_major; - int agp_version_minor; - unsigned long mode; - unsigned long aperture_base; /* physical address */ - unsigned long aperture_size; /* bytes */ - unsigned long memory_allowed; /* bytes */ - unsigned long memory_used; - - /* PCI information */ - unsigned short id_vendor; - unsigned short id_device; -}; - -/* - * DRM_IOCTL_SG_ALLOC ioctl argument type. - */ -struct drm_scatter_gather { - unsigned long size; /**< In bytes -- will round to page boundary */ - unsigned long handle; /**< Used for mapping / unmapping */ -}; - -/* - * DRM_IOCTL_SET_VERSION ioctl argument type. - */ -struct drm_set_version { - int drm_di_major; - int drm_di_minor; - int drm_dd_major; - int drm_dd_minor; -}; - -/* DRM_IOCTL_GEM_CLOSE ioctl argument type */ -struct drm_gem_close { - /** Handle of the object to be closed. */ - __u32 handle; - __u32 pad; -}; - -/* DRM_IOCTL_GEM_FLINK ioctl argument type */ -struct drm_gem_flink { - /** Handle for the object being named */ - __u32 handle; - - /** Returned global name */ - __u32 name; -}; - -/* DRM_IOCTL_GEM_OPEN ioctl argument type */ -struct drm_gem_open { - /** Name of object being opened */ - __u32 name; - - /** Returned handle for the object */ - __u32 handle; - - /** Returned size of the object */ - __u64 size; -}; - -/** - * DRM_CAP_DUMB_BUFFER - * - * If set to 1, the driver supports creating dumb buffers via the - * &DRM_IOCTL_MODE_CREATE_DUMB ioctl. - */ -#define DRM_CAP_DUMB_BUFFER 0x1 -/** - * DRM_CAP_VBLANK_HIGH_CRTC - * - * If set to 1, the kernel supports specifying a :ref:`CRTC index` - * in the high bits of &drm_wait_vblank_request.type. - * - * Starting kernel version 2.6.39, this capability is always set to 1. - */ -#define DRM_CAP_VBLANK_HIGH_CRTC 0x2 -/** - * DRM_CAP_DUMB_PREFERRED_DEPTH - * - * The preferred bit depth for dumb buffers. - * - * The bit depth is the number of bits used to indicate the color of a single - * pixel excluding any padding. This is different from the number of bits per - * pixel. For instance, XRGB8888 has a bit depth of 24 but has 32 bits per - * pixel. - * - * Note that this preference only applies to dumb buffers, it's irrelevant for - * other types of buffers. - */ -#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 -/** - * DRM_CAP_DUMB_PREFER_SHADOW - * - * If set to 1, the driver prefers userspace to render to a shadow buffer - * instead of directly rendering to a dumb buffer. For best speed, userspace - * should do streaming ordered memory copies into the dumb buffer and never - * read from it. - * - * Note that this preference only applies to dumb buffers, it's irrelevant for - * other types of buffers. - */ -#define DRM_CAP_DUMB_PREFER_SHADOW 0x4 -/** - * DRM_CAP_PRIME - * - * Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT - * and &DRM_PRIME_CAP_EXPORT. - * - * PRIME buffers are exposed as dma-buf file descriptors. See - * Documentation/gpu/drm-mm.rst, section "PRIME Buffer Sharing". - */ -#define DRM_CAP_PRIME 0x5 -/** - * DRM_PRIME_CAP_IMPORT - * - * If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME - * buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl. - */ -#define DRM_PRIME_CAP_IMPORT 0x1 -/** - * DRM_PRIME_CAP_EXPORT - * - * If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME - * buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl. - */ -#define DRM_PRIME_CAP_EXPORT 0x2 -/** - * DRM_CAP_TIMESTAMP_MONOTONIC - * - * If set to 0, the kernel will report timestamps with ``CLOCK_REALTIME`` in - * struct drm_event_vblank. If set to 1, the kernel will report timestamps with - * ``CLOCK_MONOTONIC``. See ``clock_gettime(2)`` for the definition of these - * clocks. - * - * Starting from kernel version 2.6.39, the default value for this capability - * is 1. Starting kernel version 4.15, this capability is always set to 1. - */ -#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 -/** - * DRM_CAP_ASYNC_PAGE_FLIP - * - * If set to 1, the driver supports &DRM_MODE_PAGE_FLIP_ASYNC. - */ -#define DRM_CAP_ASYNC_PAGE_FLIP 0x7 -/** - * DRM_CAP_CURSOR_WIDTH - * - * The ``CURSOR_WIDTH`` and ``CURSOR_HEIGHT`` capabilities return a valid - * width x height combination for the hardware cursor. The intention is that a - * hardware agnostic userspace can query a cursor plane size to use. - * - * Note that the cross-driver contract is to merely return a valid size; - * drivers are free to attach another meaning on top, eg. i915 returns the - * maximum plane size. - */ -#define DRM_CAP_CURSOR_WIDTH 0x8 -/** - * DRM_CAP_CURSOR_HEIGHT - * - * See &DRM_CAP_CURSOR_WIDTH. - */ -#define DRM_CAP_CURSOR_HEIGHT 0x9 -/** - * DRM_CAP_ADDFB2_MODIFIERS - * - * If set to 1, the driver supports supplying modifiers in the - * &DRM_IOCTL_MODE_ADDFB2 ioctl. - */ -#define DRM_CAP_ADDFB2_MODIFIERS 0x10 -/** - * DRM_CAP_PAGE_FLIP_TARGET - * - * If set to 1, the driver supports the &DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE and - * &DRM_MODE_PAGE_FLIP_TARGET_RELATIVE flags in - * &drm_mode_crtc_page_flip_target.flags for the &DRM_IOCTL_MODE_PAGE_FLIP - * ioctl. - */ -#define DRM_CAP_PAGE_FLIP_TARGET 0x11 -/** - * DRM_CAP_CRTC_IN_VBLANK_EVENT - * - * If set to 1, the kernel supports reporting the CRTC ID in - * &drm_event_vblank.crtc_id for the &DRM_EVENT_VBLANK and - * &DRM_EVENT_FLIP_COMPLETE events. - * - * Starting kernel version 4.12, this capability is always set to 1. - */ -#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 -/** - * DRM_CAP_SYNCOBJ - * - * If set to 1, the driver supports sync objects. See - * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects". - */ -#define DRM_CAP_SYNCOBJ 0x13 -/** - * DRM_CAP_SYNCOBJ_TIMELINE - * - * If set to 1, the driver supports timeline operations on sync objects. See - * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects". - */ -#define DRM_CAP_SYNCOBJ_TIMELINE 0x14 - -/* DRM_IOCTL_GET_CAP ioctl argument type */ -struct drm_get_cap { - __u64 capability; - __u64 value; -}; - -/** - * DRM_CLIENT_CAP_STEREO_3D - * - * If set to 1, the DRM core will expose the stereo 3D capabilities of the - * monitor by advertising the supported 3D layouts in the flags of struct - * drm_mode_modeinfo. See ``DRM_MODE_FLAG_3D_*``. - * - * This capability is always supported for all drivers starting from kernel - * version 3.13. - */ -#define DRM_CLIENT_CAP_STEREO_3D 1 - -/** - * DRM_CLIENT_CAP_UNIVERSAL_PLANES - * - * If set to 1, the DRM core will expose all planes (overlay, primary, and - * cursor) to userspace. - * - * This capability has been introduced in kernel version 3.15. Starting from - * kernel version 3.17, this capability is always supported for all drivers. - */ -#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 - -/** - * DRM_CLIENT_CAP_ATOMIC - * - * If set to 1, the DRM core will expose atomic properties to userspace. This - * implicitly enables &DRM_CLIENT_CAP_UNIVERSAL_PLANES and - * &DRM_CLIENT_CAP_ASPECT_RATIO. - * - * If the driver doesn't support atomic mode-setting, enabling this capability - * will fail with -EOPNOTSUPP. - * - * This capability has been introduced in kernel version 4.0. Starting from - * kernel version 4.2, this capability is always supported for atomic-capable - * drivers. - */ -#define DRM_CLIENT_CAP_ATOMIC 3 - -/** - * DRM_CLIENT_CAP_ASPECT_RATIO - * - * If set to 1, the DRM core will provide aspect ratio information in modes. - * See ``DRM_MODE_FLAG_PIC_AR_*``. - * - * This capability is always supported for all drivers starting from kernel - * version 4.18. - */ -#define DRM_CLIENT_CAP_ASPECT_RATIO 4 - -/** - * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS - * - * If set to 1, the DRM core will expose special connectors to be used for - * writing back to memory the scene setup in the commit. The client must enable - * &DRM_CLIENT_CAP_ATOMIC first. - * - * This capability is always supported for atomic-capable drivers starting from - * kernel version 4.19. - */ -#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 - -/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ -struct drm_set_client_cap { - __u64 capability; - __u64 value; -}; - -#define DRM_RDWR O_RDWR -#define DRM_CLOEXEC O_CLOEXEC -struct drm_prime_handle { - __u32 handle; - - /** Flags.. only applicable for handle->fd */ - __u32 flags; - - /** Returned dmabuf file descriptor */ - __s32 fd; -}; - -struct drm_syncobj_create { - __u32 handle; -#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0) - __u32 flags; -}; - -struct drm_syncobj_destroy { - __u32 handle; - __u32 pad; -}; - -#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0) -#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0) -struct drm_syncobj_handle { - __u32 handle; - __u32 flags; - - __s32 fd; - __u32 pad; -}; - -struct drm_syncobj_transfer { - __u32 src_handle; - __u32 dst_handle; - __u64 src_point; - __u64 dst_point; - __u32 flags; - __u32 pad; -}; - -#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) -#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) -#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */ -struct drm_syncobj_wait { - __u64 handles; - /* absolute timeout */ - __s64 timeout_nsec; - __u32 count_handles; - __u32 flags; - __u32 first_signaled; /* only valid when not waiting all */ - __u32 pad; -}; - -struct drm_syncobj_timeline_wait { - __u64 handles; - /* wait on specific timeline point for every handles*/ - __u64 points; - /* absolute timeout */ - __s64 timeout_nsec; - __u32 count_handles; - __u32 flags; - __u32 first_signaled; /* only valid when not waiting all */ - __u32 pad; -}; - - -struct drm_syncobj_array { - __u64 handles; - __u32 count_handles; - __u32 pad; -}; - -#define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */ -struct drm_syncobj_timeline_array { - __u64 handles; - __u64 points; - __u32 count_handles; - __u32 flags; -}; - - -/* Query current scanout sequence number */ -struct drm_crtc_get_sequence { - __u32 crtc_id; /* requested crtc_id */ - __u32 active; /* return: crtc output is active */ - __u64 sequence; /* return: most recent vblank sequence */ - __s64 sequence_ns; /* return: most recent time of first pixel out */ -}; - -/* Queue event to be delivered at specified sequence. Time stamp marks - * when the first pixel of the refresh cycle leaves the display engine - * for the display - */ -#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ -#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ - -struct drm_crtc_queue_sequence { - __u32 crtc_id; - __u32 flags; - __u64 sequence; /* on input, target sequence. on output, actual sequence */ - __u64 user_data; /* user data passed to event */ -}; - -#if defined(__cplusplus) -} -#endif - -#include "drm_mode.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define DRM_IOCTL_BASE 'd' -#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) -#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) -#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) -#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) - -#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) -#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) -#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) -#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) -#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) -#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) -#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) -#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) -#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) -#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) -#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) -#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) -#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) -#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) - -#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) -#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) -#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) -#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) -#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) -#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) -#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) -#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) -#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) -#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) -#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) - -#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) - -#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) -#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) - -#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) -#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) - -#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) -#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) -#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) -#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) -#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) -#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) -#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) -#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) -#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) -#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) -#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) -#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) -#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) - -#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) -#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) - -#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) -#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) -#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) -#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) -#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) -#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) -#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) -#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) - -#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) -#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) - -#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) - -#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) -#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) - -#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) - -#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) -#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) -#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) -#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) -#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) -#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) -#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) -#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) -#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ -#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ - -#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) -#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) -#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) -#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) -#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) -/** - * DRM_IOCTL_MODE_RMFB - Remove a framebuffer. - * - * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL - * argument is a framebuffer object ID. - * - * Warning: removing a framebuffer currently in-use on an enabled plane will - * disable that plane. The CRTC the plane is linked to may also be disabled - * (depending on driver capabilities). - */ -#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) -#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) -#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) - -#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) -#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) -#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) -#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) -#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) -#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) -#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) -#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) -#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) -#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) -#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) -#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) -#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) - -#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create) -#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) -#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) -#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) -#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) -#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) -#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) - -#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) -#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) -#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) -#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) - -#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait) -#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array) -#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) -#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) - -#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2) - -/* - * Device specific ioctls should only be in their respective headers - * The device specific ioctl range is from 0x40 to 0x9f. - * Generic IOCTLS restart at 0xA0. - * - * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and - * drmCommandReadWrite(). - */ -#define DRM_COMMAND_BASE 0x40 -#define DRM_COMMAND_END 0xA0 - -/* - * Header for events written back to userspace on the drm fd. The - * type defines the type of event, the length specifies the total - * length of the event (including the header), and user_data is - * typically a 64 bit value passed with the ioctl that triggered the - * event. A read on the drm fd will always only return complete - * events, that is, if for example the read buffer is 100 bytes, and - * there are two 64 byte events pending, only one will be returned. - * - * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and - * up are chipset specific. - */ -struct drm_event { - __u32 type; - __u32 length; -}; - -#define DRM_EVENT_VBLANK 0x01 -#define DRM_EVENT_FLIP_COMPLETE 0x02 -#define DRM_EVENT_CRTC_SEQUENCE 0x03 - -struct drm_event_vblank { - struct drm_event base; - __u64 user_data; - __u32 tv_sec; - __u32 tv_usec; - __u32 sequence; - __u32 crtc_id; /* 0 on older kernels that do not support this */ -}; - -/* Event delivered at sequence. Time stamp marks when the first pixel - * of the refresh cycle leaves the display engine for the display - */ -struct drm_event_crtc_sequence { - struct drm_event base; - __u64 user_data; - __s64 time_ns; - __u64 sequence; -}; - -/* typedef area */ -#ifndef __KERNEL__ -typedef struct drm_clip_rect drm_clip_rect_t; -typedef struct drm_drawable_info drm_drawable_info_t; -typedef struct drm_tex_region drm_tex_region_t; -typedef struct drm_hw_lock drm_hw_lock_t; -typedef struct drm_version drm_version_t; -typedef struct drm_unique drm_unique_t; -typedef struct drm_list drm_list_t; -typedef struct drm_block drm_block_t; -typedef struct drm_control drm_control_t; -typedef enum drm_map_type drm_map_type_t; -typedef enum drm_map_flags drm_map_flags_t; -typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; -typedef struct drm_map drm_map_t; -typedef struct drm_client drm_client_t; -typedef enum drm_stat_type drm_stat_type_t; -typedef struct drm_stats drm_stats_t; -typedef enum drm_lock_flags drm_lock_flags_t; -typedef struct drm_lock drm_lock_t; -typedef enum drm_dma_flags drm_dma_flags_t; -typedef struct drm_buf_desc drm_buf_desc_t; -typedef struct drm_buf_info drm_buf_info_t; -typedef struct drm_buf_free drm_buf_free_t; -typedef struct drm_buf_pub drm_buf_pub_t; -typedef struct drm_buf_map drm_buf_map_t; -typedef struct drm_dma drm_dma_t; -typedef union drm_wait_vblank drm_wait_vblank_t; -typedef struct drm_agp_mode drm_agp_mode_t; -typedef enum drm_ctx_flags drm_ctx_flags_t; -typedef struct drm_ctx drm_ctx_t; -typedef struct drm_ctx_res drm_ctx_res_t; -typedef struct drm_draw drm_draw_t; -typedef struct drm_update_draw drm_update_draw_t; -typedef struct drm_auth drm_auth_t; -typedef struct drm_irq_busid drm_irq_busid_t; -typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; - -typedef struct drm_agp_buffer drm_agp_buffer_t; -typedef struct drm_agp_binding drm_agp_binding_t; -typedef struct drm_agp_info drm_agp_info_t; -typedef struct drm_scatter_gather drm_scatter_gather_t; -typedef struct drm_set_version drm_set_version_t; -#endif - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/third_party/uapi/xe_hp_sdv/drm/drm_fourcc.h b/third_party/uapi/xe_hp_sdv/drm/drm_fourcc.h deleted file mode 100644 index 17dc3a817b..0000000000 --- a/third_party/uapi/xe_hp_sdv/drm/drm_fourcc.h +++ /dev/null @@ -1,836 +0,0 @@ -/* - * Copyright 2011 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef DRM_FOURCC_H -#define DRM_FOURCC_H - -#define __user -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** - * DOC: overview - * - * In the DRM subsystem, framebuffer pixel formats are described using the - * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the - * fourcc code, a Format Modifier may optionally be provided, in order to - * further describe the buffer's format - for example tiling or compression. - * - * Format Modifiers - * ---------------- - * - * Format modifiers are used in conjunction with a fourcc code, forming a - * unique fourcc:modifier pair. This format:modifier pair must fully define the - * format and data layout of the buffer, and should be the only way to describe - * that particular buffer. - * - * Having multiple fourcc:modifier pairs which describe the same layout should - * be avoided, as such aliases run the risk of different drivers exposing - * different names for the same data format, forcing userspace to understand - * that they are aliases. - * - * Format modifiers may change any property of the buffer, including the number - * of planes and/or the required allocation size. Format modifiers are - * vendor-namespaced, and as such the relationship between a fourcc code and a - * modifier is specific to the modifer being used. For example, some modifiers - * may preserve meaning - such as number of planes - from the fourcc code, - * whereas others may not. - * - * Vendors should document their modifier usage in as much detail as - * possible, to ensure maximum compatibility across devices, drivers and - * applications. - * - * The authoritative list of format modifier codes is found in - * `include/uapi/drm/drm_fourcc.h` - */ - -#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ - ((__u32)(c) << 16) | ((__u32)(d) << 24)) - -#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ - -/* Reserve 0 for the invalid format specifier */ -#define DRM_FORMAT_INVALID 0 - -/* color index */ -#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ - -/* 8 bpp Red */ -#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ - -/* 16 bpp Red */ -#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ - -/* 16 bpp RG */ -#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ -#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ - -/* 32 bpp RG */ -#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ -#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ - -/* 8 bpp RGB */ -#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ -#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ - -/* 16 bpp RGB */ -#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ -#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ -#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ -#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ - -#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ -#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ -#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ -#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ - -#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ -#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ -#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ -#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ - -#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ -#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ -#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ -#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ - -#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ -#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ - -/* 24 bpp RGB */ -#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ -#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ - -/* 32 bpp RGB */ -#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ -#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ -#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ -#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ - -#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ -#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ -#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ -#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ - -#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ -#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ -#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ -#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ - -#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ -#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ -#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ -#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ - -/* - * Floating point 64bpp RGB - * IEEE 754-2008 binary16 half-precision float - * [15:0] sign:exponent:mantissa 1:5:10 - */ -#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ -#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ - -#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ -#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ - -/* packed YCbCr */ -#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ -#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ -#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ -#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ - -#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ -#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ -#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ -#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ - -/* - * packed Y2xx indicate for each component, xx valid data occupy msb - * 16-xx padding occupy lsb - */ -#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ -#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ -#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ - -/* - * packed Y4xx indicate for each component, xx valid data occupy msb - * 16-xx padding occupy lsb except Y410 - */ -#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ -#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ -#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ - -#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ -#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ -#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ - -/* - * packed YCbCr420 2x2 tiled formats - * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile - */ -/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ -#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') -/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ -#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') - -/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ -#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') -/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ -#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') - -/* - * 1-plane YUV 4:2:0 - * In these formats, the component ordering is specified (Y, followed by U - * then V), but the exact Linear layout is undefined. - * These formats can only be used with a non-Linear modifier. - */ -#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') -#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') - -/* - * 2 plane RGB + A - * index 0 = RGB plane, same format as the corresponding non _A8 format has - * index 1 = A plane, [7:0] A - */ -#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') -#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') -#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') -#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') -#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') -#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') -#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') -#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') - -/* - * 2 plane YCbCr - * index 0 = Y plane, [7:0] Y - * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian - * or - * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian - */ -#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ -#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ -#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ -#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ -#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ -#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ - -/* - * 2 plane YCbCr MSB aligned - * index 0 = Y plane, [15:0] Y:x [10:6] little endian - * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian - */ -#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ - -/* - * 2 plane YCbCr MSB aligned - * index 0 = Y plane, [15:0] Y:x [10:6] little endian - * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian - */ -#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ - -/* - * 2 plane YCbCr MSB aligned - * index 0 = Y plane, [15:0] Y:x [12:4] little endian - * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian - */ -#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ - -/* - * 2 plane YCbCr MSB aligned - * index 0 = Y plane, [15:0] Y little endian - * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian - */ -#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ - -/* - * 3 plane YCbCr - * index 0: Y plane, [7:0] Y - * index 1: Cb plane, [7:0] Cb - * index 2: Cr plane, [7:0] Cr - * or - * index 1: Cr plane, [7:0] Cr - * index 2: Cb plane, [7:0] Cb - */ -#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ -#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ -#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ -#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ -#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ -#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ -#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ -#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ -#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ -#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ - - -/* - * Format Modifiers: - * - * Format modifiers describe, typically, a re-ordering or modification - * of the data in a plane of an FB. This can be used to express tiled/ - * swizzled formats, or compression, or a combination of the two. - * - * The upper 8 bits of the format modifier are a vendor-id as assigned - * below. The lower 56 bits are assigned as vendor sees fit. - */ - -/* Vendor Ids: */ -#define DRM_FORMAT_MOD_NONE 0 -#define DRM_FORMAT_MOD_VENDOR_NONE 0 -#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 -#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 -#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 -#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 -#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 -#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 -#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 -#define DRM_FORMAT_MOD_VENDOR_ARM 0x08 -#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 - -/* add more to the end as needed */ - -#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) - -#define fourcc_mod_code(vendor, val) \ - ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) - -/* - * Format Modifier tokens: - * - * When adding a new token please document the layout with a code comment, - * similar to the fourcc codes above. drm_fourcc.h is considered the - * authoritative source for all of these. - */ - -/* - * Invalid Modifier - * - * This modifier can be used as a sentinel to terminate the format modifiers - * list, or to initialize a variable with an invalid modifier. It might also be - * used to report an error back to userspace for certain APIs. - */ -#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) - -/* - * Linear Layout - * - * Just plain linear layout. Note that this is different from no specifying any - * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), - * which tells the driver to also take driver-internal information into account - * and so might actually result in a tiled framebuffer. - */ -#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) - -/* Intel framebuffer modifiers */ - -/* - * Intel X-tiling layout - * - * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) - * in row-major layout. Within the tile bytes are laid out row-major, with - * a platform-dependent stride. On top of that the memory can apply - * platform-depending swizzling of some higher address bits into bit6. - * - * This format is highly platforms specific and not useful for cross-driver - * sharing. It exists since on a given platform it does uniquely identify the - * layout in a simple way for i915-specific userspace. - */ -#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) - -/* - * Intel Y-tiling layout - * - * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) - * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) - * chunks column-major, with a platform-dependent height. On top of that the - * memory can apply platform-depending swizzling of some higher address bits - * into bit6. - * - * This format is highly platforms specific and not useful for cross-driver - * sharing. It exists since on a given platform it does uniquely identify the - * layout in a simple way for i915-specific userspace. - */ -#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) - -/* - * Intel Yf-tiling layout - * - * This is a tiled layout using 4Kb tiles in row-major layout. - * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which - * are arranged in four groups (two wide, two high) with column-major layout. - * Each group therefore consits out of four 256 byte units, which are also laid - * out as 2x2 column-major. - * 256 byte units are made out of four 64 byte blocks of pixels, producing - * either a square block or a 2:1 unit. - * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width - * in pixel depends on the pixel depth. - */ -#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) - -/* - * Intel color control surface (CCS) for render compression - * - * The framebuffer format must be one of the 8:8:8:8 RGB formats. - * The main surface will be plane index 0 and must be Y/Yf-tiled, - * the CCS will be plane index 1. - * - * Each CCS tile matches a 1024x512 pixel area of the main surface. - * To match certain aspects of the 3D hardware the CCS is - * considered to be made up of normal 128Bx32 Y tiles, Thus - * the CCS pitch must be specified in multiples of 128 bytes. - * - * In reality the CCS tile appears to be a 64Bx64 Y tile, composed - * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. - * But that fact is not relevant unless the memory is accessed - * directly. - */ -#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) -#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) - -/* - * Intel color control surfaces (CCS) for Gen-12 render compression. - * - * The main surface is Y-tiled and at plane index 0, the CCS is linear and - * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in - * main surface. In other words, 4 bits in CCS map to a main surface cache - * line pair. The main surface pitch is required to be a multiple of four - * Y-tile widths. - */ -#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) - -/* - * Intel color control surfaces (CCS) for Gen-12 media compression - * - * The main surface is Y-tiled and at plane index 0, the CCS is linear and - * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in - * main surface. In other words, 4 bits in CCS map to a main surface cache - * line pair. The main surface pitch is required to be a multiple of four - * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the - * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, - * planes 2 and 3 for the respective CCS. - */ -#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) - -/* ID #8 is reserved for TGL CCS_CC */ - -/* - * Intel color control surfaces (CCS) for DG1 render compression. - * - * The layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, but since - * DG1 may have a different hashing/compression algorithm, the actual contents - * of compressed buffers may not be safely shareable between TGL and DG1, hence - * the new modifier assignment. - */ -#define I915_FORMAT_MOD_Y_TILED_DG1_RC_CCS fourcc_mod_code(INTEL, 9) - -/* - * Intel color control surfaces (CCS) for Gen-12 media compression - * - * The layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, but since - * DG1 may have a different hashing/compression algorithm, the actual contents - * of compressed buffers may not be safely shareable between TGL and DG1, hence - * the new modifier assignment. - */ -#define I915_FORMAT_MOD_Y_TILED_DG1_MC_CCS fourcc_mod_code(INTEL, 10) - -/* ID #11 is reserved for DG1 CCS_CC */ - -/* - * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks - * - * Macroblocks are laid in a Z-shape, and each pixel data is following the - * standard NV12 style. - * As for NV12, an image is the result of two frame buffers: one for Y, - * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). - * Alignment requirements are (for each buffer): - * - multiple of 128 pixels for the width - * - multiple of 32 pixels for the height - * - * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html - */ -#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) - -/* - * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks - * - * This is a simple tiled layout using tiles of 16x16 pixels in a row-major - * layout. For YCbCr formats Cb/Cr components are taken in such a way that - * they correspond to their 16x16 luma block. - */ -#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) - -/* - * Qualcomm Compressed Format - * - * Refers to a compressed variant of the base format that is compressed. - * Implementation may be platform and base-format specific. - * - * Each macrotile consists of m x n (mostly 4 x 4) tiles. - * Pixel data pitch/stride is aligned with macrotile width. - * Pixel data height is aligned with macrotile height. - * Entire pixel data buffer is aligned with 4k(bytes). - */ -#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) - -/* Vivante framebuffer modifiers */ - -/* - * Vivante 4x4 tiling layout - * - * This is a simple tiled layout using tiles of 4x4 pixels in a row-major - * layout. - */ -#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) - -/* - * Vivante 64x64 super-tiling layout - * - * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile - * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- - * major layout. - * - * For more information: see - * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling - */ -#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) - -/* - * Vivante 4x4 tiling layout for dual-pipe - * - * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a - * different base address. Offsets from the base addresses are therefore halved - * compared to the non-split tiled layout. - */ -#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) - -/* - * Vivante 64x64 super-tiling layout for dual-pipe - * - * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile - * starts at a different base address. Offsets from the base addresses are - * therefore halved compared to the non-split super-tiled layout. - */ -#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) - -/* NVIDIA frame buffer modifiers */ - -/* - * Tegra Tiled Layout, used by Tegra 2, 3 and 4. - * - * Pixels are arranged in simple tiles of 16 x 16 bytes. - */ -#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) - -/* - * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later - * - * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked - * vertically by a power of 2 (1 to 32 GOBs) to form a block. - * - * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. - * - * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. - * Valid values are: - * - * 0 == ONE_GOB - * 1 == TWO_GOBS - * 2 == FOUR_GOBS - * 3 == EIGHT_GOBS - * 4 == SIXTEEN_GOBS - * 5 == THIRTYTWO_GOBS - * - * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format - * in full detail. - */ -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ - fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) - -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ - fourcc_mod_code(NVIDIA, 0x10) -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ - fourcc_mod_code(NVIDIA, 0x11) -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ - fourcc_mod_code(NVIDIA, 0x12) -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ - fourcc_mod_code(NVIDIA, 0x13) -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ - fourcc_mod_code(NVIDIA, 0x14) -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ - fourcc_mod_code(NVIDIA, 0x15) - -/* - * Some Broadcom modifiers take parameters, for example the number of - * vertical lines in the image. Reserve the lower 32 bits for modifier - * type, and the next 24 bits for parameters. Top 8 bits are the - * vendor code. - */ -#define __fourcc_mod_broadcom_param_shift 8 -#define __fourcc_mod_broadcom_param_bits 48 -#define fourcc_mod_broadcom_code(val, params) \ - fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) -#define fourcc_mod_broadcom_param(m) \ - ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ - ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) -#define fourcc_mod_broadcom_mod(m) \ - ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ - __fourcc_mod_broadcom_param_shift)) - -/* - * Broadcom VC4 "T" format - * - * This is the primary layout that the V3D GPU can texture from (it - * can't do linear). The T format has: - * - * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 - * pixels at 32 bit depth. - * - * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually - * 16x16 pixels). - * - * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On - * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows - * they're (TR, BR, BL, TL), where bottom left is start of memory. - * - * - an image made of 4k tiles in rows either left-to-right (even rows of 4k - * tiles) or right-to-left (odd rows of 4k tiles). - */ -#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) - -/* - * Broadcom SAND format - * - * This is the native format that the H.264 codec block uses. For VC4 - * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. - * - * The image can be considered to be split into columns, and the - * columns are placed consecutively into memory. The width of those - * columns can be either 32, 64, 128, or 256 pixels, but in practice - * only 128 pixel columns are used. - * - * The pitch between the start of each column is set to optimally - * switch between SDRAM banks. This is passed as the number of lines - * of column width in the modifier (we can't use the stride value due - * to various core checks that look at it , so you should set the - * stride to width*cpp). - * - * Note that the column height for this format modifier is the same - * for all of the planes, assuming that each column contains both Y - * and UV. Some SAND-using hardware stores UV in a separate tiled - * image from Y to reduce the column height, which is not supported - * with these modifiers. - */ - -#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ - fourcc_mod_broadcom_code(2, v) -#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ - fourcc_mod_broadcom_code(3, v) -#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ - fourcc_mod_broadcom_code(4, v) -#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ - fourcc_mod_broadcom_code(5, v) - -#define DRM_FORMAT_MOD_BROADCOM_SAND32 \ - DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) -#define DRM_FORMAT_MOD_BROADCOM_SAND64 \ - DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) -#define DRM_FORMAT_MOD_BROADCOM_SAND128 \ - DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) -#define DRM_FORMAT_MOD_BROADCOM_SAND256 \ - DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) - -/* Broadcom UIF format - * - * This is the common format for the current Broadcom multimedia - * blocks, including V3D 3.x and newer, newer video codecs, and - * displays. - * - * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), - * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are - * stored in columns, with padding between the columns to ensure that - * moving from one column to the next doesn't hit the same SDRAM page - * bank. - * - * To calculate the padding, it is assumed that each hardware block - * and the software driving it knows the platform's SDRAM page size, - * number of banks, and XOR address, and that it's identical between - * all blocks using the format. This tiling modifier will use XOR as - * necessary to reduce the padding. If a hardware block can't do XOR, - * the assumption is that a no-XOR tiling modifier will be created. - */ -#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) - -/* - * Arm Framebuffer Compression (AFBC) modifiers - * - * AFBC is a proprietary lossless image compression protocol and format. - * It provides fine-grained random access and minimizes the amount of data - * transferred between IP blocks. - * - * AFBC has several features which may be supported and/or used, which are - * represented using bits in the modifier. Not all combinations are valid, - * and different devices or use-cases may support different combinations. - * - * Further information on the use of AFBC modifiers can be found in - * Documentation/gpu/afbc.rst - */ - -/* - * The top 4 bits (out of the 56 bits alloted for specifying vendor specific - * modifiers) denote the category for modifiers. Currently we have only two - * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen - * different categories. - */ -#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ - fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) - -#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 -#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 - -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ - DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) - -/* - * AFBC superblock size - * - * Indicates the superblock size(s) used for the AFBC buffer. The buffer - * size (in pixels) must be aligned to a multiple of the superblock size. - * Four lowest significant bits(LSBs) are reserved for block size. - * - * Where one superblock size is specified, it applies to all planes of the - * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, - * the first applies to the Luma plane and the second applies to the Chroma - * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). - * Multiple superblock sizes are only valid for multi-plane YCbCr formats. - */ -#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf -#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) -#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) -#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) -#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) - -/* - * AFBC lossless colorspace transform - * - * Indicates that the buffer makes use of the AFBC lossless colorspace - * transform. - */ -#define AFBC_FORMAT_MOD_YTR (1ULL << 4) - -/* - * AFBC block-split - * - * Indicates that the payload of each superblock is split. The second - * half of the payload is positioned at a predefined offset from the start - * of the superblock payload. - */ -#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) - -/* - * AFBC sparse layout - * - * This flag indicates that the payload of each superblock must be stored at a - * predefined position relative to the other superblocks in the same AFBC - * buffer. This order is the same order used by the header buffer. In this mode - * each superblock is given the same amount of space as an uncompressed - * superblock of the particular format would require, rounding up to the next - * multiple of 128 bytes in size. - */ -#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) - -/* - * AFBC copy-block restrict - * - * Buffers with this flag must obey the copy-block restriction. The restriction - * is such that there are no copy-blocks referring across the border of 8x8 - * blocks. For the subsampled data the 8x8 limitation is also subsampled. - */ -#define AFBC_FORMAT_MOD_CBR (1ULL << 7) - -/* - * AFBC tiled layout - * - * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all - * superblocks inside a tile are stored together in memory. 8x8 tiles are used - * for pixel formats up to and including 32 bpp while 4x4 tiles are used for - * larger bpp formats. The order between the tiles is scan line. - * When the tiled layout is used, the buffer size (in pixels) must be aligned - * to the tile size. - */ -#define AFBC_FORMAT_MOD_TILED (1ULL << 8) - -/* - * AFBC solid color blocks - * - * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth - * can be reduced if a whole superblock is a single color. - */ -#define AFBC_FORMAT_MOD_SC (1ULL << 9) - -/* - * AFBC double-buffer - * - * Indicates that the buffer is allocated in a layout safe for front-buffer - * rendering. - */ -#define AFBC_FORMAT_MOD_DB (1ULL << 10) - -/* - * AFBC buffer content hints - * - * Indicates that the buffer includes per-superblock content hints. - */ -#define AFBC_FORMAT_MOD_BCH (1ULL << 11) - -/* - * Arm 16x16 Block U-Interleaved modifier - * - * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image - * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels - * in the block are reordered. - */ -#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ - DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) - -/* - * Allwinner tiled modifier - * - * This tiling mode is implemented by the VPU found on all Allwinner platforms, - * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 - * planes. - * - * With this tiling, the luminance samples are disposed in tiles representing - * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. - * The pixel order in each tile is linear and the tiles are disposed linearly, - * both in row-major order. - */ -#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) - -#if defined(__cplusplus) -} -#endif - -#endif /* DRM_FOURCC_H */ diff --git a/third_party/uapi/xe_hp_sdv/drm/drm_mode.h b/third_party/uapi/xe_hp_sdv/drm/drm_mode.h deleted file mode 100644 index 735c8cfdaa..0000000000 --- a/third_party/uapi/xe_hp_sdv/drm/drm_mode.h +++ /dev/null @@ -1,1032 +0,0 @@ -/* - * Copyright (c) 2007 Dave Airlie - * Copyright (c) 2007 Jakob Bornecrantz - * Copyright (c) 2008 Red Hat Inc. - * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA - * Copyright (c) 2007-2008 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef _DRM_MODE_H -#define _DRM_MODE_H - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** - * DOC: overview - * - * DRM exposes many UAPI and structure definition to have a consistent - * and standardized interface with user. - * Userspace can refer to these structure definitions and UAPI formats - * to communicate to driver - */ - -#define DRM_CONNECTOR_NAME_LEN 32 -#define DRM_DISPLAY_MODE_LEN 32 -#define DRM_PROP_NAME_LEN 32 - -#define DRM_MODE_TYPE_BUILTIN (1<<0) /* deprecated */ -#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) /* deprecated */ -#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) /* deprecated */ -#define DRM_MODE_TYPE_PREFERRED (1<<3) -#define DRM_MODE_TYPE_DEFAULT (1<<4) /* deprecated */ -#define DRM_MODE_TYPE_USERDEF (1<<5) -#define DRM_MODE_TYPE_DRIVER (1<<6) - -#define DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | \ - DRM_MODE_TYPE_USERDEF | \ - DRM_MODE_TYPE_DRIVER) - -/* Video mode flags */ -/* bit compatible with the xrandr RR_ definitions (bits 0-13) - * - * ABI warning: Existing userspace really expects - * the mode flags to match the xrandr definitions. Any - * changes that don't match the xrandr definitions will - * likely need a new client cap or some other mechanism - * to avoid breaking existing userspace. This includes - * allocating new flags in the previously unused bits! - */ -#define DRM_MODE_FLAG_PHSYNC (1<<0) -#define DRM_MODE_FLAG_NHSYNC (1<<1) -#define DRM_MODE_FLAG_PVSYNC (1<<2) -#define DRM_MODE_FLAG_NVSYNC (1<<3) -#define DRM_MODE_FLAG_INTERLACE (1<<4) -#define DRM_MODE_FLAG_DBLSCAN (1<<5) -#define DRM_MODE_FLAG_CSYNC (1<<6) -#define DRM_MODE_FLAG_PCSYNC (1<<7) -#define DRM_MODE_FLAG_NCSYNC (1<<8) -#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ -#define DRM_MODE_FLAG_BCAST (1<<10) /* deprecated */ -#define DRM_MODE_FLAG_PIXMUX (1<<11) /* deprecated */ -#define DRM_MODE_FLAG_DBLCLK (1<<12) -#define DRM_MODE_FLAG_CLKDIV2 (1<<13) - /* - * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX - * (define not exposed to user space). - */ -#define DRM_MODE_FLAG_3D_MASK (0x1f<<14) -#define DRM_MODE_FLAG_3D_NONE (0<<14) -#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14) -#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14) -#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14) -#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14) -#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14) -#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14) -#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) -#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) - -/* Picture aspect ratio options */ -#define DRM_MODE_PICTURE_ASPECT_NONE 0 -#define DRM_MODE_PICTURE_ASPECT_4_3 1 -#define DRM_MODE_PICTURE_ASPECT_16_9 2 -#define DRM_MODE_PICTURE_ASPECT_64_27 3 -#define DRM_MODE_PICTURE_ASPECT_256_135 4 - -/* Content type options */ -#define DRM_MODE_CONTENT_TYPE_NO_DATA 0 -#define DRM_MODE_CONTENT_TYPE_GRAPHICS 1 -#define DRM_MODE_CONTENT_TYPE_PHOTO 2 -#define DRM_MODE_CONTENT_TYPE_CINEMA 3 -#define DRM_MODE_CONTENT_TYPE_GAME 4 - -/* Aspect ratio flag bitmask (4 bits 22:19) */ -#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19) -#define DRM_MODE_FLAG_PIC_AR_NONE \ - (DRM_MODE_PICTURE_ASPECT_NONE<<19) -#define DRM_MODE_FLAG_PIC_AR_4_3 \ - (DRM_MODE_PICTURE_ASPECT_4_3<<19) -#define DRM_MODE_FLAG_PIC_AR_16_9 \ - (DRM_MODE_PICTURE_ASPECT_16_9<<19) -#define DRM_MODE_FLAG_PIC_AR_64_27 \ - (DRM_MODE_PICTURE_ASPECT_64_27<<19) -#define DRM_MODE_FLAG_PIC_AR_256_135 \ - (DRM_MODE_PICTURE_ASPECT_256_135<<19) - -#define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | \ - DRM_MODE_FLAG_NHSYNC | \ - DRM_MODE_FLAG_PVSYNC | \ - DRM_MODE_FLAG_NVSYNC | \ - DRM_MODE_FLAG_INTERLACE | \ - DRM_MODE_FLAG_DBLSCAN | \ - DRM_MODE_FLAG_CSYNC | \ - DRM_MODE_FLAG_PCSYNC | \ - DRM_MODE_FLAG_NCSYNC | \ - DRM_MODE_FLAG_HSKEW | \ - DRM_MODE_FLAG_DBLCLK | \ - DRM_MODE_FLAG_CLKDIV2 | \ - DRM_MODE_FLAG_3D_MASK) - -/* DPMS flags */ -/* bit compatible with the xorg definitions. */ -#define DRM_MODE_DPMS_ON 0 -#define DRM_MODE_DPMS_STANDBY 1 -#define DRM_MODE_DPMS_SUSPEND 2 -#define DRM_MODE_DPMS_OFF 3 - -/* Scaling mode options */ -#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or - software can still scale) */ -#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ -#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ -#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ - -/* Dithering mode options */ -#define DRM_MODE_DITHERING_OFF 0 -#define DRM_MODE_DITHERING_ON 1 -#define DRM_MODE_DITHERING_AUTO 2 - -/* Dirty info options */ -#define DRM_MODE_DIRTY_OFF 0 -#define DRM_MODE_DIRTY_ON 1 -#define DRM_MODE_DIRTY_ANNOTATE 2 - -/* Link Status options */ -#define DRM_MODE_LINK_STATUS_GOOD 0 -#define DRM_MODE_LINK_STATUS_BAD 1 - -/* - * DRM_MODE_ROTATE_ - * - * Signals that a drm plane is been rotated degrees in counter - * clockwise direction. - * - * This define is provided as a convenience, looking up the property id - * using the name->prop id lookup is the preferred method. - */ -#define DRM_MODE_ROTATE_0 (1<<0) -#define DRM_MODE_ROTATE_90 (1<<1) -#define DRM_MODE_ROTATE_180 (1<<2) -#define DRM_MODE_ROTATE_270 (1<<3) - -/* - * DRM_MODE_ROTATE_MASK - * - * Bitmask used to look for drm plane rotations. - */ -#define DRM_MODE_ROTATE_MASK (\ - DRM_MODE_ROTATE_0 | \ - DRM_MODE_ROTATE_90 | \ - DRM_MODE_ROTATE_180 | \ - DRM_MODE_ROTATE_270) - -/* - * DRM_MODE_REFLECT_ - * - * Signals that the contents of a drm plane is reflected along the axis, - * in the same way as mirroring. - * See kerneldoc chapter "Plane Composition Properties" for more details. - * - * This define is provided as a convenience, looking up the property id - * using the name->prop id lookup is the preferred method. - */ -#define DRM_MODE_REFLECT_X (1<<4) -#define DRM_MODE_REFLECT_Y (1<<5) - -/* - * DRM_MODE_REFLECT_MASK - * - * Bitmask used to look for drm plane reflections. - */ -#define DRM_MODE_REFLECT_MASK (\ - DRM_MODE_REFLECT_X | \ - DRM_MODE_REFLECT_Y) - -/* Content Protection Flags */ -#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0 -#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1 -#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2 - -struct drm_mode_modeinfo { - __u32 clock; - __u16 hdisplay; - __u16 hsync_start; - __u16 hsync_end; - __u16 htotal; - __u16 hskew; - __u16 vdisplay; - __u16 vsync_start; - __u16 vsync_end; - __u16 vtotal; - __u16 vscan; - - __u32 vrefresh; - - __u32 flags; - __u32 type; - char name[DRM_DISPLAY_MODE_LEN]; -}; - -struct drm_mode_card_res { - __u64 fb_id_ptr; - __u64 crtc_id_ptr; - __u64 connector_id_ptr; - __u64 encoder_id_ptr; - __u32 count_fbs; - __u32 count_crtcs; - __u32 count_connectors; - __u32 count_encoders; - __u32 min_width; - __u32 max_width; - __u32 min_height; - __u32 max_height; -}; - -struct drm_mode_crtc { - __u64 set_connectors_ptr; - __u32 count_connectors; - - __u32 crtc_id; /**< Id */ - __u32 fb_id; /**< Id of framebuffer */ - - __u32 x; /**< x Position on the framebuffer */ - __u32 y; /**< y Position on the framebuffer */ - - __u32 gamma_size; - __u32 mode_valid; - struct drm_mode_modeinfo mode; -}; - -#define DRM_MODE_PRESENT_TOP_FIELD (1<<0) -#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) - -/* Planes blend with or override other bits on the CRTC */ -struct drm_mode_set_plane { - __u32 plane_id; - __u32 crtc_id; - __u32 fb_id; /* fb object contains surface format type */ - __u32 flags; /* see above flags */ - - /* Signed dest location allows it to be partially off screen */ - __s32 crtc_x; - __s32 crtc_y; - __u32 crtc_w; - __u32 crtc_h; - - /* Source values are 16.16 fixed point */ - __u32 src_x; - __u32 src_y; - __u32 src_h; - __u32 src_w; -}; - -struct drm_mode_get_plane { - __u32 plane_id; - - __u32 crtc_id; - __u32 fb_id; - - __u32 possible_crtcs; - __u32 gamma_size; - - __u32 count_format_types; - __u64 format_type_ptr; -}; - -struct drm_mode_get_plane_res { - __u64 plane_id_ptr; - __u32 count_planes; -}; - -#define DRM_MODE_ENCODER_NONE 0 -#define DRM_MODE_ENCODER_DAC 1 -#define DRM_MODE_ENCODER_TMDS 2 -#define DRM_MODE_ENCODER_LVDS 3 -#define DRM_MODE_ENCODER_TVDAC 4 -#define DRM_MODE_ENCODER_VIRTUAL 5 -#define DRM_MODE_ENCODER_DSI 6 -#define DRM_MODE_ENCODER_DPMST 7 -#define DRM_MODE_ENCODER_DPI 8 - -struct drm_mode_get_encoder { - __u32 encoder_id; - __u32 encoder_type; - - __u32 crtc_id; /**< Id of crtc */ - - __u32 possible_crtcs; - __u32 possible_clones; -}; - -/* This is for connectors with multiple signal types. */ -/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ -enum drm_mode_subconnector { - DRM_MODE_SUBCONNECTOR_Automatic = 0, - DRM_MODE_SUBCONNECTOR_Unknown = 0, - DRM_MODE_SUBCONNECTOR_DVID = 3, - DRM_MODE_SUBCONNECTOR_DVIA = 4, - DRM_MODE_SUBCONNECTOR_Composite = 5, - DRM_MODE_SUBCONNECTOR_SVIDEO = 6, - DRM_MODE_SUBCONNECTOR_Component = 8, - DRM_MODE_SUBCONNECTOR_SCART = 9, -}; - -#define DRM_MODE_CONNECTOR_Unknown 0 -#define DRM_MODE_CONNECTOR_VGA 1 -#define DRM_MODE_CONNECTOR_DVII 2 -#define DRM_MODE_CONNECTOR_DVID 3 -#define DRM_MODE_CONNECTOR_DVIA 4 -#define DRM_MODE_CONNECTOR_Composite 5 -#define DRM_MODE_CONNECTOR_SVIDEO 6 -#define DRM_MODE_CONNECTOR_LVDS 7 -#define DRM_MODE_CONNECTOR_Component 8 -#define DRM_MODE_CONNECTOR_9PinDIN 9 -#define DRM_MODE_CONNECTOR_DisplayPort 10 -#define DRM_MODE_CONNECTOR_HDMIA 11 -#define DRM_MODE_CONNECTOR_HDMIB 12 -#define DRM_MODE_CONNECTOR_TV 13 -#define DRM_MODE_CONNECTOR_eDP 14 -#define DRM_MODE_CONNECTOR_VIRTUAL 15 -#define DRM_MODE_CONNECTOR_DSI 16 -#define DRM_MODE_CONNECTOR_DPI 17 -#define DRM_MODE_CONNECTOR_WRITEBACK 18 -#define DRM_MODE_CONNECTOR_SPI 19 - -struct drm_mode_get_connector { - - __u64 encoders_ptr; - __u64 modes_ptr; - __u64 props_ptr; - __u64 prop_values_ptr; - - __u32 count_modes; - __u32 count_props; - __u32 count_encoders; - - __u32 encoder_id; /**< Current Encoder */ - __u32 connector_id; /**< Id */ - __u32 connector_type; - __u32 connector_type_id; - - __u32 connection; - __u32 mm_width; /**< width in millimeters */ - __u32 mm_height; /**< height in millimeters */ - __u32 subpixel; - - __u32 pad; -}; - -#define DRM_MODE_PROP_PENDING (1<<0) /* deprecated, do not use */ -#define DRM_MODE_PROP_RANGE (1<<1) -#define DRM_MODE_PROP_IMMUTABLE (1<<2) -#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ -#define DRM_MODE_PROP_BLOB (1<<4) -#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */ - -/* non-extended types: legacy bitmask, one bit per type: */ -#define DRM_MODE_PROP_LEGACY_TYPE ( \ - DRM_MODE_PROP_RANGE | \ - DRM_MODE_PROP_ENUM | \ - DRM_MODE_PROP_BLOB | \ - DRM_MODE_PROP_BITMASK) - -/* extended-types: rather than continue to consume a bit per type, - * grab a chunk of the bits to use as integer type id. - */ -#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0 -#define DRM_MODE_PROP_TYPE(n) ((n) << 6) -#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1) -#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2) - -/* the PROP_ATOMIC flag is used to hide properties from userspace that - * is not aware of atomic properties. This is mostly to work around - * older userspace (DDX drivers) that read/write each prop they find, - * witout being aware that this could be triggering a lengthy modeset. - */ -#define DRM_MODE_PROP_ATOMIC 0x80000000 - -struct drm_mode_property_enum { - __u64 value; - char name[DRM_PROP_NAME_LEN]; -}; - -struct drm_mode_get_property { - __u64 values_ptr; /* values and blob lengths */ - __u64 enum_blob_ptr; /* enum and blob id ptrs */ - - __u32 prop_id; - __u32 flags; - char name[DRM_PROP_NAME_LEN]; - - __u32 count_values; - /* This is only used to count enum values, not blobs. The _blobs is - * simply because of a historical reason, i.e. backwards compat. */ - __u32 count_enum_blobs; -}; - -struct drm_mode_connector_set_property { - __u64 value; - __u32 prop_id; - __u32 connector_id; -}; - -#define DRM_MODE_OBJECT_CRTC 0xcccccccc -#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0 -#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0 -#define DRM_MODE_OBJECT_MODE 0xdededede -#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0 -#define DRM_MODE_OBJECT_FB 0xfbfbfbfb -#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb -#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee -#define DRM_MODE_OBJECT_ANY 0 - -struct drm_mode_obj_get_properties { - __u64 props_ptr; - __u64 prop_values_ptr; - __u32 count_props; - __u32 obj_id; - __u32 obj_type; -}; - -struct drm_mode_obj_set_property { - __u64 value; - __u32 prop_id; - __u32 obj_id; - __u32 obj_type; -}; - -struct drm_mode_get_blob { - __u32 blob_id; - __u32 length; - __u64 data; -}; - -struct drm_mode_fb_cmd { - __u32 fb_id; - __u32 width; - __u32 height; - __u32 pitch; - __u32 bpp; - __u32 depth; - /* driver specific handle */ - __u32 handle; -}; - -#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ -#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */ - -struct drm_mode_fb_cmd2 { - __u32 fb_id; - __u32 width; - __u32 height; - __u32 pixel_format; /* fourcc code from drm_fourcc.h */ - __u32 flags; /* see above flags */ - - /* - * In case of planar formats, this ioctl allows up to 4 - * buffer objects with offsets and pitches per plane. - * The pitch and offset order is dictated by the fourcc, - * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: - * - * YUV 4:2:0 image with a plane of 8 bit Y samples - * followed by an interleaved U/V plane containing - * 8 bit 2x2 subsampled colour difference samples. - * - * So it would consist of Y as offsets[0] and UV as - * offsets[1]. Note that offsets[0] will generally - * be 0 (but this is not required). - * - * To accommodate tiled, compressed, etc formats, a - * modifier can be specified. The default value of zero - * indicates "native" format as specified by the fourcc. - * Vendor specific modifier token. Note that even though - * it looks like we have a modifier per-plane, we in fact - * do not. The modifier for each plane must be identical. - * Thus all combinations of different data layouts for - * multi plane formats must be enumerated as separate - * modifiers. - */ - __u32 handles[4]; - __u32 pitches[4]; /* pitch for each plane */ - __u32 offsets[4]; /* offset of each plane */ - __u64 modifier[4]; /* ie, tiling, compress */ -}; - -#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 -#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 -#define DRM_MODE_FB_DIRTY_FLAGS 0x03 - -#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256 - -/* - * Mark a region of a framebuffer as dirty. - * - * Some hardware does not automatically update display contents - * as a hardware or software draw to a framebuffer. This ioctl - * allows userspace to tell the kernel and the hardware what - * regions of the framebuffer have changed. - * - * The kernel or hardware is free to update more then just the - * region specified by the clip rects. The kernel or hardware - * may also delay and/or coalesce several calls to dirty into a - * single update. - * - * Userspace may annotate the updates, the annotates are a - * promise made by the caller that the change is either a copy - * of pixels or a fill of a single color in the region specified. - * - * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then - * the number of updated regions are half of num_clips given, - * where the clip rects are paired in src and dst. The width and - * height of each one of the pairs must match. - * - * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller - * promises that the region specified of the clip rects is filled - * completely with a single color as given in the color argument. - */ - -struct drm_mode_fb_dirty_cmd { - __u32 fb_id; - __u32 flags; - __u32 color; - __u32 num_clips; - __u64 clips_ptr; -}; - -struct drm_mode_mode_cmd { - __u32 connector_id; - struct drm_mode_modeinfo mode; -}; - -#define DRM_MODE_CURSOR_BO 0x01 -#define DRM_MODE_CURSOR_MOVE 0x02 -#define DRM_MODE_CURSOR_FLAGS 0x03 - -/* - * depending on the value in flags different members are used. - * - * CURSOR_BO uses - * crtc_id - * width - * height - * handle - if 0 turns the cursor off - * - * CURSOR_MOVE uses - * crtc_id - * x - * y - */ -struct drm_mode_cursor { - __u32 flags; - __u32 crtc_id; - __s32 x; - __s32 y; - __u32 width; - __u32 height; - /* driver specific handle */ - __u32 handle; -}; - -struct drm_mode_cursor2 { - __u32 flags; - __u32 crtc_id; - __s32 x; - __s32 y; - __u32 width; - __u32 height; - /* driver specific handle */ - __u32 handle; - __s32 hot_x; - __s32 hot_y; -}; - -struct drm_mode_crtc_lut { - __u32 crtc_id; - __u32 gamma_size; - - /* pointers to arrays */ - __u64 red; - __u64 green; - __u64 blue; -}; - -struct drm_color_ctm { - /* - * Conversion matrix in S31.32 sign-magnitude - * (not two's complement!) format. - */ - __u64 matrix[9]; -}; - -struct drm_color_lut { - /* - * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and - * 0xffff == 1.0. - */ - __u16 red; - __u16 green; - __u16 blue; - __u16 reserved; -}; - -/** - * struct hdr_metadata_infoframe - HDR Metadata Infoframe Data. - * - * HDR Metadata Infoframe as per CTA 861.G spec. This is expected - * to match exactly with the spec. - * - * Userspace is expected to pass the metadata information as per - * the format described in this structure. - */ -struct hdr_metadata_infoframe { - /** - * @eotf: Electro-Optical Transfer Function (EOTF) - * used in the stream. - */ - __u8 eotf; - /** - * @metadata_type: Static_Metadata_Descriptor_ID. - */ - __u8 metadata_type; - /** - * @display_primaries: Color Primaries of the Data. - * These are coded as unsigned 16-bit values in units of - * 0.00002, where 0x0000 represents zero and 0xC350 - * represents 1.0000. - * @display_primaries.x: X cordinate of color primary. - * @display_primaries.y: Y cordinate of color primary. - */ - struct { - __u16 x, y; - } display_primaries[3]; - /** - * @white_point: White Point of Colorspace Data. - * These are coded as unsigned 16-bit values in units of - * 0.00002, where 0x0000 represents zero and 0xC350 - * represents 1.0000. - * @white_point.x: X cordinate of whitepoint of color primary. - * @white_point.y: Y cordinate of whitepoint of color primary. - */ - struct { - __u16 x, y; - } white_point; - /** - * @max_display_mastering_luminance: Max Mastering Display Luminance. - * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, - * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. - */ - __u16 max_display_mastering_luminance; - /** - * @min_display_mastering_luminance: Min Mastering Display Luminance. - * This value is coded as an unsigned 16-bit value in units of - * 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF - * represents 6.5535 cd/m2. - */ - __u16 min_display_mastering_luminance; - /** - * @max_cll: Max Content Light Level. - * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, - * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. - */ - __u16 max_cll; - /** - * @max_fall: Max Frame Average Light Level. - * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, - * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. - */ - __u16 max_fall; -}; - -/** - * struct hdr_output_metadata - HDR output metadata - * - * Metadata Information to be passed from userspace - */ -struct hdr_output_metadata { - /** - * @metadata_type: Static_Metadata_Descriptor_ID. - */ - __u32 metadata_type; - /** - * @hdmi_metadata_type1: HDR Metadata Infoframe. - */ - union { - struct hdr_metadata_infoframe hdmi_metadata_type1; - }; -}; - -#define DRM_MODE_PAGE_FLIP_EVENT 0x01 -#define DRM_MODE_PAGE_FLIP_ASYNC 0x02 -#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 -#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8 -#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \ - DRM_MODE_PAGE_FLIP_TARGET_RELATIVE) -#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | \ - DRM_MODE_PAGE_FLIP_ASYNC | \ - DRM_MODE_PAGE_FLIP_TARGET) - -/* - * Request a page flip on the specified crtc. - * - * This ioctl will ask KMS to schedule a page flip for the specified - * crtc. Once any pending rendering targeting the specified fb (as of - * ioctl time) has completed, the crtc will be reprogrammed to display - * that fb after the next vertical refresh. The ioctl returns - * immediately, but subsequent rendering to the current fb will block - * in the execbuffer ioctl until the page flip happens. If a page - * flip is already pending as the ioctl is called, EBUSY will be - * returned. - * - * Flag DRM_MODE_PAGE_FLIP_EVENT requests that drm sends back a vblank - * event (see drm.h: struct drm_event_vblank) when the page flip is - * done. The user_data field passed in with this ioctl will be - * returned as the user_data field in the vblank event struct. - * - * Flag DRM_MODE_PAGE_FLIP_ASYNC requests that the flip happen - * 'as soon as possible', meaning that it not delay waiting for vblank. - * This may cause tearing on the screen. - * - * The reserved field must be zero. - */ - -struct drm_mode_crtc_page_flip { - __u32 crtc_id; - __u32 fb_id; - __u32 flags; - __u32 reserved; - __u64 user_data; -}; - -/* - * Request a page flip on the specified crtc. - * - * Same as struct drm_mode_crtc_page_flip, but supports new flags and - * re-purposes the reserved field: - * - * The sequence field must be zero unless either of the - * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is specified. When - * the ABSOLUTE flag is specified, the sequence field denotes the absolute - * vblank sequence when the flip should take effect. When the RELATIVE - * flag is specified, the sequence field denotes the relative (to the - * current one when the ioctl is called) vblank sequence when the flip - * should take effect. NOTE: DRM_IOCTL_WAIT_VBLANK must still be used to - * make sure the vblank sequence before the target one has passed before - * calling this ioctl. The purpose of the - * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is merely to clarify - * the target for when code dealing with a page flip runs during a - * vertical blank period. - */ - -struct drm_mode_crtc_page_flip_target { - __u32 crtc_id; - __u32 fb_id; - __u32 flags; - __u32 sequence; - __u64 user_data; -}; - -/* create a dumb scanout buffer */ -struct drm_mode_create_dumb { - __u32 height; - __u32 width; - __u32 bpp; - __u32 flags; - /* handle, pitch, size will be returned */ - __u32 handle; - __u32 pitch; - __u64 size; -}; - -/* set up for mmap of a dumb scanout buffer */ -struct drm_mode_map_dumb { - /** Handle for the object being mapped. */ - __u32 handle; - __u32 pad; - /** - * Fake offset to use for subsequent mmap call - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 offset; -}; - -struct drm_mode_destroy_dumb { - __u32 handle; -}; - -/* page-flip flags are valid, plus: */ -#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100 -#define DRM_MODE_ATOMIC_NONBLOCK 0x0200 -#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400 - -#define DRM_MODE_ATOMIC_FLAGS (\ - DRM_MODE_PAGE_FLIP_EVENT |\ - DRM_MODE_PAGE_FLIP_ASYNC |\ - DRM_MODE_ATOMIC_TEST_ONLY |\ - DRM_MODE_ATOMIC_NONBLOCK |\ - DRM_MODE_ATOMIC_ALLOW_MODESET) - -struct drm_mode_atomic { - __u32 flags; - __u32 count_objs; - __u64 objs_ptr; - __u64 count_props_ptr; - __u64 props_ptr; - __u64 prop_values_ptr; - __u64 reserved; - __u64 user_data; -}; - -struct drm_format_modifier_blob { -#define FORMAT_BLOB_CURRENT 1 - /* Version of this blob format */ - __u32 version; - - /* Flags */ - __u32 flags; - - /* Number of fourcc formats supported */ - __u32 count_formats; - - /* Where in this blob the formats exist (in bytes) */ - __u32 formats_offset; - - /* Number of drm_format_modifiers */ - __u32 count_modifiers; - - /* Where in this blob the modifiers exist (in bytes) */ - __u32 modifiers_offset; - - /* __u32 formats[] */ - /* struct drm_format_modifier modifiers[] */ -}; - -struct drm_format_modifier { - /* Bitmask of formats in get_plane format list this info applies to. The - * offset allows a sliding window of which 64 formats (bits). - * - * Some examples: - * In today's world with < 65 formats, and formats 0, and 2 are - * supported - * 0x0000000000000005 - * ^-offset = 0, formats = 5 - * - * If the number formats grew to 128, and formats 98-102 are - * supported with the modifier: - * - * 0x0000007c00000000 0000000000000000 - * ^ - * |__offset = 64, formats = 0x7c00000000 - * - */ - __u64 formats; - __u32 offset; - __u32 pad; - - /* The modifier that applies to the >get_plane format list bitmask. */ - __u64 modifier; -}; - -/** - * struct drm_mode_create_blob - Create New block property - * @data: Pointer to data to copy. - * @length: Length of data to copy. - * @blob_id: new property ID. - * Create a new 'blob' data property, copying length bytes from data pointer, - * and returning new blob ID. - */ -struct drm_mode_create_blob { - /** Pointer to data to copy. */ - __u64 data; - /** Length of data to copy. */ - __u32 length; - /** Return: new property ID. */ - __u32 blob_id; -}; - -/** - * struct drm_mode_destroy_blob - Destroy user blob - * @blob_id: blob_id to destroy - * Destroy a user-created blob property. - */ -struct drm_mode_destroy_blob { - __u32 blob_id; -}; - -/** - * struct drm_mode_create_lease - Create lease - * @object_ids: Pointer to array of object ids. - * @object_count: Number of object ids. - * @flags: flags for new FD. - * @lessee_id: unique identifier for lessee. - * @fd: file descriptor to new drm_master file. - * Lease mode resources, creating another drm_master. - */ -struct drm_mode_create_lease { - /** Pointer to array of object ids (__u32) */ - __u64 object_ids; - /** Number of object ids */ - __u32 object_count; - /** flags for new FD (O_CLOEXEC, etc) */ - __u32 flags; - - /** Return: unique identifier for lessee. */ - __u32 lessee_id; - /** Return: file descriptor to new drm_master file */ - __u32 fd; -}; - -/** - * struct drm_mode_list_lessees - List lessees - * @count_lessees: Number of lessees. - * @pad: pad. - * @lessees_ptr: Pointer to lessess. - * List lesses from a drm_master - */ -struct drm_mode_list_lessees { - /** Number of lessees. - * On input, provides length of the array. - * On output, provides total number. No - * more than the input number will be written - * back, so two calls can be used to get - * the size and then the data. - */ - __u32 count_lessees; - __u32 pad; - - /** Pointer to lessees. - * pointer to __u64 array of lessee ids - */ - __u64 lessees_ptr; -}; - -/** - * struct drm_mode_get_lease - Get Lease - * @count_objects: Number of leased objects. - * @pad: pad. - * @objects_ptr: Pointer to objects. - * Get leased objects - */ -struct drm_mode_get_lease { - /** Number of leased objects. - * On input, provides length of the array. - * On output, provides total number. No - * more than the input number will be written - * back, so two calls can be used to get - * the size and then the data. - */ - __u32 count_objects; - __u32 pad; - - /** Pointer to objects. - * pointer to __u32 array of object ids - */ - __u64 objects_ptr; -}; - -/** - * struct drm_mode_revoke_lease - Revoke lease - * @lessee_id: Unique ID of lessee. - * Revoke lease - */ -struct drm_mode_revoke_lease { - /** Unique ID of lessee - */ - __u32 lessee_id; -}; - -/** - * struct drm_mode_rect - Two dimensional rectangle. - * @x1: Horizontal starting coordinate (inclusive). - * @y1: Vertical starting coordinate (inclusive). - * @x2: Horizontal ending coordinate (exclusive). - * @y2: Vertical ending coordinate (exclusive). - * - * With drm subsystem using struct drm_rect to manage rectangular area this - * export it to user-space. - * - * Currently used by drm_mode_atomic blob property FB_DAMAGE_CLIPS. - */ -struct drm_mode_rect { - __s32 x1; - __s32 y1; - __s32 x2; - __s32 y2; -}; - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/third_party/uapi/xe_hp_sdv/drm/i915_drm.h b/third_party/uapi/xe_hp_sdv/drm/i915_drm.h deleted file mode 100644 index 17ce762fc8..0000000000 --- a/third_party/uapi/xe_hp_sdv/drm/i915_drm.h +++ /dev/null @@ -1,3047 +0,0 @@ -/* - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _UAPI_I915_DRM_H_ -#define _UAPI_I915_DRM_H_ - -#define __user -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* Please note that modifications to all structs defined here are - * subject to backwards-compatibility constraints. - */ - -/** - * DOC: uevents generated by i915 on it's device node - * - * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch - * event from the gpu l3 cache. Additional information supplied is ROW, - * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep - * track of these events and if a specific cache-line seems to have a - * persistent error remap it with the l3 remapping tool supplied in - * intel-gpu-tools. The value supplied with the event is always 1. - * - * I915_ERROR_UEVENT - Generated upon error detection, currently only via - * hangcheck. The error detection event is a good indicator of when things - * began to go badly. The value supplied with the event is a 1 upon error - * detection, and a 0 upon reset completion, signifying no more error - * exists. NOTE: Disabling hangcheck or reset via module parameter will - * cause the related events to not be seen. - * - * I915_RESET_UEVENT - Event is generated just before an attempt to reset the - * GPU. The value supplied with the event is always 1. NOTE: Disable - * reset via module parameter will cause this event to not be seen. - */ -#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" -#define I915_ERROR_UEVENT "ERROR" -#define I915_RESET_UEVENT "RESET" - -/** - * struct i915_user_extension - Base class for defining a chain of extensions - * - * Many interfaces need to grow over time. In most cases we can simply - * extend the struct and have userspace pass in more data. Another option, - * as demonstrated by Vulkan's approach to providing extensions for forward - * and backward compatibility, is to use a list of optional structs to - * provide those extra details. - * - * The key advantage to using an extension chain is that it allows us to - * redefine the interface more easily than an ever growing struct of - * increasing complexity, and for large parts of that interface to be - * entirely optional. The downside is more pointer chasing; chasing across - * the __user boundary with pointers encapsulated inside u64. - * - * Example chaining: - * - * .. code-block:: C - * - * struct i915_user_extension ext3 { - * .next_extension = 0, // end - * .name = ..., - * }; - * struct i915_user_extension ext2 { - * .next_extension = (uintptr_t)&ext3, - * .name = ..., - * }; - * struct i915_user_extension ext1 { - * .next_extension = (uintptr_t)&ext2, - * .name = ..., - * }; - * - * Typically the struct i915_user_extension would be embedded in some uAPI - * struct, and in this case we would feed it the head of the chain(i.e ext1), - * which would then apply all of the above extensions. - * - */ -struct i915_user_extension { - /** - * @next_extension: - * - * Pointer to the next struct i915_user_extension, or zero if the end. - */ - __u64 next_extension; - /** - * @name: Name of the extension. - * - * Note that the name here is just some integer. - * - * Also note that the name space for this is not global for the whole - * driver, but rather its scope/meaning is limited to the specific piece - * of uAPI which has embedded the struct i915_user_extension. - */ - __u32 name; - /** - * @flags: MBZ - * - * All undefined bits must be zero. - */ - __u32 flags; - /** - * @rsvd: MBZ - * - * Reserved for future use; must be zero. - */ - __u32 rsvd[4]; -}; - -/* - * MOCS indexes used for GPU surfaces, defining the cacheability of the - * surface data and the coherency for this data wrt. CPU vs. GPU accesses. - */ -enum i915_mocs_table_index { - /* - * Not cached anywhere, coherency between CPU and GPU accesses is - * guaranteed. - */ - I915_MOCS_UNCACHED, - /* - * Cacheability and coherency controlled by the kernel automatically - * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current - * usage of the surface (used for display scanout or not). - */ - I915_MOCS_PTE, - /* - * Cached in all GPU caches available on the platform. - * Coherency between CPU and GPU accesses to the surface is not - * guaranteed without extra synchronization. - */ - I915_MOCS_CACHED, -}; - -/* - * Different engines serve different roles, and there may be more than one - * engine serving each role. enum drm_i915_gem_engine_class provides a - * classification of the role of the engine, which may be used when requesting - * operations to be performed on a certain subset of engines, or for providing - * information about that group. - */ -enum drm_i915_gem_engine_class { - I915_ENGINE_CLASS_RENDER = 0, - I915_ENGINE_CLASS_COPY = 1, - I915_ENGINE_CLASS_VIDEO = 2, - I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, - I915_ENGINE_CLASS_COMPUTE = 4, - - /* should be kept compact */ - - I915_ENGINE_CLASS_INVALID = -1 -}; - -/* - * There may be more than one engine fulfilling any role within the system. - * Each engine of a class is given a unique instance number and therefore - * any engine can be specified by its class:instance tuplet. APIs that allow - * access to any engine in the system will use struct i915_engine_class_instance - * for this identification. - */ -struct i915_engine_class_instance { - __u16 engine_class; /* see enum drm_i915_gem_engine_class */ - __u16 engine_instance; -#define I915_ENGINE_CLASS_INVALID_NONE -1 -#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2 -}; - -/** - * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 - * - */ - -enum drm_i915_pmu_engine_sample { - I915_SAMPLE_BUSY = 0, - I915_SAMPLE_WAIT = 1, - I915_SAMPLE_SEMA = 2 -}; - -#define I915_PMU_SAMPLE_BITS (4) -#define I915_PMU_SAMPLE_MASK (0xf) -#define I915_PMU_SAMPLE_INSTANCE_BITS (8) -#define I915_PMU_CLASS_SHIFT \ - (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) - -#define __I915_PMU_ENGINE(class, instance, sample) \ - ((class) << I915_PMU_CLASS_SHIFT | \ - (instance) << I915_PMU_SAMPLE_BITS | \ - (sample)) - -#define I915_PMU_ENGINE_BUSY(class, instance) \ - __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) - -#define I915_PMU_ENGINE_WAIT(class, instance) \ - __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) - -#define I915_PMU_ENGINE_SEMA(class, instance) \ - __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) - -#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) - -#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) -#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) -#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) -#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) -#define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4) - -#define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY - -/* Each region is a minimum of 16k, and there are at most 255 of them. - */ -#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use - * of chars for next/prev indices */ -#define I915_LOG_MIN_TEX_REGION_SIZE 14 - -typedef struct _drm_i915_init { - enum { - I915_INIT_DMA = 0x01, - I915_CLEANUP_DMA = 0x02, - I915_RESUME_DMA = 0x03 - } func; - unsigned int mmio_offset; - int sarea_priv_offset; - unsigned int ring_start; - unsigned int ring_end; - unsigned int ring_size; - unsigned int front_offset; - unsigned int back_offset; - unsigned int depth_offset; - unsigned int w; - unsigned int h; - unsigned int pitch; - unsigned int pitch_bits; - unsigned int back_pitch; - unsigned int depth_pitch; - unsigned int cpp; - unsigned int chipset; -} drm_i915_init_t; - -typedef struct _drm_i915_sarea { - struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; - int last_upload; /* last time texture was uploaded */ - int last_enqueue; /* last time a buffer was enqueued */ - int last_dispatch; /* age of the most recently dispatched buffer */ - int ctxOwner; /* last context to upload state */ - int texAge; - int pf_enabled; /* is pageflipping allowed? */ - int pf_active; - int pf_current_page; /* which buffer is being displayed? */ - int perf_boxes; /* performance boxes to be displayed */ - int width, height; /* screen size in pixels */ - - drm_handle_t front_handle; - int front_offset; - int front_size; - - drm_handle_t back_handle; - int back_offset; - int back_size; - - drm_handle_t depth_handle; - int depth_offset; - int depth_size; - - drm_handle_t tex_handle; - int tex_offset; - int tex_size; - int log_tex_granularity; - int pitch; - int rotation; /* 0, 90, 180 or 270 */ - int rotated_offset; - int rotated_size; - int rotated_pitch; - int virtualX, virtualY; - - unsigned int front_tiled; - unsigned int back_tiled; - unsigned int depth_tiled; - unsigned int rotated_tiled; - unsigned int rotated2_tiled; - - int pipeA_x; - int pipeA_y; - int pipeA_w; - int pipeA_h; - int pipeB_x; - int pipeB_y; - int pipeB_w; - int pipeB_h; - - /* fill out some space for old userspace triple buffer */ - drm_handle_t unused_handle; - __u32 unused1, unused2, unused3; - - /* buffer object handles for static buffers. May change - * over the lifetime of the client. - */ - __u32 front_bo_handle; - __u32 back_bo_handle; - __u32 unused_bo_handle; - __u32 depth_bo_handle; - -} drm_i915_sarea_t; - -/* due to userspace building against these headers we need some compat here */ -#define planeA_x pipeA_x -#define planeA_y pipeA_y -#define planeA_w pipeA_w -#define planeA_h pipeA_h -#define planeB_x pipeB_x -#define planeB_y pipeB_y -#define planeB_w pipeB_w -#define planeB_h pipeB_h - -/* Flags for perf_boxes - */ -#define I915_BOX_RING_EMPTY 0x1 -#define I915_BOX_FLIP 0x2 -#define I915_BOX_WAIT 0x4 -#define I915_BOX_TEXTURE_LOAD 0x8 -#define I915_BOX_LOST_CONTEXT 0x10 - -/* - * i915 specific ioctls. - * - * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie - * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset - * against DRM_COMMAND_BASE and should be between [0x0, 0x60). - */ -#define DRM_I915_INIT 0x00 -#define DRM_I915_FLUSH 0x01 -#define DRM_I915_FLIP 0x02 -#define DRM_I915_BATCHBUFFER 0x03 -#define DRM_I915_IRQ_EMIT 0x04 -#define DRM_I915_IRQ_WAIT 0x05 -#define DRM_I915_GETPARAM 0x06 -#define DRM_I915_SETPARAM 0x07 -#define DRM_I915_ALLOC 0x08 -#define DRM_I915_FREE 0x09 -#define DRM_I915_INIT_HEAP 0x0a -#define DRM_I915_CMDBUFFER 0x0b -#define DRM_I915_DESTROY_HEAP 0x0c -#define DRM_I915_SET_VBLANK_PIPE 0x0d -#define DRM_I915_GET_VBLANK_PIPE 0x0e -#define DRM_I915_VBLANK_SWAP 0x0f -#define DRM_I915_HWS_ADDR 0x11 -#define DRM_I915_GEM_INIT 0x13 -#define DRM_I915_GEM_EXECBUFFER 0x14 -#define DRM_I915_GEM_PIN 0x15 -#define DRM_I915_GEM_UNPIN 0x16 -#define DRM_I915_GEM_BUSY 0x17 -#define DRM_I915_GEM_THROTTLE 0x18 -#define DRM_I915_GEM_ENTERVT 0x19 -#define DRM_I915_GEM_LEAVEVT 0x1a -#define DRM_I915_GEM_CREATE 0x1b -#define DRM_I915_GEM_PREAD 0x1c -#define DRM_I915_GEM_PWRITE 0x1d -#define DRM_I915_GEM_MMAP 0x1e -#define DRM_I915_GEM_SET_DOMAIN 0x1f -#define DRM_I915_GEM_SW_FINISH 0x20 -#define DRM_I915_GEM_SET_TILING 0x21 -#define DRM_I915_GEM_GET_TILING 0x22 -#define DRM_I915_GEM_GET_APERTURE 0x23 -#define DRM_I915_GEM_MMAP_GTT 0x24 -#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 -#define DRM_I915_GEM_MADVISE 0x26 -#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 -#define DRM_I915_OVERLAY_ATTRS 0x28 -#define DRM_I915_GEM_EXECBUFFER2 0x29 -#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 -#define DRM_I915_GET_SPRITE_COLORKEY 0x2a -#define DRM_I915_SET_SPRITE_COLORKEY 0x2b -#define DRM_I915_GEM_WAIT 0x2c -#define DRM_I915_GEM_CONTEXT_CREATE 0x2d -#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e -#define DRM_I915_GEM_SET_CACHING 0x2f -#define DRM_I915_GEM_GET_CACHING 0x30 -#define DRM_I915_REG_READ 0x31 -#define DRM_I915_GET_RESET_STATS 0x32 -#define DRM_I915_GEM_USERPTR 0x33 -#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 -#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 -#define DRM_I915_PERF_OPEN 0x36 -#define DRM_I915_PERF_ADD_CONFIG 0x37 -#define DRM_I915_PERF_REMOVE_CONFIG 0x38 -#define DRM_I915_QUERY 0x39 -#define DRM_I915_GEM_VM_CREATE 0x3a -#define DRM_I915_GEM_VM_DESTROY 0x3b -#define DRM_I915_GEM_CREATE_EXT 0x3c -/* Must be kept compact -- no holes */ - -#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) -#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) -#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) -#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) -#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) -#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) -#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) -#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) -#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) -#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) -#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) -#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) -#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) -#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) -#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) -#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) -#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) -#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) -#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) -#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) -#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) -#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) -#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) -#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) -#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) -#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) -#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) -#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) -#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext) -#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) -#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) -#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) -#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) -#define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset) -#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) -#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) -#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) -#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) -#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) -#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) -#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) -#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) -#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) -#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) -#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) -#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) -#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) -#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) -#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) -#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) -#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) -#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) -#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) -#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) -#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) -#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) -#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) -#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) -#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) -#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) - -/* Allow drivers to submit batchbuffers directly to hardware, relying - * on the security mechanisms provided by hardware. - */ -typedef struct drm_i915_batchbuffer { - int start; /* agp offset */ - int used; /* nr bytes in use */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ -} drm_i915_batchbuffer_t; - -/* As above, but pass a pointer to userspace buffer which can be - * validated by the kernel prior to sending to hardware. - */ -typedef struct _drm_i915_cmdbuffer { - char __user *buf; /* pointer to userspace command buffer */ - int sz; /* nr bytes in buf */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ -} drm_i915_cmdbuffer_t; - -/* Userspace can request & wait on irq's: - */ -typedef struct drm_i915_irq_emit { - int __user *irq_seq; -} drm_i915_irq_emit_t; - -typedef struct drm_i915_irq_wait { - int irq_seq; -} drm_i915_irq_wait_t; - -/* - * Different modes of per-process Graphics Translation Table, - * see I915_PARAM_HAS_ALIASING_PPGTT - */ -#define I915_GEM_PPGTT_NONE 0 -#define I915_GEM_PPGTT_ALIASING 1 -#define I915_GEM_PPGTT_FULL 2 - -/* Ioctl to query kernel params: - */ -#define I915_PARAM_IRQ_ACTIVE 1 -#define I915_PARAM_ALLOW_BATCHBUFFER 2 -#define I915_PARAM_LAST_DISPATCH 3 -#define I915_PARAM_CHIPSET_ID 4 -#define I915_PARAM_HAS_GEM 5 -#define I915_PARAM_NUM_FENCES_AVAIL 6 -#define I915_PARAM_HAS_OVERLAY 7 -#define I915_PARAM_HAS_PAGEFLIPPING 8 -#define I915_PARAM_HAS_EXECBUF2 9 -#define I915_PARAM_HAS_BSD 10 -#define I915_PARAM_HAS_BLT 11 -#define I915_PARAM_HAS_RELAXED_FENCING 12 -#define I915_PARAM_HAS_COHERENT_RINGS 13 -#define I915_PARAM_HAS_EXEC_CONSTANTS 14 -#define I915_PARAM_HAS_RELAXED_DELTA 15 -#define I915_PARAM_HAS_GEN7_SOL_RESET 16 -#define I915_PARAM_HAS_LLC 17 -#define I915_PARAM_HAS_ALIASING_PPGTT 18 -#define I915_PARAM_HAS_WAIT_TIMEOUT 19 -#define I915_PARAM_HAS_SEMAPHORES 20 -#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 -#define I915_PARAM_HAS_VEBOX 22 -#define I915_PARAM_HAS_SECURE_BATCHES 23 -#define I915_PARAM_HAS_PINNED_BATCHES 24 -#define I915_PARAM_HAS_EXEC_NO_RELOC 25 -#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 -#define I915_PARAM_HAS_WT 27 -#define I915_PARAM_CMD_PARSER_VERSION 28 -#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 -#define I915_PARAM_MMAP_VERSION 30 -#define I915_PARAM_HAS_BSD2 31 -#define I915_PARAM_REVISION 32 -#define I915_PARAM_SUBSLICE_TOTAL 33 -#define I915_PARAM_EU_TOTAL 34 -#define I915_PARAM_HAS_GPU_RESET 35 -#define I915_PARAM_HAS_RESOURCE_STREAMER 36 -#define I915_PARAM_HAS_EXEC_SOFTPIN 37 -#define I915_PARAM_HAS_POOLED_EU 38 -#define I915_PARAM_MIN_EU_IN_POOL 39 -#define I915_PARAM_MMAP_GTT_VERSION 40 - -/* - * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution - * priorities and the driver will attempt to execute batches in priority order. - * The param returns a capability bitmask, nonzero implies that the scheduler - * is enabled, with different features present according to the mask. - * - * The initial priority for each batch is supplied by the context and is - * controlled via I915_CONTEXT_PARAM_PRIORITY. - */ -#define I915_PARAM_HAS_SCHEDULER 41 -#define I915_SCHEDULER_CAP_ENABLED (1ul << 0) -#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) -#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) -#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) -#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) -/* - * Indicates the 2k user priority levels are statically mapped into 3 buckets as - * follows: - * - * -1k to -1 Low priority - * 0 Normal priority - * 1 to 1k Highest priority - */ -#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5) - -#define I915_PARAM_HUC_STATUS 42 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of - * synchronisation with implicit fencing on individual objects. - * See EXEC_OBJECT_ASYNC. - */ -#define I915_PARAM_HAS_EXEC_ASYNC 43 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - - * both being able to pass in a sync_file fd to wait upon before executing, - * and being able to return a new sync_file fd that is signaled when the - * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. - */ -#define I915_PARAM_HAS_EXEC_FENCE 44 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture - * user specified bufffers for post-mortem debugging of GPU hangs. See - * EXEC_OBJECT_CAPTURE. - */ -#define I915_PARAM_HAS_EXEC_CAPTURE 45 - -#define I915_PARAM_SLICE_MASK 46 - -/* Assuming it's uniform for each slice, this queries the mask of subslices - * per-slice for this system. - */ -#define I915_PARAM_SUBSLICE_MASK 47 - -/* - * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer - * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. - */ -#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of - * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. - */ -#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 - -/* - * Query whether every context (both per-file default and user created) is - * isolated (insofar as HW supports). If this parameter is not true, then - * freshly created contexts may inherit values from an existing context, - * rather than default HW values. If true, it also ensures (insofar as HW - * supports) that all state set by this context will not leak to any other - * context. - * - * As not every engine across every gen support contexts, the returned - * value reports the support of context isolation for individual engines by - * returning a bitmask of each engine class set to true if that class supports - * isolation. - */ -#define I915_PARAM_HAS_CONTEXT_ISOLATION 50 - -/* Frequency of the command streamer timestamps given by the *_TIMESTAMP - * registers. This used to be fixed per platform but from CNL onwards, this - * might vary depending on the parts. - */ -#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 - -/* - * Once upon a time we supposed that writes through the GGTT would be - * immediately in physical memory (once flushed out of the CPU path). However, - * on a few different processors and chipsets, this is not necessarily the case - * as the writes appear to be buffered internally. Thus a read of the backing - * storage (physical memory) via a different path (with different physical tags - * to the indirect write via the GGTT) will see stale values from before - * the GGTT write. Inside the kernel, we can for the most part keep track of - * the different read/write domains in use (e.g. set-domain), but the assumption - * of coherency is baked into the ABI, hence reporting its true state in this - * parameter. - * - * Reports true when writes via mmap_gtt are immediately visible following an - * lfence to flush the WCB. - * - * Reports false when writes via mmap_gtt are indeterminately delayed in an in - * internal buffer and are _not_ immediately visible to third parties accessing - * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC - * communications channel when reporting false is strongly disadvised. - */ -#define I915_PARAM_MMAP_GTT_COHERENT 52 - -/* - * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel - * execution through use of explicit fence support. - * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT. - */ -#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 - -/* - * Revision of the i915-perf uAPI. The value returned helps determine what - * i915-perf features are available. See drm_i915_perf_property_id. - */ -#define I915_PARAM_PERF_REVISION 54 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of - * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See - * I915_EXEC_USE_EXTENSIONS. - */ -#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55 - -/* Query if the kernel supports the I915_USERPTR_PROBE flag. */ -#define I915_PARAM_HAS_USERPTR_PROBE 56 - -/* Must be kept compact -- no holes and well documented */ - -typedef struct drm_i915_getparam { - __s32 param; - /* - * WARNING: Using pointers instead of fixed-size u64 means we need to write - * compat32 code. Don't repeat this mistake. - */ - int __user *value; -} drm_i915_getparam_t; - -/* Ioctl to set kernel params: - */ -#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 -#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 -#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 -#define I915_SETPARAM_NUM_USED_FENCES 4 -/* Must be kept compact -- no holes */ - -typedef struct drm_i915_setparam { - int param; - int value; -} drm_i915_setparam_t; - -/* A memory manager for regions of shared memory: - */ -#define I915_MEM_REGION_AGP 1 - -typedef struct drm_i915_mem_alloc { - int region; - int alignment; - int size; - int __user *region_offset; /* offset from start of fb or agp */ -} drm_i915_mem_alloc_t; - -typedef struct drm_i915_mem_free { - int region; - int region_offset; -} drm_i915_mem_free_t; - -typedef struct drm_i915_mem_init_heap { - int region; - int size; - int start; -} drm_i915_mem_init_heap_t; - -/* Allow memory manager to be torn down and re-initialized (eg on - * rotate): - */ -typedef struct drm_i915_mem_destroy_heap { - int region; -} drm_i915_mem_destroy_heap_t; - -/* Allow X server to configure which pipes to monitor for vblank signals - */ -#define DRM_I915_VBLANK_PIPE_A 1 -#define DRM_I915_VBLANK_PIPE_B 2 - -typedef struct drm_i915_vblank_pipe { - int pipe; -} drm_i915_vblank_pipe_t; - -/* Schedule buffer swap at given vertical blank: - */ -typedef struct drm_i915_vblank_swap { - drm_drawable_t drawable; - enum drm_vblank_seq_type seqtype; - unsigned int sequence; -} drm_i915_vblank_swap_t; - -typedef struct drm_i915_hws_addr { - __u64 addr; -} drm_i915_hws_addr_t; - -struct drm_i915_gem_init { - /** - * Beginning offset in the GTT to be managed by the DRM memory - * manager. - */ - __u64 gtt_start; - /** - * Ending offset in the GTT to be managed by the DRM memory - * manager. - */ - __u64 gtt_end; -}; - -struct drm_i915_gem_create { - /** - * Requested size for the object. - * - * The (page-aligned) allocated size for the object will be returned. - */ - __u64 size; - /** - * Returned handle for the object. - * - * Object handles are nonzero. - */ - __u32 handle; - __u32 pad; -}; - -struct drm_i915_gem_pread { - /** Handle for the object being read. */ - __u32 handle; - __u32 pad; - /** Offset into the object to read from */ - __u64 offset; - /** Length of data to read */ - __u64 size; - /** - * Pointer to write the data into. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 data_ptr; -}; - -struct drm_i915_gem_pwrite { - /** Handle for the object being written to. */ - __u32 handle; - __u32 pad; - /** Offset into the object to write to */ - __u64 offset; - /** Length of data to write */ - __u64 size; - /** - * Pointer to read the data from. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 data_ptr; -}; - -struct drm_i915_gem_mmap { - /** Handle for the object being mapped. */ - __u32 handle; - __u32 pad; - /** Offset in the object to map. */ - __u64 offset; - /** - * Length of data to map. - * - * The value will be page-aligned. - */ - __u64 size; - /** - * Returned pointer the data was mapped at. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 addr_ptr; - - /** - * Flags for extended behaviour. - * - * Added in version 2. - */ - __u64 flags; -#define I915_MMAP_WC 0x1 -}; - -struct drm_i915_gem_mmap_gtt { - /** Handle for the object being mapped. */ - __u32 handle; - __u32 pad; - /** - * Fake offset to use for subsequent mmap call - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 offset; -}; - -/** - * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object. - * - * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl, - * and is used to retrieve the fake offset to mmap an object specified by &handle. - * - * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+. - * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave - * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`. - */ -struct drm_i915_gem_mmap_offset { - /** @handle: Handle for the object being mapped. */ - __u32 handle; - /** @pad: Must be zero */ - __u32 pad; - /** - * @offset: The fake offset to use for subsequent mmap call - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 offset; - - /** - * @flags: Flags for extended behaviour. - * - * It is mandatory that one of the `MMAP_OFFSET` types - * should be included: - * - * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) - * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. - * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. - * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. - * - * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid - * type. On devices without local memory, this caching mode is invalid. - * - * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will - * be used, depending on the object placement on creation. WB will be used - * when the object can only exist in system memory, WC otherwise. - */ - __u64 flags; - -#define I915_MMAP_OFFSET_GTT 0 -#define I915_MMAP_OFFSET_WC 1 -#define I915_MMAP_OFFSET_WB 2 -#define I915_MMAP_OFFSET_UC 3 -#define I915_MMAP_OFFSET_FIXED 4 - - /** - * @extensions: Zero-terminated chain of extensions. - * - * No current extensions defined; mbz. - */ - __u64 extensions; -}; - -/** - * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in - * preparation for accessing the pages via some CPU domain. - * - * Specifying a new write or read domain will flush the object out of the - * previous domain(if required), before then updating the objects domain - * tracking with the new domain. - * - * Note this might involve waiting for the object first if it is still active on - * the GPU. - * - * Supported values for @read_domains and @write_domain: - * - * - I915_GEM_DOMAIN_WC: Uncached write-combined domain - * - I915_GEM_DOMAIN_CPU: CPU cache domain - * - I915_GEM_DOMAIN_GTT: Mappable aperture domain - * - * All other domains are rejected. - * - * Note that for discrete, starting from DG1, this is no longer supported, and - * is instead rejected. On such platforms the CPU domain is effectively static, - * where we also only support a single &drm_i915_gem_mmap_offset cache mode, - * which can't be set explicitly and instead depends on the object placements, - * as per the below. - * - * Implicit caching rules, starting from DG1: - * - * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) - * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and - * mapped as write-combined only. - * - * - Everything else is always allocated and mapped as write-back, with the - * guarantee that everything is also coherent with the GPU. - * - * Note that this is likely to change in the future again, where we might need - * more flexibility on future devices, so making this all explicit as part of a - * new &drm_i915_gem_create_ext extension is probable. - */ -struct drm_i915_gem_set_domain { - /** @handle: Handle for the object. */ - __u32 handle; - - /** @read_domains: New read domains. */ - __u32 read_domains; - - /** - * @write_domain: New write domain. - * - * Note that having something in the write domain implies it's in the - * read domain, and only that read domain. - */ - __u32 write_domain; -}; - -struct drm_i915_gem_sw_finish { - /** Handle for the object */ - __u32 handle; -}; - -struct drm_i915_gem_relocation_entry { - /** - * Handle of the buffer being pointed to by this relocation entry. - * - * It's appealing to make this be an index into the mm_validate_entry - * list to refer to the buffer, but this allows the driver to create - * a relocation list for state buffers and not re-write it per - * exec using the buffer. - */ - __u32 target_handle; - - /** - * Value to be added to the offset of the target buffer to make up - * the relocation entry. - */ - __u32 delta; - - /** Offset in the buffer the relocation entry will be written into */ - __u64 offset; - - /** - * Offset value of the target buffer that the relocation entry was last - * written as. - * - * If the buffer has the same offset as last time, we can skip syncing - * and writing the relocation. This value is written back out by - * the execbuffer ioctl when the relocation is written. - */ - __u64 presumed_offset; - - /** - * Target memory domains read by this operation. - */ - __u32 read_domains; - - /** - * Target memory domains written by this operation. - * - * Note that only one domain may be written by the whole - * execbuffer operation, so that where there are conflicts, - * the application will get -EINVAL back. - */ - __u32 write_domain; -}; - -/** @{ - * Intel memory domains - * - * Most of these just align with the various caches in - * the system and are used to flush and invalidate as - * objects end up cached in different domains. - */ -/** CPU cache */ -#define I915_GEM_DOMAIN_CPU 0x00000001 -/** Render cache, used by 2D and 3D drawing */ -#define I915_GEM_DOMAIN_RENDER 0x00000002 -/** Sampler cache, used by texture engine */ -#define I915_GEM_DOMAIN_SAMPLER 0x00000004 -/** Command queue, used to load batch buffers */ -#define I915_GEM_DOMAIN_COMMAND 0x00000008 -/** Instruction cache, used by shader programs */ -#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 -/** Vertex address cache */ -#define I915_GEM_DOMAIN_VERTEX 0x00000020 -/** GTT domain - aperture and scanout */ -#define I915_GEM_DOMAIN_GTT 0x00000040 -/** WC domain - uncached access */ -#define I915_GEM_DOMAIN_WC 0x00000080 -/** @} */ - -struct drm_i915_gem_exec_object { - /** - * User's handle for a buffer to be bound into the GTT for this - * operation. - */ - __u32 handle; - - /** Number of relocations to be performed on this buffer */ - __u32 relocation_count; - /** - * Pointer to array of struct drm_i915_gem_relocation_entry containing - * the relocations to be performed in this buffer. - */ - __u64 relocs_ptr; - - /** Required alignment in graphics aperture */ - __u64 alignment; - - /** - * Returned value of the updated offset of the object, for future - * presumed_offset writes. - */ - __u64 offset; -}; - -/* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */ -struct drm_i915_gem_execbuffer { - /** - * List of buffers to be validated with their relocations to be - * performend on them. - * - * This is a pointer to an array of struct drm_i915_gem_validate_entry. - * - * These buffers must be listed in an order such that all relocations - * a buffer is performing refer to buffers that have already appeared - * in the validate list. - */ - __u64 buffers_ptr; - __u32 buffer_count; - - /** Offset in the batchbuffer to start execution from. */ - __u32 batch_start_offset; - /** Bytes used in batchbuffer from batch_start_offset */ - __u32 batch_len; - __u32 DR1; - __u32 DR4; - __u32 num_cliprects; - /** This is a struct drm_clip_rect *cliprects */ - __u64 cliprects_ptr; -}; - -struct drm_i915_gem_exec_object2 { - /** - * User's handle for a buffer to be bound into the GTT for this - * operation. - */ - __u32 handle; - - /** Number of relocations to be performed on this buffer */ - __u32 relocation_count; - /** - * Pointer to array of struct drm_i915_gem_relocation_entry containing - * the relocations to be performed in this buffer. - */ - __u64 relocs_ptr; - - /** Required alignment in graphics aperture */ - __u64 alignment; - - /** - * When the EXEC_OBJECT_PINNED flag is specified this is populated by - * the user with the GTT offset at which this object will be pinned. - * When the I915_EXEC_NO_RELOC flag is specified this must contain the - * presumed_offset of the object. - * During execbuffer2 the kernel populates it with the value of the - * current GTT offset of the object, for future presumed_offset writes. - */ - __u64 offset; - -#define EXEC_OBJECT_NEEDS_FENCE (1<<0) -#define EXEC_OBJECT_NEEDS_GTT (1<<1) -#define EXEC_OBJECT_WRITE (1<<2) -#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) -#define EXEC_OBJECT_PINNED (1<<4) -#define EXEC_OBJECT_PAD_TO_SIZE (1<<5) -/* The kernel implicitly tracks GPU activity on all GEM objects, and - * synchronises operations with outstanding rendering. This includes - * rendering on other devices if exported via dma-buf. However, sometimes - * this tracking is too coarse and the user knows better. For example, - * if the object is split into non-overlapping ranges shared between different - * clients or engines (i.e. suballocating objects), the implicit tracking - * by kernel assumes that each operation affects the whole object rather - * than an individual range, causing needless synchronisation between clients. - * The kernel will also forgo any CPU cache flushes prior to rendering from - * the object as the client is expected to be also handling such domain - * tracking. - * - * The kernel maintains the implicit tracking in order to manage resources - * used by the GPU - this flag only disables the synchronisation prior to - * rendering with this object in this execbuf. - * - * Opting out of implicit synhronisation requires the user to do its own - * explicit tracking to avoid rendering corruption. See, for example, - * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. - */ -#define EXEC_OBJECT_ASYNC (1<<6) -/* Request that the contents of this execobject be copied into the error - * state upon a GPU hang involving this batch for post-mortem debugging. - * These buffers are recorded in no particular order as "user" in - * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see - * if the kernel supports this flag. - */ -#define EXEC_OBJECT_CAPTURE (1<<7) -/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ -#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) - __u64 flags; - - union { - __u64 rsvd1; - __u64 pad_to_size; - }; - __u64 rsvd2; -}; - -struct drm_i915_gem_exec_fence { - /** - * User's handle for a drm_syncobj to wait on or signal. - */ - __u32 handle; - -#define I915_EXEC_FENCE_WAIT (1<<0) -#define I915_EXEC_FENCE_SIGNAL (1<<1) -#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) - __u32 flags; -}; - -/* - * See drm_i915_gem_execbuffer_ext_timeline_fences. - */ -#define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0 - -/* - * This structure describes an array of drm_syncobj and associated points for - * timeline variants of drm_syncobj. It is invalid to append this structure to - * the execbuf if I915_EXEC_FENCE_ARRAY is set. - */ -struct drm_i915_gem_execbuffer_ext_timeline_fences { - struct i915_user_extension base; - - /** - * Number of element in the handles_ptr & value_ptr arrays. - */ - __u64 fence_count; - - /** - * Pointer to an array of struct drm_i915_gem_exec_fence of length - * fence_count. - */ - __u64 handles_ptr; - - /** - * Pointer to an array of u64 values of length fence_count. Values - * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline - * drm_syncobj is invalid as it turns a drm_syncobj into a binary one. - */ - __u64 values_ptr; -}; - -struct drm_i915_gem_execbuffer2 { - /** - * List of gem_exec_object2 structs - */ - __u64 buffers_ptr; - __u32 buffer_count; - - /** Offset in the batchbuffer to start execution from. */ - __u32 batch_start_offset; - /** Bytes used in batchbuffer from batch_start_offset */ - __u32 batch_len; - __u32 DR1; - __u32 DR4; - __u32 num_cliprects; - /** - * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY - * & I915_EXEC_USE_EXTENSIONS are not set. - * - * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array - * of struct drm_i915_gem_exec_fence and num_cliprects is the length - * of the array. - * - * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a - * single struct i915_user_extension and num_cliprects is 0. - */ - __u64 cliprects_ptr; -#define I915_EXEC_RING_MASK (0x3f) -#define I915_EXEC_DEFAULT (0<<0) -#define I915_EXEC_RENDER (1<<0) -#define I915_EXEC_BSD (2<<0) -#define I915_EXEC_BLT (3<<0) -#define I915_EXEC_VEBOX (4<<0) - -/* Used for switching the constants addressing mode on gen4+ RENDER ring. - * Gen6+ only supports relative addressing to dynamic state (default) and - * absolute addressing. - * - * These flags are ignored for the BSD and BLT rings. - */ -#define I915_EXEC_CONSTANTS_MASK (3<<6) -#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ -#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) -#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ - __u64 flags; - __u64 rsvd1; /* now used for context info */ - __u64 rsvd2; -}; - -/** Resets the SO write offset registers for transform feedback on gen7. */ -#define I915_EXEC_GEN7_SOL_RESET (1<<8) - -/** Request a privileged ("secure") batch buffer. Note only available for - * DRM_ROOT_ONLY | DRM_MASTER processes. - */ -#define I915_EXEC_SECURE (1<<9) - -/** Inform the kernel that the batch is and will always be pinned. This - * negates the requirement for a workaround to be performed to avoid - * an incoherent CS (such as can be found on 830/845). If this flag is - * not passed, the kernel will endeavour to make sure the batch is - * coherent with the CS before execution. If this flag is passed, - * userspace assumes the responsibility for ensuring the same. - */ -#define I915_EXEC_IS_PINNED (1<<10) - -/** Provide a hint to the kernel that the command stream and auxiliary - * state buffers already holds the correct presumed addresses and so the - * relocation process may be skipped if no buffers need to be moved in - * preparation for the execbuffer. - */ -#define I915_EXEC_NO_RELOC (1<<11) - -/** Use the reloc.handle as an index into the exec object array rather - * than as the per-file handle. - */ -#define I915_EXEC_HANDLE_LUT (1<<12) - -/** Used for switching BSD rings on the platforms with two BSD rings */ -#define I915_EXEC_BSD_SHIFT (13) -#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) -/* default ping-pong mode */ -#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) -#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) -#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) - -/** Tell the kernel that the batchbuffer is processed by - * the resource streamer. - */ -#define I915_EXEC_RESOURCE_STREAMER (1<<15) - -/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent - * a sync_file fd to wait upon (in a nonblocking manner) prior to executing - * the batch. - * - * Returns -EINVAL if the sync_file fd cannot be found. - */ -#define I915_EXEC_FENCE_IN (1<<16) - -/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd - * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given - * to the caller, and it should be close() after use. (The fd is a regular - * file descriptor and will be cleaned up on process termination. It holds - * a reference to the request, but nothing else.) - * - * The sync_file fd can be combined with other sync_file and passed either - * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip - * will only occur after this request completes), or to other devices. - * - * Using I915_EXEC_FENCE_OUT requires use of - * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written - * back to userspace. Failure to do so will cause the out-fence to always - * be reported as zero, and the real fence fd to be leaked. - */ -#define I915_EXEC_FENCE_OUT (1<<17) - -/* - * Traditionally the execbuf ioctl has only considered the final element in - * the execobject[] to be the executable batch. Often though, the client - * will known the batch object prior to construction and being able to place - * it into the execobject[] array first can simplify the relocation tracking. - * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the - * execobject[] as the * batch instead (the default is to use the last - * element). - */ -#define I915_EXEC_BATCH_FIRST (1<<18) - -/* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr - * define an array of i915_gem_exec_fence structures which specify a set of - * dma fences to wait upon or signal. - */ -#define I915_EXEC_FENCE_ARRAY (1<<19) - -/* - * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent - * a sync_file fd to wait upon (in a nonblocking manner) prior to executing - * the batch. - * - * Returns -EINVAL if the sync_file fd cannot be found. - */ -#define I915_EXEC_FENCE_SUBMIT (1 << 20) - -/* - * Setting I915_EXEC_USE_EXTENSIONS implies that - * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked - * list of i915_user_extension. Each i915_user_extension node is the base of a - * larger structure. The list of supported structures are listed in the - * drm_i915_gem_execbuffer_ext enum. - */ -#define I915_EXEC_USE_EXTENSIONS (1 << 21) - -#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)) - -#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) -#define i915_execbuffer2_set_context_id(eb2, context) \ - (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK -#define i915_execbuffer2_get_context_id(eb2) \ - ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) - -struct drm_i915_gem_pin { - /** Handle of the buffer to be pinned. */ - __u32 handle; - __u32 pad; - - /** alignment required within the aperture */ - __u64 alignment; - - /** Returned GTT offset of the buffer. */ - __u64 offset; -}; - -struct drm_i915_gem_unpin { - /** Handle of the buffer to be unpinned. */ - __u32 handle; - __u32 pad; -}; - -struct drm_i915_gem_busy { - /** Handle of the buffer to check for busy */ - __u32 handle; - - /** Return busy status - * - * A return of 0 implies that the object is idle (after - * having flushed any pending activity), and a non-zero return that - * the object is still in-flight on the GPU. (The GPU has not yet - * signaled completion for all pending requests that reference the - * object.) An object is guaranteed to become idle eventually (so - * long as no new GPU commands are executed upon it). Due to the - * asynchronous nature of the hardware, an object reported - * as busy may become idle before the ioctl is completed. - * - * Furthermore, if the object is busy, which engine is busy is only - * provided as a guide and only indirectly by reporting its class - * (there may be more than one engine in each class). There are race - * conditions which prevent the report of which engines are busy from - * being always accurate. However, the converse is not true. If the - * object is idle, the result of the ioctl, that all engines are idle, - * is accurate. - * - * The returned dword is split into two fields to indicate both - * the engine classess on which the object is being read, and the - * engine class on which it is currently being written (if any). - * - * The low word (bits 0:15) indicate if the object is being written - * to by any engine (there can only be one, as the GEM implicit - * synchronisation rules force writes to be serialised). Only the - * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as - * 1 not 0 etc) for the last write is reported. - * - * The high word (bits 16:31) are a bitmask of which engines classes - * are currently reading from the object. Multiple engines may be - * reading from the object simultaneously. - * - * The value of each engine class is the same as specified in the - * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e. - * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc. - * Some hardware may have parallel execution engines, e.g. multiple - * media engines, which are mapped to the same class identifier and so - * are not separately reported for busyness. - * - * Caveat emptor: - * Only the boolean result of this query is reliable; that is whether - * the object is idle or busy. The report of which engines are busy - * should be only used as a heuristic. - */ - __u32 busy; -}; - -/** - * struct drm_i915_gem_caching - Set or get the caching for given object - * handle. - * - * Allow userspace to control the GTT caching bits for a given object when the - * object is later mapped through the ppGTT(or GGTT on older platforms lacking - * ppGTT support, or if the object is used for scanout). Note that this might - * require unbinding the object from the GTT first, if its current caching value - * doesn't match. - * - * Note that this all changes on discrete platforms, starting from DG1, the - * set/get caching is no longer supported, and is now rejected. Instead the CPU - * caching attributes(WB vs WC) will become an immutable creation time property - * for the object, along with the GTT caching level. For now we don't expose any - * new uAPI for this, instead on DG1 this is all implicit, although this largely - * shouldn't matter since DG1 is coherent by default(without any way of - * controlling it). - * - * Implicit caching rules, starting from DG1: - * - * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) - * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and - * mapped as write-combined only. - * - * - Everything else is always allocated and mapped as write-back, with the - * guarantee that everything is also coherent with the GPU. - * - * Note that this is likely to change in the future again, where we might need - * more flexibility on future devices, so making this all explicit as part of a - * new &drm_i915_gem_create_ext extension is probable. - * - * Side note: Part of the reason for this is that changing the at-allocation-time CPU - * caching attributes for the pages might be required(and is expensive) if we - * need to then CPU map the pages later with different caching attributes. This - * inconsistent caching behaviour, while supported on x86, is not universally - * supported on other architectures. So for simplicity we opt for setting - * everything at creation time, whilst also making it immutable, on discrete - * platforms. - */ -struct drm_i915_gem_caching { - /** - * @handle: Handle of the buffer to set/get the caching level. - */ - __u32 handle; - - /** - * @caching: The GTT caching level to apply or possible return value. - * - * The supported @caching values: - * - * I915_CACHING_NONE: - * - * GPU access is not coherent with CPU caches. Default for machines - * without an LLC. This means manual flushing might be needed, if we - * want GPU access to be coherent. - * - * I915_CACHING_CACHED: - * - * GPU access is coherent with CPU caches and furthermore the data is - * cached in last-level caches shared between CPU cores and the GPU GT. - * - * I915_CACHING_DISPLAY: - * - * Special GPU caching mode which is coherent with the scanout engines. - * Transparently falls back to I915_CACHING_NONE on platforms where no - * special cache mode (like write-through or gfdt flushing) is - * available. The kernel automatically sets this mode when using a - * buffer as a scanout target. Userspace can manually set this mode to - * avoid a costly stall and clflush in the hotpath of drawing the first - * frame. - */ -#define I915_CACHING_NONE 0 -#define I915_CACHING_CACHED 1 -#define I915_CACHING_DISPLAY 2 - __u32 caching; -}; - -#define I915_TILING_NONE 0 -#define I915_TILING_X 1 -#define I915_TILING_Y 2 -#define I915_TILING_LAST I915_TILING_Y - -#define I915_BIT_6_SWIZZLE_NONE 0 -#define I915_BIT_6_SWIZZLE_9 1 -#define I915_BIT_6_SWIZZLE_9_10 2 -#define I915_BIT_6_SWIZZLE_9_11 3 -#define I915_BIT_6_SWIZZLE_9_10_11 4 -/* Not seen by userland */ -#define I915_BIT_6_SWIZZLE_UNKNOWN 5 -/* Seen by userland. */ -#define I915_BIT_6_SWIZZLE_9_17 6 -#define I915_BIT_6_SWIZZLE_9_10_17 7 - -struct drm_i915_gem_set_tiling { - /** Handle of the buffer to have its tiling state updated */ - __u32 handle; - - /** - * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, - * I915_TILING_Y). - * - * This value is to be set on request, and will be updated by the - * kernel on successful return with the actual chosen tiling layout. - * - * The tiling mode may be demoted to I915_TILING_NONE when the system - * has bit 6 swizzling that can't be managed correctly by GEM. - * - * Buffer contents become undefined when changing tiling_mode. - */ - __u32 tiling_mode; - - /** - * Stride in bytes for the object when in I915_TILING_X or - * I915_TILING_Y. - */ - __u32 stride; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping. - */ - __u32 swizzle_mode; -}; - -struct drm_i915_gem_get_tiling { - /** Handle of the buffer to get tiling state for. */ - __u32 handle; - - /** - * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, - * I915_TILING_Y). - */ - __u32 tiling_mode; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping. - */ - __u32 swizzle_mode; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping whilst bound. - */ - __u32 phys_swizzle_mode; -}; - -struct drm_i915_gem_get_aperture { - /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ - __u64 aper_size; - - /** - * Available space in the aperture used by i915_gem_execbuffer, in - * bytes - */ - __u64 aper_available_size; -}; - -struct drm_i915_get_pipe_from_crtc_id { - /** ID of CRTC being requested **/ - __u32 crtc_id; - - /** pipe of requested CRTC **/ - __u32 pipe; -}; - -#define I915_MADV_WILLNEED 0 -#define I915_MADV_DONTNEED 1 -#define __I915_MADV_PURGED 2 /* internal state */ - -struct drm_i915_gem_madvise { - /** Handle of the buffer to change the backing store advice */ - __u32 handle; - - /* Advice: either the buffer will be needed again in the near future, - * or wont be and could be discarded under memory pressure. - */ - __u32 madv; - - /** Whether the backing store still exists. */ - __u32 retained; -}; - -/* flags */ -#define I915_OVERLAY_TYPE_MASK 0xff -#define I915_OVERLAY_YUV_PLANAR 0x01 -#define I915_OVERLAY_YUV_PACKED 0x02 -#define I915_OVERLAY_RGB 0x03 - -#define I915_OVERLAY_DEPTH_MASK 0xff00 -#define I915_OVERLAY_RGB24 0x1000 -#define I915_OVERLAY_RGB16 0x2000 -#define I915_OVERLAY_RGB15 0x3000 -#define I915_OVERLAY_YUV422 0x0100 -#define I915_OVERLAY_YUV411 0x0200 -#define I915_OVERLAY_YUV420 0x0300 -#define I915_OVERLAY_YUV410 0x0400 - -#define I915_OVERLAY_SWAP_MASK 0xff0000 -#define I915_OVERLAY_NO_SWAP 0x000000 -#define I915_OVERLAY_UV_SWAP 0x010000 -#define I915_OVERLAY_Y_SWAP 0x020000 -#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 - -#define I915_OVERLAY_FLAGS_MASK 0xff000000 -#define I915_OVERLAY_ENABLE 0x01000000 - -struct drm_intel_overlay_put_image { - /* various flags and src format description */ - __u32 flags; - /* source picture description */ - __u32 bo_handle; - /* stride values and offsets are in bytes, buffer relative */ - __u16 stride_Y; /* stride for packed formats */ - __u16 stride_UV; - __u32 offset_Y; /* offset for packet formats */ - __u32 offset_U; - __u32 offset_V; - /* in pixels */ - __u16 src_width; - __u16 src_height; - /* to compensate the scaling factors for partially covered surfaces */ - __u16 src_scan_width; - __u16 src_scan_height; - /* output crtc description */ - __u32 crtc_id; - __u16 dst_x; - __u16 dst_y; - __u16 dst_width; - __u16 dst_height; -}; - -/* flags */ -#define I915_OVERLAY_UPDATE_ATTRS (1<<0) -#define I915_OVERLAY_UPDATE_GAMMA (1<<1) -#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) -struct drm_intel_overlay_attrs { - __u32 flags; - __u32 color_key; - __s32 brightness; - __u32 contrast; - __u32 saturation; - __u32 gamma0; - __u32 gamma1; - __u32 gamma2; - __u32 gamma3; - __u32 gamma4; - __u32 gamma5; -}; - -/* - * Intel sprite handling - * - * Color keying works with a min/mask/max tuple. Both source and destination - * color keying is allowed. - * - * Source keying: - * Sprite pixels within the min & max values, masked against the color channels - * specified in the mask field, will be transparent. All other pixels will - * be displayed on top of the primary plane. For RGB surfaces, only the min - * and mask fields will be used; ranged compares are not allowed. - * - * Destination keying: - * Primary plane pixels that match the min value, masked against the color - * channels specified in the mask field, will be replaced by corresponding - * pixels from the sprite plane. - * - * Note that source & destination keying are exclusive; only one can be - * active on a given plane. - */ - -#define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set - * flags==0 to disable colorkeying. - */ -#define I915_SET_COLORKEY_DESTINATION (1<<1) -#define I915_SET_COLORKEY_SOURCE (1<<2) -struct drm_intel_sprite_colorkey { - __u32 plane_id; - __u32 min_value; - __u32 channel_mask; - __u32 max_value; - __u32 flags; -}; - -struct drm_i915_gem_wait { - /** Handle of BO we shall wait on */ - __u32 bo_handle; - __u32 flags; - /** Number of nanoseconds to wait, Returns time remaining. */ - __s64 timeout_ns; -}; - -struct drm_i915_gem_context_create { - __u32 ctx_id; /* output: id of new context*/ - __u32 pad; -}; - -struct drm_i915_gem_context_create_ext { - __u32 ctx_id; /* output: id of new context*/ - __u32 flags; -#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) -#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) -#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \ - (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) - __u64 extensions; -}; - -struct drm_i915_gem_context_param { - __u32 ctx_id; - __u32 size; - __u64 param; -#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 -/* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance - * someone somewhere has attempted to use it, never re-use this context - * param number. - */ -#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 -#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 -#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 -#define I915_CONTEXT_PARAM_BANNABLE 0x5 -#define I915_CONTEXT_PARAM_PRIORITY 0x6 -#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ -#define I915_CONTEXT_DEFAULT_PRIORITY 0 -#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ - /* - * When using the following param, value should be a pointer to - * drm_i915_gem_context_param_sseu. - */ -#define I915_CONTEXT_PARAM_SSEU 0x7 - -/* - * Not all clients may want to attempt automatic recover of a context after - * a hang (for example, some clients may only submit very small incremental - * batches relying on known logical state of previous batches which will never - * recover correctly and each attempt will hang), and so would prefer that - * the context is forever banned instead. - * - * If set to false (0), after a reset, subsequent (and in flight) rendering - * from this context is discarded, and the client will need to create a new - * context to use instead. - * - * If set to true (1), the kernel will automatically attempt to recover the - * context by skipping the hanging batch and executing the next batch starting - * from the default context state (discarding the incomplete logical context - * state lost due to the reset). - * - * On creation, all new contexts are marked as recoverable. - */ -#define I915_CONTEXT_PARAM_RECOVERABLE 0x8 - - /* - * The id of the associated virtual memory address space (ppGTT) of - * this context. Can be retrieved and passed to another context - * (on the same fd) for both to use the same ppGTT and so share - * address layouts, and avoid reloading the page tables on context - * switches between themselves. - * - * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY. - */ -#define I915_CONTEXT_PARAM_VM 0x9 - -/* - * I915_CONTEXT_PARAM_ENGINES: - * - * Bind this context to operate on this subset of available engines. Henceforth, - * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as - * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0] - * and upwards. Slots 0...N are filled in using the specified (class, instance). - * Use - * engine_class: I915_ENGINE_CLASS_INVALID, - * engine_instance: I915_ENGINE_CLASS_INVALID_NONE - * to specify a gap in the array that can be filled in later, e.g. by a - * virtual engine used for load balancing. - * - * Setting the number of engines bound to the context to 0, by passing a zero - * sized argument, will revert back to default settings. - * - * See struct i915_context_param_engines. - * - * Extensions: - * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE) - * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND) - */ -#define I915_CONTEXT_PARAM_ENGINES 0xa - -/* - * I915_CONTEXT_PARAM_PERSISTENCE: - * - * Allow the context and active rendering to survive the process until - * completion. Persistence allows fire-and-forget clients to queue up a - * bunch of work, hand the output over to a display server and then quit. - * If the context is marked as not persistent, upon closing (either via - * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure - * or process termination), the context and any outstanding requests will be - * cancelled (and exported fences for cancelled requests marked as -EIO). - * - * By default, new contexts allow persistence. - */ -#define I915_CONTEXT_PARAM_PERSISTENCE 0xb - -/* This API has been removed. On the off chance someone somewhere has - * attempted to use it, never re-use this context param number. - */ -#define I915_CONTEXT_PARAM_RINGSIZE 0xc -/* Must be kept compact -- no holes and well documented */ - - __u64 value; -}; - -/* - * Context SSEU programming - * - * It may be necessary for either functional or performance reason to configure - * a context to run with a reduced number of SSEU (where SSEU stands for Slice/ - * Sub-slice/EU). - * - * This is done by configuring SSEU configuration using the below - * @struct drm_i915_gem_context_param_sseu for every supported engine which - * userspace intends to use. - * - * Not all GPUs or engines support this functionality in which case an error - * code -ENODEV will be returned. - * - * Also, flexibility of possible SSEU configuration permutations varies between - * GPU generations and software imposed limitations. Requesting such a - * combination will return an error code of -EINVAL. - * - * NOTE: When perf/OA is active the context's SSEU configuration is ignored in - * favour of a single global setting. - */ -struct drm_i915_gem_context_param_sseu { - /* - * Engine class & instance to be configured or queried. - */ - struct i915_engine_class_instance engine; - - /* - * Unknown flags must be cleared to zero. - */ - __u32 flags; -#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) - - /* - * Mask of slices to enable for the context. Valid values are a subset - * of the bitmask value returned for I915_PARAM_SLICE_MASK. - */ - __u64 slice_mask; - - /* - * Mask of subslices to enable for the context. Valid values are a - * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK. - */ - __u64 subslice_mask; - - /* - * Minimum/Maximum number of EUs to enable per subslice for the - * context. min_eus_per_subslice must be inferior or equal to - * max_eus_per_subslice. - */ - __u16 min_eus_per_subslice; - __u16 max_eus_per_subslice; - - /* - * Unused for now. Must be cleared to zero. - */ - __u32 rsvd; -}; - -/** - * DOC: Virtual Engine uAPI - * - * Virtual engine is a concept where userspace is able to configure a set of - * physical engines, submit a batch buffer, and let the driver execute it on any - * engine from the set as it sees fit. - * - * This is primarily useful on parts which have multiple instances of a same - * class engine, like for example GT3+ Skylake parts with their two VCS engines. - * - * For instance userspace can enumerate all engines of a certain class using the - * previously described `Engine Discovery uAPI`_. After that userspace can - * create a GEM context with a placeholder slot for the virtual engine (using - * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class - * and instance respectively) and finally using the - * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in - * the same reserved slot. - * - * Example of creating a virtual engine and submitting a batch buffer to it: - * - * .. code-block:: C - * - * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { - * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, - * .engine_index = 0, // Place this virtual engine into engine map slot 0 - * .num_siblings = 2, - * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, - * { I915_ENGINE_CLASS_VIDEO, 1 }, }, - * }; - * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { - * .engines = { { I915_ENGINE_CLASS_INVALID, - * I915_ENGINE_CLASS_INVALID_NONE } }, - * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension - * }; - * struct drm_i915_gem_context_create_ext_setparam p_engines = { - * .base = { - * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, - * }, - * .param = { - * .param = I915_CONTEXT_PARAM_ENGINES, - * .value = to_user_pointer(&engines), - * .size = sizeof(engines), - * }, - * }; - * struct drm_i915_gem_context_create_ext create = { - * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, - * .extensions = to_user_pointer(&p_engines); - * }; - * - * ctx_id = gem_context_create_ext(drm_fd, &create); - * - * // Now we have created a GEM context with its engine map containing a - * // single virtual engine. Submissions to this slot can go either to - * // vcs0 or vcs1, depending on the load balancing algorithm used inside - * // the driver. The load balancing is dynamic from one batch buffer to - * // another and transparent to userspace. - * - * ... - * execbuf.rsvd1 = ctx_id; - * execbuf.flags = 0; // Submits to index 0 which is the virtual engine - * gem_execbuf(drm_fd, &execbuf); - */ - -/* - * i915_context_engines_load_balance: - * - * Enable load balancing across this set of engines. - * - * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when - * used will proxy the execbuffer request onto one of the set of engines - * in such a way as to distribute the load evenly across the set. - * - * The set of engines must be compatible (e.g. the same HW class) as they - * will share the same logical GPU context and ring. - * - * To intermix rendering with the virtual engine and direct rendering onto - * the backing engines (bypassing the load balancing proxy), the context must - * be defined to use a single timeline for all engines. - */ -struct i915_context_engines_load_balance { - struct i915_user_extension base; - - __u16 engine_index; - __u16 num_siblings; - __u32 flags; /* all undefined flags must be zero */ - - __u64 mbz64; /* reserved for future use; must be zero */ - - struct i915_engine_class_instance engines[0]; -} __attribute__((packed)); - -#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \ - struct i915_user_extension base; \ - __u16 engine_index; \ - __u16 num_siblings; \ - __u32 flags; \ - __u64 mbz64; \ - struct i915_engine_class_instance engines[N__]; \ -} __attribute__((packed)) name__ - -/* - * i915_context_engines_bond: - * - * Constructed bonded pairs for execution within a virtual engine. - * - * All engines are equal, but some are more equal than others. Given - * the distribution of resources in the HW, it may be preferable to run - * a request on a given subset of engines in parallel to a request on a - * specific engine. We enable this selection of engines within a virtual - * engine by specifying bonding pairs, for any given master engine we will - * only execute on one of the corresponding siblings within the virtual engine. - * - * To execute a request in parallel on the master engine and a sibling requires - * coordination with a I915_EXEC_FENCE_SUBMIT. - */ -struct i915_context_engines_bond { - struct i915_user_extension base; - - struct i915_engine_class_instance master; - - __u16 virtual_index; /* index of virtual engine in ctx->engines[] */ - __u16 num_bonds; - - __u64 flags; /* all undefined flags must be zero */ - __u64 mbz64[4]; /* reserved for future use; must be zero */ - - struct i915_engine_class_instance engines[0]; -} __attribute__((packed)); - -#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \ - struct i915_user_extension base; \ - struct i915_engine_class_instance master; \ - __u16 virtual_index; \ - __u16 num_bonds; \ - __u64 flags; \ - __u64 mbz64[4]; \ - struct i915_engine_class_instance engines[N__]; \ -} __attribute__((packed)) name__ - -/** - * DOC: Context Engine Map uAPI - * - * Context engine map is a new way of addressing engines when submitting batch- - * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` - * inside the flags field of `struct drm_i915_gem_execbuffer2`. - * - * To use it created GEM contexts need to be configured with a list of engines - * the user is intending to submit to. This is accomplished using the - * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct - * i915_context_param_engines`. - * - * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the - * configured map. - * - * Example of creating such context and submitting against it: - * - * .. code-block:: C - * - * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { - * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, - * { I915_ENGINE_CLASS_COPY, 0 } } - * }; - * struct drm_i915_gem_context_create_ext_setparam p_engines = { - * .base = { - * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, - * }, - * .param = { - * .param = I915_CONTEXT_PARAM_ENGINES, - * .value = to_user_pointer(&engines), - * .size = sizeof(engines), - * }, - * }; - * struct drm_i915_gem_context_create_ext create = { - * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, - * .extensions = to_user_pointer(&p_engines); - * }; - * - * ctx_id = gem_context_create_ext(drm_fd, &create); - * - * // We have now created a GEM context with two engines in the map: - * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines - * // will not be accessible from this context. - * - * ... - * execbuf.rsvd1 = ctx_id; - * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context - * gem_execbuf(drm_fd, &execbuf); - * - * ... - * execbuf.rsvd1 = ctx_id; - * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context - * gem_execbuf(drm_fd, &execbuf); - */ - -struct i915_context_param_engines { - __u64 extensions; /* linked chain of extension blocks, 0 terminates */ -#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ -#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */ - struct i915_engine_class_instance engines[0]; -} __attribute__((packed)); - -#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \ - __u64 extensions; \ - struct i915_engine_class_instance engines[N__]; \ -} __attribute__((packed)) name__ - -struct drm_i915_gem_context_create_ext_setparam { -#define I915_CONTEXT_CREATE_EXT_SETPARAM 0 - struct i915_user_extension base; - struct drm_i915_gem_context_param param; -}; - -/* This API has been removed. On the off chance someone somewhere has - * attempted to use it, never re-use this extension number. - */ -#define I915_CONTEXT_CREATE_EXT_CLONE 1 - -struct drm_i915_gem_context_destroy { - __u32 ctx_id; - __u32 pad; -}; - -/* - * DRM_I915_GEM_VM_CREATE - - * - * Create a new virtual memory address space (ppGTT) for use within a context - * on the same file. Extensions can be provided to configure exactly how the - * address space is setup upon creation. - * - * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is - * returned in the outparam @id. - * - * No flags are defined, with all bits reserved and must be zero. - * - * An extension chain maybe provided, starting with @extensions, and terminated - * by the @next_extension being 0. Currently, no extensions are defined. - * - * DRM_I915_GEM_VM_DESTROY - - * - * Destroys a previously created VM id, specified in @id. - * - * No extensions or flags are allowed currently, and so must be zero. - */ -struct drm_i915_gem_vm_control { - __u64 extensions; - __u32 flags; - __u32 vm_id; -}; - -struct drm_i915_reg_read { - /* - * Register offset. - * For 64bit wide registers where the upper 32bits don't immediately - * follow the lower 32bits, the offset of the lower 32bits must - * be specified - */ - __u64 offset; -#define I915_REG_READ_8B_WA (1ul << 0) - - __u64 val; /* Return value */ -}; - -/* Known registers: - * - * Render engine timestamp - 0x2358 + 64bit - gen7+ - * - Note this register returns an invalid value if using the default - * single instruction 8byte read, in order to workaround that pass - * flag I915_REG_READ_8B_WA in offset field. - * - */ - -struct drm_i915_reset_stats { - __u32 ctx_id; - __u32 flags; - - /* All resets since boot/module reload, for all contexts */ - __u32 reset_count; - - /* Number of batches lost when active in GPU, for this context */ - __u32 batch_active; - - /* Number of batches lost pending for execution, for this context */ - __u32 batch_pending; - - __u32 pad; -}; - -/** - * struct drm_i915_gem_userptr - Create GEM object from user allocated memory. - * - * Userptr objects have several restrictions on what ioctls can be used with the - * object handle. - */ -struct drm_i915_gem_userptr { - /** - * @user_ptr: The pointer to the allocated memory. - * - * Needs to be aligned to PAGE_SIZE. - */ - __u64 user_ptr; - - /** - * @user_size: - * - * The size in bytes for the allocated memory. This will also become the - * object size. - * - * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, - * or larger. - */ - __u64 user_size; - - /** - * @flags: - * - * Supported flags: - * - * I915_USERPTR_READ_ONLY: - * - * Mark the object as readonly, this also means GPU access can only be - * readonly. This is only supported on HW which supports readonly access - * through the GTT. If the HW can't support readonly access, an error is - * returned. - * - * I915_USERPTR_PROBE: - * - * Probe the provided @user_ptr range and validate that the @user_ptr is - * indeed pointing to normal memory and that the range is also valid. - * For example if some garbage address is given to the kernel, then this - * should complain. - * - * Returns -EFAULT if the probe failed. - * - * Note that this doesn't populate the backing pages, and also doesn't - * guarantee that the object will remain valid when the object is - * eventually used. - * - * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE - * returns a non-zero value. - * - * I915_USERPTR_UNSYNCHRONIZED: - * - * NOT USED. Setting this flag will result in an error. - */ - __u32 flags; -#define I915_USERPTR_READ_ONLY 0x1 -#define I915_USERPTR_PROBE 0x2 -#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 - /** - * @handle: Returned handle for the object. - * - * Object handles are nonzero. - */ - __u32 handle; -}; - -enum drm_i915_oa_format { - I915_OA_FORMAT_A13 = 1, /* HSW only */ - I915_OA_FORMAT_A29, /* HSW only */ - I915_OA_FORMAT_A13_B8_C8, /* HSW only */ - I915_OA_FORMAT_B4_C8, /* HSW only */ - I915_OA_FORMAT_A45_B8_C8, /* HSW only */ - I915_OA_FORMAT_B4_C8_A16, /* HSW only */ - I915_OA_FORMAT_C4_B8, /* HSW+ */ - - /* Gen8+ */ - I915_OA_FORMAT_A12, - I915_OA_FORMAT_A12_B8_C8, - I915_OA_FORMAT_A32u40_A4u32_B8_C8, - - I915_OA_FORMAT_MAX /* non-ABI */ -}; - -enum drm_i915_perf_property_id { - /** - * Open the stream for a specific context handle (as used with - * execbuffer2). A stream opened for a specific context this way - * won't typically require root privileges. - * - * This property is available in perf revision 1. - */ - DRM_I915_PERF_PROP_CTX_HANDLE = 1, - - /** - * A value of 1 requests the inclusion of raw OA unit reports as - * part of stream samples. - * - * This property is available in perf revision 1. - */ - DRM_I915_PERF_PROP_SAMPLE_OA, - - /** - * The value specifies which set of OA unit metrics should be - * configured, defining the contents of any OA unit reports. - * - * This property is available in perf revision 1. - */ - DRM_I915_PERF_PROP_OA_METRICS_SET, - - /** - * The value specifies the size and layout of OA unit reports. - * - * This property is available in perf revision 1. - */ - DRM_I915_PERF_PROP_OA_FORMAT, - - /** - * Specifying this property implicitly requests periodic OA unit - * sampling and (at least on Haswell) the sampling frequency is derived - * from this exponent as follows: - * - * 80ns * 2^(period_exponent + 1) - * - * This property is available in perf revision 1. - */ - DRM_I915_PERF_PROP_OA_EXPONENT, - - /** - * Specifying this property is only valid when specify a context to - * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property - * will hold preemption of the particular context we want to gather - * performance data about. The execbuf2 submissions must include a - * drm_i915_gem_execbuffer_ext_perf parameter for this to apply. - * - * This property is available in perf revision 3. - */ - DRM_I915_PERF_PROP_HOLD_PREEMPTION, - - /** - * Specifying this pins all contexts to the specified SSEU power - * configuration for the duration of the recording. - * - * This parameter's value is a pointer to a struct - * drm_i915_gem_context_param_sseu. - * - * This property is available in perf revision 4. - */ - DRM_I915_PERF_PROP_GLOBAL_SSEU, - - /** - * This optional parameter specifies the timer interval in nanoseconds - * at which the i915 driver will check the OA buffer for available data. - * Minimum allowed value is 100 microseconds. A default value is used by - * the driver if this parameter is not specified. Note that larger timer - * values will reduce cpu consumption during OA perf captures. However, - * excessively large values would potentially result in OA buffer - * overwrites as captures reach end of the OA buffer. - * - * This property is available in perf revision 5. - */ - DRM_I915_PERF_PROP_POLL_OA_PERIOD, - - DRM_I915_PERF_PROP_MAX /* non-ABI */ -}; - -struct drm_i915_perf_open_param { - __u32 flags; -#define I915_PERF_FLAG_FD_CLOEXEC (1<<0) -#define I915_PERF_FLAG_FD_NONBLOCK (1<<1) -#define I915_PERF_FLAG_DISABLED (1<<2) - - /** The number of u64 (id, value) pairs */ - __u32 num_properties; - - /** - * Pointer to array of u64 (id, value) pairs configuring the stream - * to open. - */ - __u64 properties_ptr; -}; - -/* - * Enable data capture for a stream that was either opened in a disabled state - * via I915_PERF_FLAG_DISABLED or was later disabled via - * I915_PERF_IOCTL_DISABLE. - * - * It is intended to be cheaper to disable and enable a stream than it may be - * to close and re-open a stream with the same configuration. - * - * It's undefined whether any pending data for the stream will be lost. - * - * This ioctl is available in perf revision 1. - */ -#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) - -/* - * Disable data capture for a stream. - * - * It is an error to try and read a stream that is disabled. - * - * This ioctl is available in perf revision 1. - */ -#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) - -/* - * Change metrics_set captured by a stream. - * - * If the stream is bound to a specific context, the configuration change - * will performed inline with that context such that it takes effect before - * the next execbuf submission. - * - * Returns the previously bound metrics set id, or a negative error code. - * - * This ioctl is available in perf revision 2. - */ -#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2) - -/* - * Common to all i915 perf records - */ -struct drm_i915_perf_record_header { - __u32 type; - __u16 pad; - __u16 size; -}; - -enum drm_i915_perf_record_type { - - /** - * Samples are the work horse record type whose contents are extensible - * and defined when opening an i915 perf stream based on the given - * properties. - * - * Boolean properties following the naming convention - * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in - * every sample. - * - * The order of these sample properties given by userspace has no - * affect on the ordering of data within a sample. The order is - * documented here. - * - * struct { - * struct drm_i915_perf_record_header header; - * - * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA - * }; - */ - DRM_I915_PERF_RECORD_SAMPLE = 1, - - /* - * Indicates that one or more OA reports were not written by the - * hardware. This can happen for example if an MI_REPORT_PERF_COUNT - * command collides with periodic sampling - which would be more likely - * at higher sampling frequencies. - */ - DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, - - /** - * An error occurred that resulted in all pending OA reports being lost. - */ - DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, - - DRM_I915_PERF_RECORD_MAX /* non-ABI */ -}; - -/* - * Structure to upload perf dynamic configuration into the kernel. - */ -struct drm_i915_perf_oa_config { - /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ - char uuid[36]; - - __u32 n_mux_regs; - __u32 n_boolean_regs; - __u32 n_flex_regs; - - /* - * These fields are pointers to tuples of u32 values (register address, - * value). For example the expected length of the buffer pointed by - * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). - */ - __u64 mux_regs_ptr; - __u64 boolean_regs_ptr; - __u64 flex_regs_ptr; -}; - -/** - * struct drm_i915_query_item - An individual query for the kernel to process. - * - * The behaviour is determined by the @query_id. Note that exactly what - * @data_ptr is also depends on the specific @query_id. - */ -struct drm_i915_query_item { - /** @query_id: The id for this query */ - __u64 query_id; -#define DRM_I915_QUERY_TOPOLOGY_INFO 1 -#define DRM_I915_QUERY_ENGINE_INFO 2 -#define DRM_I915_QUERY_PERF_CONFIG 3 -#define DRM_I915_QUERY_MEMORY_REGIONS 4 -/* Must be kept compact -- no holes and well documented */ - - /** - * @length: - * - * When set to zero by userspace, this is filled with the size of the - * data to be written at the @data_ptr pointer. The kernel sets this - * value to a negative value to signal an error on a particular query - * item. - */ - __s32 length; - - /** - * @flags: - * - * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0. - * - * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the - * following: - * - * - DRM_I915_QUERY_PERF_CONFIG_LIST - * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID - * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID - */ - __u32 flags; -#define DRM_I915_QUERY_PERF_CONFIG_LIST 1 -#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2 -#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3 - - /** - * @data_ptr: - * - * Data will be written at the location pointed by @data_ptr when the - * value of @length matches the length of the data to be written by the - * kernel. - */ - __u64 data_ptr; -}; - -/** - * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the - * kernel to fill out. - * - * Note that this is generally a two step process for each struct - * drm_i915_query_item in the array: - * - * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct - * drm_i915_query_item, with &drm_i915_query_item.length set to zero. The - * kernel will then fill in the size, in bytes, which tells userspace how - * memory it needs to allocate for the blob(say for an array of properties). - * - * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the - * &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that - * the &drm_i915_query_item.length should still be the same as what the - * kernel previously set. At this point the kernel can fill in the blob. - * - * Note that for some query items it can make sense for userspace to just pass - * in a buffer/blob equal to or larger than the required size. In this case only - * a single ioctl call is needed. For some smaller query items this can work - * quite well. - * - */ -struct drm_i915_query { - /** @num_items: The number of elements in the @items_ptr array */ - __u32 num_items; - - /** - * @flags: Unused for now. Must be cleared to zero. - */ - __u32 flags; - - /** - * @items_ptr: - * - * Pointer to an array of struct drm_i915_query_item. The number of - * array elements is @num_items. - */ - __u64 items_ptr; -}; - -/* - * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO : - * - * data: contains the 3 pieces of information : - * - * - the slice mask with one bit per slice telling whether a slice is - * available. The availability of slice X can be queried with the following - * formula : - * - * (data[X / 8] >> (X % 8)) & 1 - * - * - the subslice mask for each slice with one bit per subslice telling - * whether a subslice is available. Gen12 has dual-subslices, which are - * similar to two gen11 subslices. For gen12, this array represents dual- - * subslices. The availability of subslice Y in slice X can be queried - * with the following formula : - * - * (data[subslice_offset + - * X * subslice_stride + - * Y / 8] >> (Y % 8)) & 1 - * - * - the EU mask for each subslice in each slice with one bit per EU telling - * whether an EU is available. The availability of EU Z in subslice Y in - * slice X can be queried with the following formula : - * - * (data[eu_offset + - * (X * max_subslices + Y) * eu_stride + - * Z / 8] >> (Z % 8)) & 1 - */ -struct drm_i915_query_topology_info { - /* - * Unused for now. Must be cleared to zero. - */ - __u16 flags; - - __u16 max_slices; - __u16 max_subslices; - __u16 max_eus_per_subslice; - - /* - * Offset in data[] at which the subslice masks are stored. - */ - __u16 subslice_offset; - - /* - * Stride at which each of the subslice masks for each slice are - * stored. - */ - __u16 subslice_stride; - - /* - * Offset in data[] at which the EU masks are stored. - */ - __u16 eu_offset; - - /* - * Stride at which each of the EU masks for each subslice are stored. - */ - __u16 eu_stride; - - __u8 data[]; -}; - -/** - * DOC: Engine Discovery uAPI - * - * Engine discovery uAPI is a way of enumerating physical engines present in a - * GPU associated with an open i915 DRM file descriptor. This supersedes the old - * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like - * `I915_PARAM_HAS_BLT`. - * - * The need for this interface came starting with Icelake and newer GPUs, which - * started to establish a pattern of having multiple engines of a same class, - * where not all instances were always completely functionally equivalent. - * - * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the - * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. - * - * Example for getting the list of engines: - * - * .. code-block:: C - * - * struct drm_i915_query_engine_info *info; - * struct drm_i915_query_item item = { - * .query_id = DRM_I915_QUERY_ENGINE_INFO; - * }; - * struct drm_i915_query query = { - * .num_items = 1, - * .items_ptr = (uintptr_t)&item, - * }; - * int err, i; - * - * // First query the size of the blob we need, this needs to be large - * // enough to hold our array of engines. The kernel will fill out the - * // item.length for us, which is the number of bytes we need. - * // - * // Alternatively a large buffer can be allocated straight away enabling - * // querying in one pass, in which case item.length should contain the - * // length of the provided buffer. - * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); - * if (err) ... - * - * info = calloc(1, item.length); - * // Now that we allocated the required number of bytes, we call the ioctl - * // again, this time with the data_ptr pointing to our newly allocated - * // blob, which the kernel can then populate with info on all engines. - * item.data_ptr = (uintptr_t)&info, - * - * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); - * if (err) ... - * - * // We can now access each engine in the array - * for (i = 0; i < info->num_engines; i++) { - * struct drm_i915_engine_info einfo = info->engines[i]; - * u16 class = einfo.engine.class; - * u16 instance = einfo.engine.instance; - * .... - * } - * - * free(info); - * - * Each of the enumerated engines, apart from being defined by its class and - * instance (see `struct i915_engine_class_instance`), also can have flags and - * capabilities defined as documented in i915_drm.h. - * - * For instance video engines which support HEVC encoding will have the - * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. - * - * Engine discovery only fully comes to its own when combined with the new way - * of addressing engines when submitting batch buffers using contexts with - * engine maps configured. - */ - -/** - * struct drm_i915_engine_info - * - * Describes one engine and it's capabilities as known to the driver. - */ -struct drm_i915_engine_info { - /** @engine: Engine class and instance. */ - struct i915_engine_class_instance engine; - - /** @rsvd0: Reserved field. */ - __u32 rsvd0; - - /** @flags: Engine flags. */ - __u64 flags; - - /** @capabilities: Capabilities of this engine. */ - __u64 capabilities; -#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) -#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) - - /** @rsvd1: Reserved fields. */ - __u64 rsvd1[4]; -}; - -/** - * struct drm_i915_query_engine_info - * - * Engine info query enumerates all engines known to the driver by filling in - * an array of struct drm_i915_engine_info structures. - */ -struct drm_i915_query_engine_info { - /** @num_engines: Number of struct drm_i915_engine_info structs following. */ - __u32 num_engines; - - /** @rsvd: MBZ */ - __u32 rsvd[3]; - - /** @engines: Marker for drm_i915_engine_info structures. */ - struct drm_i915_engine_info engines[]; -}; - -/* - * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG. - */ -struct drm_i915_query_perf_config { - union { - /* - * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets - * this fields to the number of configurations available. - */ - __u64 n_configs; - - /* - * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, - * i915 will use the value in this field as configuration - * identifier to decide what data to write into config_ptr. - */ - __u64 config; - - /* - * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, - * i915 will use the value in this field as configuration - * identifier to decide what data to write into config_ptr. - * - * String formatted like "%08x-%04x-%04x-%04x-%012x" - */ - char uuid[36]; - }; - - /* - * Unused for now. Must be cleared to zero. - */ - __u32 flags; - - /* - * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will - * write an array of __u64 of configuration identifiers. - * - * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will - * write a struct drm_i915_perf_oa_config. If the following fields of - * drm_i915_perf_oa_config are set not set to 0, i915 will write into - * the associated pointers the values of submitted when the - * configuration was created : - * - * - n_mux_regs - * - n_boolean_regs - * - n_flex_regs - */ - __u8 data[]; -}; - -/** - * enum drm_i915_gem_memory_class - Supported memory classes - */ -enum drm_i915_gem_memory_class { - /** @I915_MEMORY_CLASS_SYSTEM: System memory */ - I915_MEMORY_CLASS_SYSTEM = 0, - /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */ - I915_MEMORY_CLASS_DEVICE, -}; - -/** - * struct drm_i915_gem_memory_class_instance - Identify particular memory region - */ -struct drm_i915_gem_memory_class_instance { - /** @memory_class: See enum drm_i915_gem_memory_class */ - __u16 memory_class; - - /** @memory_instance: Which instance */ - __u16 memory_instance; -}; - -/** - * struct drm_i915_memory_region_info - Describes one region as known to the - * driver. - * - * Note that we reserve some stuff here for potential future work. As an example - * we might want expose the capabilities for a given region, which could include - * things like if the region is CPU mappable/accessible, what are the supported - * mapping types etc. - * - * Note that to extend struct drm_i915_memory_region_info and struct - * drm_i915_query_memory_regions in the future the plan is to do the following: - * - * .. code-block:: C - * - * struct drm_i915_memory_region_info { - * struct drm_i915_gem_memory_class_instance region; - * union { - * __u32 rsvd0; - * __u32 new_thing1; - * }; - * ... - * union { - * __u64 rsvd1[8]; - * struct { - * __u64 new_thing2; - * __u64 new_thing3; - * ... - * }; - * }; - * }; - * - * With this things should remain source compatible between versions for - * userspace, even as we add new fields. - * - * Note this is using both struct drm_i915_query_item and struct drm_i915_query. - * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS - * at &drm_i915_query_item.query_id. - */ -struct drm_i915_memory_region_info { - /** @region: The class:instance pair encoding */ - struct drm_i915_gem_memory_class_instance region; - - /** @rsvd0: MBZ */ - __u32 rsvd0; - - /** @probed_size: Memory probed by the driver (-1 = unknown) */ - __u64 probed_size; - - /** @unallocated_size: Estimate of memory remaining (-1 = unknown) */ - __u64 unallocated_size; - - /** @rsvd1: MBZ */ - __u64 rsvd1[8]; -}; - -/** - * struct drm_i915_query_memory_regions - * - * The region info query enumerates all regions known to the driver by filling - * in an array of struct drm_i915_memory_region_info structures. - * - * Example for getting the list of supported regions: - * - * .. code-block:: C - * - * struct drm_i915_query_memory_regions *info; - * struct drm_i915_query_item item = { - * .query_id = DRM_I915_QUERY_MEMORY_REGIONS; - * }; - * struct drm_i915_query query = { - * .num_items = 1, - * .items_ptr = (uintptr_t)&item, - * }; - * int err, i; - * - * // First query the size of the blob we need, this needs to be large - * // enough to hold our array of regions. The kernel will fill out the - * // item.length for us, which is the number of bytes we need. - * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); - * if (err) ... - * - * info = calloc(1, item.length); - * // Now that we allocated the required number of bytes, we call the ioctl - * // again, this time with the data_ptr pointing to our newly allocated - * // blob, which the kernel can then populate with the all the region info. - * item.data_ptr = (uintptr_t)&info, - * - * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); - * if (err) ... - * - * // We can now access each region in the array - * for (i = 0; i < info->num_regions; i++) { - * struct drm_i915_memory_region_info mr = info->regions[i]; - * u16 class = mr.region.class; - * u16 instance = mr.region.instance; - * - * .... - * } - * - * free(info); - */ -struct drm_i915_query_memory_regions { - /** @num_regions: Number of supported regions */ - __u32 num_regions; - - /** @rsvd: MBZ */ - __u32 rsvd[3]; - - /** @regions: Info about each supported region */ - struct drm_i915_memory_region_info regions[]; -}; - -/** - * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added - * extension support using struct i915_user_extension. - * - * Note that in the future we want to have our buffer flags here, at least for - * the stuff that is immutable. Previously we would have two ioctls, one to - * create the object with gem_create, and another to apply various parameters, - * however this creates some ambiguity for the params which are considered - * immutable. Also in general we're phasing out the various SET/GET ioctls. - */ -struct drm_i915_gem_create_ext { - /** - * @size: Requested size for the object. - * - * The (page-aligned) allocated size for the object will be returned. - * - * Note that for some devices we have might have further minimum - * page-size restrictions(larger than 4K), like for device local-memory. - * However in general the final size here should always reflect any - * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS - * extension to place the object in device local-memory. - */ - __u64 size; - /** - * @handle: Returned handle for the object. - * - * Object handles are nonzero. - */ - __u32 handle; - /** @flags: MBZ */ - __u32 flags; - /** - * @extensions: The chain of extensions to apply to this object. - * - * This will be useful in the future when we need to support several - * different extensions, and we need to apply more than one when - * creating the object. See struct i915_user_extension. - * - * If we don't supply any extensions then we get the same old gem_create - * behaviour. - * - * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see - * struct drm_i915_gem_create_ext_memory_regions. - */ -#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 - __u64 extensions; -}; - -/** - * struct drm_i915_gem_create_ext_memory_regions - The - * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension. - * - * Set the object with the desired set of placements/regions in priority - * order. Each entry must be unique and supported by the device. - * - * This is provided as an array of struct drm_i915_gem_memory_class_instance, or - * an equivalent layout of class:instance pair encodings. See struct - * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to - * query the supported regions for a device. - * - * As an example, on discrete devices, if we wish to set the placement as - * device local-memory we can do something like: - * - * .. code-block:: C - * - * struct drm_i915_gem_memory_class_instance region_lmem = { - * .memory_class = I915_MEMORY_CLASS_DEVICE, - * .memory_instance = 0, - * }; - * struct drm_i915_gem_create_ext_memory_regions regions = { - * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, - * .regions = (uintptr_t)®ion_lmem, - * .num_regions = 1, - * }; - * struct drm_i915_gem_create_ext create_ext = { - * .size = 16 * PAGE_SIZE, - * .extensions = (uintptr_t)®ions, - * }; - * - * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); - * if (err) ... - * - * At which point we get the object handle in &drm_i915_gem_create_ext.handle, - * along with the final object size in &drm_i915_gem_create_ext.size, which - * should account for any rounding up, if required. - */ -struct drm_i915_gem_create_ext_memory_regions { - /** @base: Extension link. See struct i915_user_extension. */ - struct i915_user_extension base; - - /** @pad: MBZ */ - __u32 pad; - /** @num_regions: Number of elements in the @regions array. */ - __u32 num_regions; - /** - * @regions: The regions/placements array. - * - * An array of struct drm_i915_gem_memory_class_instance. - */ - __u64 regions; -}; - -#if defined(__cplusplus) -} -#endif - -#endif /* _UAPI_I915_DRM_H_ */