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Reuse common logic of programming SCM fields for gen 9 and gen 11
Logic related to programming non coherent and thread arbitration policy for gens 9 and 11 has been moved to EncodeComputeMode object, where similar logic for gens gen12lp and newer is located. Functions PreambleHelper::programThreadArbitration and PreambleHelper::getThreadArbitrationCommandsSize have been removed. Redundant setForceNonCoherent call has been removed from XE HPG Related-To: NEO-6728 Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
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Compute-Runtime-Automation
parent
5d90e2ab1d
commit
cd95572443
@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2020-2021 Intel Corporation
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* Copyright (C) 2020-2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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@@ -17,6 +17,7 @@ using Family = NEO::BDWFamily;
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#include "shared/source/command_container/image_surface_state/compression_params_bdw_and_later.inl"
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namespace NEO {
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template <>
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void EncodeSurfaceState<Family>::setAuxParamsForMCSCCS(R_SURFACE_STATE *surfaceState) {
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}
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@@ -32,6 +33,16 @@ void EncodeSurfaceState<Family>::setFlagsForMediaCompression(R_SURFACE_STATE *su
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}
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}
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template <typename Family>
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size_t EncodeComputeMode<Family>::getCmdSizeForComputeMode(const HardwareInfo &hwInfo, bool hasSharedHandles, bool isRcs) {
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return 0u;
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}
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template <typename Family>
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void EncodeComputeMode<Family>::programComputeModeCommand(LinearStream &csr, StateComputeModeProperties &properties,
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const HardwareInfo &hwInfo) {
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}
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template struct EncodeDispatchKernel<Family>;
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template struct EncodeStates<Family>;
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template struct EncodeMath<Family>;
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@@ -15,10 +15,6 @@ namespace NEO {
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typedef BDWFamily Family;
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static auto gfxCore = IGFX_GEN8_CORE;
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template <>
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void CommandStreamReceiverHw<Family>::programComputeMode(LinearStream &stream, DispatchFlags &dispatchFlags, const HardwareInfo &hwInfo) {
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}
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template <>
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void populateFactoryTable<CommandStreamReceiverHw<Family>>() {
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extern CommandStreamReceiverCreateFunc commandStreamReceiverFactory[2 * IGFX_MAX_CORE];
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