From d18d1b6ce491b25db87f12788910ebf8c8063d25 Mon Sep 17 00:00:00 2001 From: "Dunajski, Bartosz" Date: Wed, 18 Sep 2019 19:32:33 +0200 Subject: [PATCH] Opensource TGLLP Change-Id: I1685057a641d938170b8c7ec860d2f53f45b1d6d Signed-off-by: Dunajski, Bartosz --- Jenkinsfile | 2 +- core/gen12lp/hw_cmds_generated.inl | 4459 +++++++++++++++++ core/gen12lp/hw_cmds_generated_patched.inl | 1017 ++++ .../definitions/engine_limits.h | 2 +- manifests/manifest.yml | 2 +- platforms.cmake | 19 + runtime/aub_mem_dump/aub_mem_dump.h | 7 + runtime/aub_mem_dump/aub_services.h | 4 +- .../gen12lp/scheduler_simulation.cpp | 94 + runtime/dll/linux/devices/devices_base.inl | 7 + .../gen12lp/additional_files_gen12lp.cmake | 17 + .../aub_command_stream_receiver_gen12lp.cpp | 45 + runtime/gen12lp/aub_mapper.h | 30 + runtime/gen12lp/aub_mem_dump_gen12lp.cpp | 255 + runtime/gen12lp/buffer_gen12lp.cpp | 17 + runtime/gen12lp/command_queue_gen12lp.cpp | 26 + .../command_stream_receiver_hw_gen12lp.cpp | 122 + ...m_receiver_simulated_common_hw_gen12lp.cpp | 47 + .../command_queue_helpers_gen12lp.inl | 8 + .../hardware_commands_helper_gen12lp.inl | 6 + runtime/gen12lp/device_enqueue.h | 22 + runtime/gen12lp/device_queue_gen12lp.cpp | 39 + .../gen12lp/enable_family_full_gen12lp.cpp | 41 + runtime/gen12lp/enable_gen12lp.cpp | 18 + .../gen12lp/enable_hw_info_config_gen12lp.cpp | 17 + .../experimental_command_buffer_gen12lp.cpp | 26 + runtime/gen12lp/gpgpu_walker_gen12lp.cpp | 25 + runtime/gen12lp/gtpin_setup_gen12lp.cpp | 35 + .../hardware_commands_helper_gen12lp.cpp | 42 + runtime/gen12lp/helpers_gen12lp.cpp | 46 + runtime/gen12lp/helpers_gen12lp.h | 35 + runtime/gen12lp/hw_cmds.h | 11 + runtime/gen12lp/hw_cmds_base.h | 69 + runtime/gen12lp/hw_cmds_tgllp.h | 34 + runtime/gen12lp/hw_helper_gen12lp.cpp | 107 + runtime/gen12lp/hw_info.h | 11 + runtime/gen12lp/hw_info_gen12lp.cpp | 14 + runtime/gen12lp/hw_info_gen12lp.h | 20 + runtime/gen12lp/hw_info_tgllp.h | 23 + runtime/gen12lp/hw_info_tgllp.inl | 160 + runtime/gen12lp/image_gen12lp.cpp | 42 + .../linux/command_stream_receiver_gen12lp.cpp | 18 + .../gen12lp/linux/hw_info_config_gen12lp.cpp | 13 + .../gen12lp/linux/hw_info_config_tgllp.inl | 25 + runtime/gen12lp/preamble_gen12lp.cpp | 81 + runtime/gen12lp/preemption_gen12lp.cpp | 66 + runtime/gen12lp/reg_configs.h | 25 + runtime/gen12lp/sampler_gen12lp.cpp | 11 + runtime/gen12lp/scheduler_definitions.h | 150 + runtime/gen12lp/scheduler_igdrcl_built_in.inl | 94 + .../gen12lp/state_base_address_gen12lp.cpp | 13 + .../tbx_command_stream_receiver_gen12lp.cpp | 40 + .../command_stream_receiver_gen12lp.cpp | 17 + .../gen12lp/windows/gmm_callbacks_gen12lp.cpp | 14 + .../windows/hw_info_config_gen12lp.cpp | 35 + runtime/gen_common/aub_mapper.h | 3 + runtime/gen_common/hw_cmds.h | 3 + .../reg_configs/reg_configs_common.h | 3 + runtime/helpers/CMakeLists.txt | 1 + runtime/helpers/gmm_callbacks_tgllp_plus.inl | 52 + runtime/mem_obj/CMakeLists.txt | 1 + runtime/mem_obj/image_tgllp_plus.inl | 33 + runtime/mem_obj/mem_obj_helper.cpp | 2 +- runtime/os_interface/debug_variables_base.inl | 1 + .../os_interface/linux/drm_engine_mapper.cpp | 2 + .../windows/wddm_engine_mapper.cpp | 2 + runtime/sampler/CMakeLists.txt | 1 + runtime/sampler/sampler_tgllp_plus.inl | 24 + third_party/aub_stream/headers/engine_node.h | 1 + third_party/uapi/drm/i915_drm.h | 1 + unit_tests/aub_tests/gen12lp/CMakeLists.txt | 15 + .../gen12lp/aub_mem_dump_tests_gen12lp.cpp | 19 + .../aub_tests_configuration_gen12lp.cpp | 18 + .../gen12lp/batch_buffer/CMakeLists.txt | 11 + .../aub_batch_buffer_tests_gen12lp.cpp | 63 + .../aub_batch_buffer_tests_gen12lp.h | 163 + .../gen12lp/execution_model/CMakeLists.txt | 10 + .../enqueue_parent_kernel_tests_gen12lp.cpp | 114 + .../context/driver_diagnostics_tests.cpp | 4 +- unit_tests/gen12lp/CMakeLists.txt | 32 + ..._command_stream_receiver_tests_gen12lp.cpp | 70 + .../gen12lp/cmd_parse/cmd_parse_gen12lp.inl | 14 + unit_tests/gen12lp/cmd_parse_gen12lp.cpp | 103 + .../gen12lp/coherency_tests_gen12lp.cpp | 307 ++ ...mmand_stream_receiver_hw_tests_gen12lp.cpp | 77 + ...iver_simulated_common_hw_tests_gen12lp.cpp | 144 + .../gen12lp/enqueue_media_kernel_gen12lp.cpp | 180 + .../gen12lp/hw_helper_tests_gen12lp.cpp | 151 + unit_tests/gen12lp/image_tests_gen12lp.cpp | 137 + unit_tests/gen12lp/kernel_tests_gen12lp.cpp | 24 + .../gen12lp/profiling_tests_gen12lp.cpp | 77 + unit_tests/gen12lp/sampler_tests_gen12lp.cpp | 58 + .../scheduler_source_tests_gen12lp.cpp | 31 + ..._command_stream_receiver_tests_gen12lp.cpp | 48 + .../gen12lp/test_device_caps_gen12lp.cpp | 107 + .../gen12lp/test_device_queue_hw_gen12lp.cpp | 84 + .../gen12lp/test_platform_caps_gen12lp.cpp | 28 + unit_tests/gen12lp/test_preamble_gen12lp.cpp | 150 + .../gen12lp/test_preemption_gen12lp.cpp | 81 + unit_tests/gen12lp/test_sample_gen12lp.cpp | 25 + unit_tests/gen12lp/tgllp/CMakeLists.txt | 14 + unit_tests/gen12lp/tgllp/linux/CMakeLists.txt | 13 + .../gen12lp/tgllp/linux/dll/CMakeLists.txt | 11 + .../tgllp/linux/dll/device_id_tests_tgllp.cpp | 39 + .../tgllp/test_hw_info_config_tgllp.cpp | 89 + .../gen12lp/tgllp/windows/CMakeLists.txt | 13 + .../windows/hw_info_config_tests_tgllp.cpp | 27 + .../gen12lp/unit_test_helper_gen12lp.cpp | 35 + unit_tests/gen12lp/windows/CMakeLists.txt | 15 + .../windows/gmm_callbacks_tests_gen12lp.cpp | 127 + .../windows/hw_info_config_tests_gen12lp.cpp | 31 + unit_tests/gen_common/CMakeLists.txt | 2 + .../gen_common/cmd_parse_compute_mode.inl | 23 + unit_tests/gen_common/cmd_parse_mi_arb.inl | 16 + unit_tests/gen_common/test.h | 28 +- unit_tests/libult/gen12lp.cpp | 33 + .../os_interface/linux/drm_mapper_tests.cpp | 3 + .../windows/wddm_mapper_tests.cpp | 3 + unit_tests/test_files/igdrcl.config | 1 + 119 files changed, 10616 insertions(+), 7 deletions(-) create mode 100644 core/gen12lp/hw_cmds_generated.inl create mode 100644 core/gen12lp/hw_cmds_generated_patched.inl create mode 100644 runtime/builtin_kernels_simulation/gen12lp/scheduler_simulation.cpp create mode 100644 runtime/gen12lp/additional_files_gen12lp.cmake create mode 100644 runtime/gen12lp/aub_command_stream_receiver_gen12lp.cpp create mode 100644 runtime/gen12lp/aub_mapper.h create mode 100644 runtime/gen12lp/aub_mem_dump_gen12lp.cpp create mode 100644 runtime/gen12lp/buffer_gen12lp.cpp create mode 100644 runtime/gen12lp/command_queue_gen12lp.cpp create mode 100644 runtime/gen12lp/command_stream_receiver_hw_gen12lp.cpp create mode 100644 runtime/gen12lp/command_stream_receiver_simulated_common_hw_gen12lp.cpp create mode 100644 runtime/gen12lp/definitions/command_queue_helpers_gen12lp.inl create mode 100644 runtime/gen12lp/definitions/hardware_commands_helper_gen12lp.inl create mode 100644 runtime/gen12lp/device_enqueue.h create mode 100644 runtime/gen12lp/device_queue_gen12lp.cpp create mode 100644 runtime/gen12lp/enable_family_full_gen12lp.cpp create mode 100644 runtime/gen12lp/enable_gen12lp.cpp create mode 100644 runtime/gen12lp/enable_hw_info_config_gen12lp.cpp create mode 100644 runtime/gen12lp/experimental_command_buffer_gen12lp.cpp create mode 100644 runtime/gen12lp/gpgpu_walker_gen12lp.cpp create mode 100644 runtime/gen12lp/gtpin_setup_gen12lp.cpp create mode 100644 runtime/gen12lp/hardware_commands_helper_gen12lp.cpp create mode 100644 runtime/gen12lp/helpers_gen12lp.cpp create mode 100644 runtime/gen12lp/helpers_gen12lp.h create mode 100644 runtime/gen12lp/hw_cmds.h create mode 100644 runtime/gen12lp/hw_cmds_base.h create mode 100644 runtime/gen12lp/hw_cmds_tgllp.h create mode 100644 runtime/gen12lp/hw_helper_gen12lp.cpp create mode 100644 runtime/gen12lp/hw_info.h create mode 100644 runtime/gen12lp/hw_info_gen12lp.cpp create mode 100644 runtime/gen12lp/hw_info_gen12lp.h create mode 100644 runtime/gen12lp/hw_info_tgllp.h create mode 100644 runtime/gen12lp/hw_info_tgllp.inl create mode 100644 runtime/gen12lp/image_gen12lp.cpp create mode 100644 runtime/gen12lp/linux/command_stream_receiver_gen12lp.cpp create mode 100644 runtime/gen12lp/linux/hw_info_config_gen12lp.cpp create mode 100644 runtime/gen12lp/linux/hw_info_config_tgllp.inl create mode 100644 runtime/gen12lp/preamble_gen12lp.cpp create mode 100644 runtime/gen12lp/preemption_gen12lp.cpp create mode 100644 runtime/gen12lp/reg_configs.h create mode 100644 runtime/gen12lp/sampler_gen12lp.cpp create mode 100644 runtime/gen12lp/scheduler_definitions.h create mode 100644 runtime/gen12lp/scheduler_igdrcl_built_in.inl create mode 100644 runtime/gen12lp/state_base_address_gen12lp.cpp create mode 100644 runtime/gen12lp/tbx_command_stream_receiver_gen12lp.cpp create mode 100644 runtime/gen12lp/windows/command_stream_receiver_gen12lp.cpp create mode 100644 runtime/gen12lp/windows/gmm_callbacks_gen12lp.cpp create mode 100644 runtime/gen12lp/windows/hw_info_config_gen12lp.cpp create mode 100644 runtime/helpers/gmm_callbacks_tgllp_plus.inl create mode 100644 runtime/mem_obj/image_tgllp_plus.inl create mode 100644 runtime/sampler/sampler_tgllp_plus.inl create mode 100644 unit_tests/aub_tests/gen12lp/CMakeLists.txt create mode 100644 unit_tests/aub_tests/gen12lp/aub_mem_dump_tests_gen12lp.cpp create mode 100644 unit_tests/aub_tests/gen12lp/aub_tests_configuration_gen12lp.cpp create mode 100644 unit_tests/aub_tests/gen12lp/batch_buffer/CMakeLists.txt create mode 100644 unit_tests/aub_tests/gen12lp/batch_buffer/aub_batch_buffer_tests_gen12lp.cpp create mode 100644 unit_tests/aub_tests/gen12lp/batch_buffer/aub_batch_buffer_tests_gen12lp.h create mode 100644 unit_tests/aub_tests/gen12lp/execution_model/CMakeLists.txt create mode 100644 unit_tests/aub_tests/gen12lp/execution_model/enqueue_parent_kernel_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/CMakeLists.txt create mode 100644 unit_tests/gen12lp/aub_command_stream_receiver_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/cmd_parse/cmd_parse_gen12lp.inl create mode 100644 unit_tests/gen12lp/cmd_parse_gen12lp.cpp create mode 100644 unit_tests/gen12lp/coherency_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/command_stream_receiver_hw_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/command_stream_receiver_simulated_common_hw_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/enqueue_media_kernel_gen12lp.cpp create mode 100644 unit_tests/gen12lp/hw_helper_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/image_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/kernel_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/profiling_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/sampler_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/scheduler_source_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/tbx_command_stream_receiver_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/test_device_caps_gen12lp.cpp create mode 100644 unit_tests/gen12lp/test_device_queue_hw_gen12lp.cpp create mode 100644 unit_tests/gen12lp/test_platform_caps_gen12lp.cpp create mode 100644 unit_tests/gen12lp/test_preamble_gen12lp.cpp create mode 100644 unit_tests/gen12lp/test_preemption_gen12lp.cpp create mode 100644 unit_tests/gen12lp/test_sample_gen12lp.cpp create mode 100644 unit_tests/gen12lp/tgllp/CMakeLists.txt create mode 100644 unit_tests/gen12lp/tgllp/linux/CMakeLists.txt create mode 100644 unit_tests/gen12lp/tgllp/linux/dll/CMakeLists.txt create mode 100644 unit_tests/gen12lp/tgllp/linux/dll/device_id_tests_tgllp.cpp create mode 100644 unit_tests/gen12lp/tgllp/test_hw_info_config_tgllp.cpp create mode 100644 unit_tests/gen12lp/tgllp/windows/CMakeLists.txt create mode 100644 unit_tests/gen12lp/tgllp/windows/hw_info_config_tests_tgllp.cpp create mode 100644 unit_tests/gen12lp/unit_test_helper_gen12lp.cpp create mode 100644 unit_tests/gen12lp/windows/CMakeLists.txt create mode 100644 unit_tests/gen12lp/windows/gmm_callbacks_tests_gen12lp.cpp create mode 100644 unit_tests/gen12lp/windows/hw_info_config_tests_gen12lp.cpp create mode 100644 unit_tests/gen_common/cmd_parse_compute_mode.inl create mode 100644 unit_tests/gen_common/cmd_parse_mi_arb.inl create mode 100644 unit_tests/libult/gen12lp.cpp diff --git a/Jenkinsfile b/Jenkinsfile index 4049d306a3..c837331857 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -1,5 +1,5 @@ #!groovy dependenciesRevision='3387a68d271545925f5ff091109728166e6f6d46-1309' strategy='EQUAL' -allowedCD=259 +allowedCD=263 allowedF=5 diff --git a/core/gen12lp/hw_cmds_generated.inl b/core/gen12lp/hw_cmds_generated.inl new file mode 100644 index 0000000000..5387010373 --- /dev/null +++ b/core/gen12lp/hw_cmds_generated.inl @@ -0,0 +1,4459 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma pack(1) +typedef struct tagBINDING_TABLE_STATE { + union tagTheStructure { + struct tagCommon { + uint32_t Reserved_0 : BITFIELD_RANGE(0, 5); + uint32_t SurfaceStatePointer : BITFIELD_RANGE(6, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + typedef enum tagPATCH_CONSTANTS { + SURFACESTATEPOINTER_BYTEOFFSET = 0x0, + SURFACESTATEPOINTER_INDEX = 0x0, + } PATCH_CONSTANTS; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + } + static tagBINDING_TABLE_STATE sInit(void) { + BINDING_TABLE_STATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 1); + return TheStructure.RawData[index]; + } + typedef enum tagSURFACESTATEPOINTER { + SURFACESTATEPOINTER_BIT_SHIFT = 0x6, + SURFACESTATEPOINTER_ALIGN_SIZE = 0x40, + } SURFACESTATEPOINTER; + inline void setSurfaceStatePointer(const uint64_t value) { + DEBUG_BREAK_IF(value >= 0x100000000); + TheStructure.Common.SurfaceStatePointer = (uint32_t)value >> SURFACESTATEPOINTER_BIT_SHIFT; + } + inline uint32_t getSurfaceStatePointer(void) const { + return (TheStructure.Common.SurfaceStatePointer << SURFACESTATEPOINTER_BIT_SHIFT); + } +} BINDING_TABLE_STATE; +STATIC_ASSERT(4 == sizeof(BINDING_TABLE_STATE)); + +typedef struct tagGPGPU_WALKER { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t PredicateEnable : BITFIELD_RANGE(8, 8); + uint32_t Reserved_9 : BITFIELD_RANGE(9, 9); + uint32_t IndirectParameterEnable : BITFIELD_RANGE(10, 10); + uint32_t Reserved_11 : BITFIELD_RANGE(11, 15); + uint32_t Subopcode : BITFIELD_RANGE(16, 23); + uint32_t MediaCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t Pipeline : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t InterfaceDescriptorOffset : BITFIELD_RANGE(0, 5); + uint32_t Reserved_38 : BITFIELD_RANGE(6, 31); + uint32_t IndirectDataLength : BITFIELD_RANGE(0, 16); + uint32_t Reserved_81 : BITFIELD_RANGE(17, 31); + uint32_t Reserved_96 : BITFIELD_RANGE(0, 5); + uint32_t IndirectDataStartAddress : BITFIELD_RANGE(6, 31); + uint32_t ThreadWidthCounterMaximum : BITFIELD_RANGE(0, 5); + uint32_t Reserved_134 : BITFIELD_RANGE(6, 7); + uint32_t ThreadHeightCounterMaximum : BITFIELD_RANGE(8, 13); + uint32_t Reserved_142 : BITFIELD_RANGE(14, 15); + uint32_t ThreadDepthCounterMaximum : BITFIELD_RANGE(16, 21); + uint32_t Reserved_150 : BITFIELD_RANGE(22, 29); + uint32_t SimdSize : BITFIELD_RANGE(30, 31); + uint32_t ThreadGroupIdStartingX; + uint32_t Reserved_192; + uint32_t ThreadGroupIdXDimension; + uint32_t ThreadGroupIdStartingY; + uint32_t Reserved_288; + uint32_t ThreadGroupIdYDimension; + uint32_t ThreadGroupIdStartingResumeZ; + uint32_t ThreadGroupIdZDimension; + uint32_t RightExecutionMask; + uint32_t BottomExecutionMask; + } Common; + uint32_t RawData[15]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0xd, + } DWORD_LENGTH; + typedef enum tagSUBOPCODE { + SUBOPCODE_GPGPU_WALKER_SUBOP = 0x5, + } SUBOPCODE; + typedef enum tagMEDIA_COMMAND_OPCODE { + MEDIA_COMMAND_OPCODE_GPGPU_WALKER = 0x1, + } MEDIA_COMMAND_OPCODE; + typedef enum tagPIPELINE { + PIPELINE_MEDIA = 0x2, + } PIPELINE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagSIMD_SIZE { + SIMD_SIZE_SIMD8 = 0x0, + SIMD_SIZE_SIMD16 = 0x1, + SIMD_SIZE_SIMD32 = 0x2, + } SIMD_SIZE; + typedef enum tagPATCH_CONSTANTS { + INDIRECTDATASTARTADDRESS_BYTEOFFSET = 0xc, + INDIRECTDATASTARTADDRESS_INDEX = 0x3, + } PATCH_CONSTANTS; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common.Subopcode = SUBOPCODE_GPGPU_WALKER_SUBOP; + TheStructure.Common.MediaCommandOpcode = MEDIA_COMMAND_OPCODE_GPGPU_WALKER; + TheStructure.Common.Pipeline = PIPELINE_MEDIA; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + TheStructure.Common.SimdSize = SIMD_SIZE_SIMD8; + } + static tagGPGPU_WALKER sInit(void) { + GPGPU_WALKER state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 15); + return TheStructure.RawData[index]; + } + inline void setPredicateEnable(const bool value) { + TheStructure.Common.PredicateEnable = value; + } + inline bool getPredicateEnable(void) const { + return (TheStructure.Common.PredicateEnable); + } + inline void setIndirectParameterEnable(const bool value) { + TheStructure.Common.IndirectParameterEnable = value; + } + inline bool getIndirectParameterEnable(void) const { + return (TheStructure.Common.IndirectParameterEnable); + } + inline void setInterfaceDescriptorOffset(const uint32_t value) { + TheStructure.Common.InterfaceDescriptorOffset = value; + } + inline uint32_t getInterfaceDescriptorOffset(void) const { + return (TheStructure.Common.InterfaceDescriptorOffset); + } + inline void setIndirectDataLength(const uint32_t value) { + TheStructure.Common.IndirectDataLength = value; + } + inline uint32_t getIndirectDataLength(void) const { + return (TheStructure.Common.IndirectDataLength); + } + typedef enum tagINDIRECTDATASTARTADDRESS { + INDIRECTDATASTARTADDRESS_BIT_SHIFT = 0x6, + INDIRECTDATASTARTADDRESS_ALIGN_SIZE = 0x40, + } INDIRECTDATASTARTADDRESS; + inline void setIndirectDataStartAddress(const uint32_t value) { + TheStructure.Common.IndirectDataStartAddress = value >> INDIRECTDATASTARTADDRESS_BIT_SHIFT; + } + inline uint32_t getIndirectDataStartAddress(void) const { + return (TheStructure.Common.IndirectDataStartAddress << INDIRECTDATASTARTADDRESS_BIT_SHIFT); + } + inline void setThreadWidthCounterMaximum(const uint32_t value) { + TheStructure.Common.ThreadWidthCounterMaximum = value - 1; + } + inline uint32_t getThreadWidthCounterMaximum(void) const { + return (TheStructure.Common.ThreadWidthCounterMaximum + 1); + } + inline void setThreadHeightCounterMaximum(const uint32_t value) { + TheStructure.Common.ThreadHeightCounterMaximum = value - 1; + } + inline uint32_t getThreadHeightCounterMaximum(void) const { + return (TheStructure.Common.ThreadHeightCounterMaximum + 1); + } + inline void setThreadDepthCounterMaximum(const uint32_t value) { + TheStructure.Common.ThreadDepthCounterMaximum = value; + } + inline uint32_t getThreadDepthCounterMaximum(void) const { + return (TheStructure.Common.ThreadDepthCounterMaximum); + } + inline void setSimdSize(const SIMD_SIZE value) { + TheStructure.Common.SimdSize = value; + } + inline SIMD_SIZE getSimdSize(void) const { + return static_cast(TheStructure.Common.SimdSize); + } + inline void setThreadGroupIdStartingX(const uint32_t value) { + TheStructure.Common.ThreadGroupIdStartingX = value; + } + inline uint32_t getThreadGroupIdStartingX(void) const { + return (TheStructure.Common.ThreadGroupIdStartingX); + } + inline void setThreadGroupIdXDimension(const uint32_t value) { + TheStructure.Common.ThreadGroupIdXDimension = value; + } + inline uint32_t getThreadGroupIdXDimension(void) const { + return (TheStructure.Common.ThreadGroupIdXDimension); + } + inline void setThreadGroupIdStartingY(const uint32_t value) { + TheStructure.Common.ThreadGroupIdStartingY = value; + } + inline uint32_t getThreadGroupIdStartingY(void) const { + return (TheStructure.Common.ThreadGroupIdStartingY); + } + inline void setThreadGroupIdYDimension(const uint32_t value) { + TheStructure.Common.ThreadGroupIdYDimension = value; + } + inline uint32_t getThreadGroupIdYDimension(void) const { + return (TheStructure.Common.ThreadGroupIdYDimension); + } + inline void setThreadGroupIdStartingResumeZ(const uint32_t value) { + TheStructure.Common.ThreadGroupIdStartingResumeZ = value; + } + inline uint32_t getThreadGroupIdStartingResumeZ(void) const { + return (TheStructure.Common.ThreadGroupIdStartingResumeZ); + } + inline void setThreadGroupIdZDimension(const uint32_t value) { + TheStructure.Common.ThreadGroupIdZDimension = value; + } + inline uint32_t getThreadGroupIdZDimension(void) const { + return (TheStructure.Common.ThreadGroupIdZDimension); + } + inline void setRightExecutionMask(const uint32_t value) { + TheStructure.Common.RightExecutionMask = value; + } + inline uint32_t getRightExecutionMask(void) const { + return (TheStructure.Common.RightExecutionMask); + } + inline void setBottomExecutionMask(const uint32_t value) { + TheStructure.Common.BottomExecutionMask = value; + } + inline uint32_t getBottomExecutionMask(void) const { + return (TheStructure.Common.BottomExecutionMask); + } +} GPGPU_WALKER; +STATIC_ASSERT(60 == sizeof(GPGPU_WALKER)); + +typedef struct tagINTERFACE_DESCRIPTOR_DATA { + union tagTheStructure { + struct tagCommon { + uint32_t Reserved_0 : BITFIELD_RANGE(0, 5); + uint32_t KernelStartPointer : BITFIELD_RANGE(6, 31); + uint32_t KernelStartPointerHigh : BITFIELD_RANGE(0, 15); + uint32_t Reserved_48 : BITFIELD_RANGE(16, 31); + uint32_t Reserved_64 : BITFIELD_RANGE(0, 6); + uint32_t SoftwareExceptionEnable : BITFIELD_RANGE(7, 7); + uint32_t Reserved_72 : BITFIELD_RANGE(8, 10); + uint32_t MaskStackExceptionEnable : BITFIELD_RANGE(11, 11); + uint32_t Reserved_76 : BITFIELD_RANGE(12, 12); + uint32_t IllegalOpcodeExceptionEnable : BITFIELD_RANGE(13, 13); + uint32_t Reserved_78 : BITFIELD_RANGE(14, 15); + uint32_t FloatingPointMode : BITFIELD_RANGE(16, 16); + uint32_t ThreadPriority : BITFIELD_RANGE(17, 17); + uint32_t SingleProgramFlow : BITFIELD_RANGE(18, 18); + uint32_t DenormMode : BITFIELD_RANGE(19, 19); + uint32_t ThreadPreemptionDisable : BITFIELD_RANGE(20, 20); + uint32_t Reserved_85 : BITFIELD_RANGE(21, 31); + uint32_t Reserved_96 : BITFIELD_RANGE(0, 1); + uint32_t SamplerCount : BITFIELD_RANGE(2, 4); + uint32_t SamplerStatePointer : BITFIELD_RANGE(5, 31); + uint32_t BindingTableEntryCount : BITFIELD_RANGE(0, 4); + uint32_t BindingTablePointer : BITFIELD_RANGE(5, 15); + uint32_t Reserved_144 : BITFIELD_RANGE(16, 31); + uint32_t ConstantUrbEntryReadOffset : BITFIELD_RANGE(0, 15); + uint32_t ConstantIndirectUrbEntryReadLength : BITFIELD_RANGE(16, 31); + uint32_t NumberOfThreadsInGpgpuThreadGroup : BITFIELD_RANGE(0, 9); + uint32_t Reserved_202 : BITFIELD_RANGE(10, 15); + uint32_t SharedLocalMemorySize : BITFIELD_RANGE(16, 20); + uint32_t BarrierEnable : BITFIELD_RANGE(21, 21); + uint32_t RoundingMode : BITFIELD_RANGE(22, 23); + uint32_t Reserved_216 : BITFIELD_RANGE(24, 31); + uint32_t Cross_ThreadConstantDataReadLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_232 : BITFIELD_RANGE(8, 31); + } Common; + uint32_t RawData[8]; + } TheStructure; + typedef enum tagFLOATING_POINT_MODE { + FLOATING_POINT_MODE_IEEE_754 = 0x0, + FLOATING_POINT_MODE_ALTERNATE = 0x1, + } FLOATING_POINT_MODE; + typedef enum tagTHREAD_PRIORITY { + THREAD_PRIORITY_NORMAL_PRIORITY = 0x0, + THREAD_PRIORITY_HIGH_PRIORITY = 0x1, + } THREAD_PRIORITY; + typedef enum tagSINGLE_PROGRAM_FLOW { + SINGLE_PROGRAM_FLOW_MULTIPLE = 0x0, + SINGLE_PROGRAM_FLOW_SINGLE = 0x1, + } SINGLE_PROGRAM_FLOW; + typedef enum tagDENORM_MODE { + DENORM_MODE_FTZ = 0x0, + DENORM_MODE_SETBYKERNEL = 0x1, + } DENORM_MODE; + typedef enum tagTHREAD_PREEMPTION_DISABLE { + THREAD_PREEMPTION_DISABLE_DISABLE = 0x0, + THREAD_PREEMPTION_DISABLE_ENABLE = 0x1, + } THREAD_PREEMPTION_DISABLE; + typedef enum tagSAMPLER_COUNT { + SAMPLER_COUNT_NO_SAMPLERS_USED = 0x0, + SAMPLER_COUNT_BETWEEN_1_AND_4_SAMPLERS_USED = 0x1, + SAMPLER_COUNT_BETWEEN_5_AND_8_SAMPLERS_USED = 0x2, + SAMPLER_COUNT_BETWEEN_9_AND_12_SAMPLERS_USED = 0x3, + SAMPLER_COUNT_BETWEEN_13_AND_16_SAMPLERS_USED = 0x4, + } SAMPLER_COUNT; + typedef enum tagSHARED_LOCAL_MEMORY_SIZE { + SHARED_LOCAL_MEMORY_SIZE_ENCODES_0K = 0x0, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_1K = 0x1, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_2K = 0x2, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_4K = 0x3, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_8K = 0x4, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_16K = 0x5, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_32K = 0x6, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_64K = 0x7, + } SHARED_LOCAL_MEMORY_SIZE; + typedef enum tagROUNDING_MODE { + ROUNDING_MODE_RTNE = 0x0, + ROUNDING_MODE_RU = 0x1, + ROUNDING_MODE_RD = 0x2, + ROUNDING_MODE_RTZ = 0x3, + } ROUNDING_MODE; + typedef enum tagPATCH_CONSTANTS { + KERNELSTARTPOINTER_BYTEOFFSET = 0x0, + KERNELSTARTPOINTER_INDEX = 0x0, + KERNELSTARTPOINTERHIGH_BYTEOFFSET = 0x4, + KERNELSTARTPOINTERHIGH_INDEX = 0x1, + SAMPLERSTATEPOINTER_BYTEOFFSET = 0xc, + SAMPLERSTATEPOINTER_INDEX = 0x3, + BINDINGTABLEPOINTER_BYTEOFFSET = 0x10, + BINDINGTABLEPOINTER_INDEX = 0x4, + } PATCH_CONSTANTS; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.FloatingPointMode = FLOATING_POINT_MODE_IEEE_754; + TheStructure.Common.ThreadPriority = THREAD_PRIORITY_NORMAL_PRIORITY; + TheStructure.Common.SingleProgramFlow = SINGLE_PROGRAM_FLOW_MULTIPLE; + TheStructure.Common.DenormMode = DENORM_MODE_FTZ; + TheStructure.Common.ThreadPreemptionDisable = THREAD_PREEMPTION_DISABLE_DISABLE; + TheStructure.Common.SamplerCount = SAMPLER_COUNT_NO_SAMPLERS_USED; + TheStructure.Common.SharedLocalMemorySize = SHARED_LOCAL_MEMORY_SIZE_ENCODES_0K; + TheStructure.Common.RoundingMode = ROUNDING_MODE_RTNE; + } + static tagINTERFACE_DESCRIPTOR_DATA sInit(void) { + INTERFACE_DESCRIPTOR_DATA state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 8); + return TheStructure.RawData[index]; + } + typedef enum tagKERNELSTARTPOINTER { + KERNELSTARTPOINTER_BIT_SHIFT = 0x6, + KERNELSTARTPOINTER_ALIGN_SIZE = 0x40, + } KERNELSTARTPOINTER; + inline void setKernelStartPointer(const uint64_t value) { + DEBUG_BREAK_IF(value >= 0x100000000); + TheStructure.Common.KernelStartPointer = (uint32_t)value >> KERNELSTARTPOINTER_BIT_SHIFT; + } + inline uint32_t getKernelStartPointer(void) const { + return (TheStructure.Common.KernelStartPointer << KERNELSTARTPOINTER_BIT_SHIFT); + } + inline void setKernelStartPointerHigh(const uint32_t value) { + TheStructure.Common.KernelStartPointerHigh = value; + } + inline uint32_t getKernelStartPointerHigh(void) const { + return (TheStructure.Common.KernelStartPointerHigh); + } + inline void setSoftwareExceptionEnable(const bool value) { + TheStructure.Common.SoftwareExceptionEnable = value; + } + inline bool getSoftwareExceptionEnable(void) const { + return (TheStructure.Common.SoftwareExceptionEnable); + } + inline void setMaskStackExceptionEnable(const bool value) { + TheStructure.Common.MaskStackExceptionEnable = value; + } + inline bool getMaskStackExceptionEnable(void) const { + return (TheStructure.Common.MaskStackExceptionEnable); + } + inline void setIllegalOpcodeExceptionEnable(const bool value) { + TheStructure.Common.IllegalOpcodeExceptionEnable = value; + } + inline bool getIllegalOpcodeExceptionEnable(void) const { + return (TheStructure.Common.IllegalOpcodeExceptionEnable); + } + inline void setFloatingPointMode(const FLOATING_POINT_MODE value) { + TheStructure.Common.FloatingPointMode = value; + } + inline FLOATING_POINT_MODE getFloatingPointMode(void) const { + return static_cast(TheStructure.Common.FloatingPointMode); + } + inline void setThreadPriority(const THREAD_PRIORITY value) { + TheStructure.Common.ThreadPriority = value; + } + inline THREAD_PRIORITY getThreadPriority(void) const { + return static_cast(TheStructure.Common.ThreadPriority); + } + inline void setSingleProgramFlow(const SINGLE_PROGRAM_FLOW value) { + TheStructure.Common.SingleProgramFlow = value; + } + inline SINGLE_PROGRAM_FLOW getSingleProgramFlow(void) const { + return static_cast(TheStructure.Common.SingleProgramFlow); + } + inline void setDenormMode(const DENORM_MODE value) { + TheStructure.Common.DenormMode = value; + } + inline DENORM_MODE getDenormMode(void) const { + return static_cast(TheStructure.Common.DenormMode); + } + inline void setThreadPreemptionDisable(const THREAD_PREEMPTION_DISABLE value) { + TheStructure.Common.ThreadPreemptionDisable = value; + } + inline THREAD_PREEMPTION_DISABLE getThreadPreemptionDisable(void) const { + return static_cast(TheStructure.Common.ThreadPreemptionDisable); + } + inline void setSamplerCount(const SAMPLER_COUNT value) { + TheStructure.Common.SamplerCount = value; + } + inline SAMPLER_COUNT getSamplerCount(void) const { + return static_cast(TheStructure.Common.SamplerCount); + } + typedef enum tagSAMPLERSTATEPOINTER { + SAMPLERSTATEPOINTER_BIT_SHIFT = 0x5, + SAMPLERSTATEPOINTER_ALIGN_SIZE = 0x20, + } SAMPLERSTATEPOINTER; + inline void setSamplerStatePointer(const uint64_t value) { + DEBUG_BREAK_IF(value >= 0x100000000); + TheStructure.Common.SamplerStatePointer = (uint32_t)value >> SAMPLERSTATEPOINTER_BIT_SHIFT; + } + inline uint32_t getSamplerStatePointer(void) const { + return (TheStructure.Common.SamplerStatePointer << SAMPLERSTATEPOINTER_BIT_SHIFT); + } + inline void setBindingTableEntryCount(const uint32_t value) { + TheStructure.Common.BindingTableEntryCount = value; + } + inline uint32_t getBindingTableEntryCount(void) const { + return (TheStructure.Common.BindingTableEntryCount); + } + typedef enum tagBINDINGTABLEPOINTER { + BINDINGTABLEPOINTER_BIT_SHIFT = 0x5, + BINDINGTABLEPOINTER_ALIGN_SIZE = 0x20, + } BINDINGTABLEPOINTER; + inline void setBindingTablePointer(const uint64_t value) { + DEBUG_BREAK_IF(value >= 0x100000000); + TheStructure.Common.BindingTablePointer = (uint32_t)value >> BINDINGTABLEPOINTER_BIT_SHIFT; + } + inline uint32_t getBindingTablePointer(void) const { + return (TheStructure.Common.BindingTablePointer << BINDINGTABLEPOINTER_BIT_SHIFT); + } + inline void setConstantUrbEntryReadOffset(const uint32_t value) { + TheStructure.Common.ConstantUrbEntryReadOffset = value; + } + inline uint32_t getConstantUrbEntryReadOffset(void) const { + return (TheStructure.Common.ConstantUrbEntryReadOffset); + } + inline void setConstantIndirectUrbEntryReadLength(const uint32_t value) { + TheStructure.Common.ConstantIndirectUrbEntryReadLength = value; + } + inline uint32_t getConstantIndirectUrbEntryReadLength(void) const { + return (TheStructure.Common.ConstantIndirectUrbEntryReadLength); + } + inline void setNumberOfThreadsInGpgpuThreadGroup(const uint32_t value) { + TheStructure.Common.NumberOfThreadsInGpgpuThreadGroup = value; + } + inline uint32_t getNumberOfThreadsInGpgpuThreadGroup(void) const { + return (TheStructure.Common.NumberOfThreadsInGpgpuThreadGroup); + } + inline void setSharedLocalMemorySize(const SHARED_LOCAL_MEMORY_SIZE value) { + TheStructure.Common.SharedLocalMemorySize = value; + } + inline SHARED_LOCAL_MEMORY_SIZE getSharedLocalMemorySize(void) const { + return static_cast(TheStructure.Common.SharedLocalMemorySize); + } + inline void setBarrierEnable(const bool value) { + TheStructure.Common.BarrierEnable = value; + } + inline bool getBarrierEnable(void) const { + return (TheStructure.Common.BarrierEnable); + } + inline void setRoundingMode(const ROUNDING_MODE value) { + TheStructure.Common.RoundingMode = value; + } + inline ROUNDING_MODE getRoundingMode(void) const { + return static_cast(TheStructure.Common.RoundingMode); + } + inline void setCrossThreadConstantDataReadLength(const uint32_t value) { + TheStructure.Common.Cross_ThreadConstantDataReadLength = value; + } + inline uint32_t getCrossThreadConstantDataReadLength(void) const { + return (TheStructure.Common.Cross_ThreadConstantDataReadLength); + } +} INTERFACE_DESCRIPTOR_DATA; +STATIC_ASSERT(32 == sizeof(INTERFACE_DESCRIPTOR_DATA)); + +typedef struct tagMEDIA_INTERFACE_DESCRIPTOR_LOAD { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 15); + uint32_t Subopcode : BITFIELD_RANGE(16, 23); + uint32_t MediaCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t Pipeline : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t Reserved_32; + uint32_t InterfaceDescriptorTotalLength : BITFIELD_RANGE(0, 16); + uint32_t Reserved_81 : BITFIELD_RANGE(17, 31); + uint32_t InterfaceDescriptorDataStartAddress; + } Common; + uint32_t RawData[4]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x2, + } DWORD_LENGTH; + typedef enum tagSUBOPCODE { + SUBOPCODE_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SUBOP = 0x2, + } SUBOPCODE; + typedef enum tagMEDIA_COMMAND_OPCODE { + MEDIA_COMMAND_OPCODE_MEDIA_INTERFACE_DESCRIPTOR_LOAD = 0x0, + } MEDIA_COMMAND_OPCODE; + typedef enum tagPIPELINE { + PIPELINE_MEDIA = 0x2, + } PIPELINE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagPATCH_CONSTANTS { + INTERFACEDESCRIPTORDATASTARTADDRESS_BYTEOFFSET = 0xc, + INTERFACEDESCRIPTORDATASTARTADDRESS_INDEX = 0x3, + } PATCH_CONSTANTS; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common.Subopcode = SUBOPCODE_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SUBOP; + TheStructure.Common.MediaCommandOpcode = MEDIA_COMMAND_OPCODE_MEDIA_INTERFACE_DESCRIPTOR_LOAD; + TheStructure.Common.Pipeline = PIPELINE_MEDIA; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + } + static tagMEDIA_INTERFACE_DESCRIPTOR_LOAD sInit(void) { + MEDIA_INTERFACE_DESCRIPTOR_LOAD state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setInterfaceDescriptorTotalLength(const uint32_t value) { + TheStructure.Common.InterfaceDescriptorTotalLength = value; + } + inline uint32_t getInterfaceDescriptorTotalLength(void) const { + return (TheStructure.Common.InterfaceDescriptorTotalLength); + } + inline void setInterfaceDescriptorDataStartAddress(const uint32_t value) { + TheStructure.Common.InterfaceDescriptorDataStartAddress = value; + } + inline uint32_t getInterfaceDescriptorDataStartAddress(void) const { + return (TheStructure.Common.InterfaceDescriptorDataStartAddress); + } +} MEDIA_INTERFACE_DESCRIPTOR_LOAD; +STATIC_ASSERT(16 == sizeof(MEDIA_INTERFACE_DESCRIPTOR_LOAD)); + +typedef struct tagMEDIA_STATE_FLUSH { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 15); + uint32_t Subopcode : BITFIELD_RANGE(16, 23); + uint32_t MediaCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t Pipeline : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t InterfaceDescriptorOffset : BITFIELD_RANGE(0, 5); + uint32_t Reserved_38 : BITFIELD_RANGE(6, 6); + uint32_t FlushToGo : BITFIELD_RANGE(7, 7); + uint32_t Reserved_40 : BITFIELD_RANGE(8, 31); + } Common; + uint32_t RawData[2]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x0, + } DWORD_LENGTH; + typedef enum tagSUBOPCODE { + SUBOPCODE_MEDIA_STATE_FLUSH_SUBOP = 0x4, + } SUBOPCODE; + typedef enum tagMEDIA_COMMAND_OPCODE { + MEDIA_COMMAND_OPCODE_MEDIA_STATE_FLUSH = 0x0, + } MEDIA_COMMAND_OPCODE; + typedef enum tagPIPELINE { + PIPELINE_MEDIA = 0x2, + } PIPELINE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common.Subopcode = SUBOPCODE_MEDIA_STATE_FLUSH_SUBOP; + TheStructure.Common.MediaCommandOpcode = MEDIA_COMMAND_OPCODE_MEDIA_STATE_FLUSH; + TheStructure.Common.Pipeline = PIPELINE_MEDIA; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + } + static tagMEDIA_STATE_FLUSH sInit(void) { + MEDIA_STATE_FLUSH state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 2); + return TheStructure.RawData[index]; + } + inline void setInterfaceDescriptorOffset(const uint32_t value) { + TheStructure.Common.InterfaceDescriptorOffset = value; + } + inline uint32_t getInterfaceDescriptorOffset(void) const { + return (TheStructure.Common.InterfaceDescriptorOffset); + } + inline void setFlushToGo(const bool value) { + TheStructure.Common.FlushToGo = value; + } + inline bool getFlushToGo(void) const { + return (TheStructure.Common.FlushToGo); + } +} MEDIA_STATE_FLUSH; +STATIC_ASSERT(8 == sizeof(MEDIA_STATE_FLUSH)); + +typedef struct tagMEDIA_VFE_STATE { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 15); + uint32_t Subopcode : BITFIELD_RANGE(16, 23); + uint32_t MediaCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t Pipeline : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t PerThreadScratchSpace : BITFIELD_RANGE(0, 3); + uint32_t StackSize : BITFIELD_RANGE(4, 7); + uint32_t Reserved_40 : BITFIELD_RANGE(8, 9); + uint32_t ScratchSpaceBasePointer : BITFIELD_RANGE(10, 31); + uint32_t ScratchSpaceBasePointerHigh : BITFIELD_RANGE(0, 15); + uint32_t Reserved_80 : BITFIELD_RANGE(16, 31); + uint32_t Reserved_96 : BITFIELD_RANGE(0, 1); + uint32_t DispatchLoadBalance : BITFIELD_RANGE(2, 2); + uint32_t Reserved_99 : BITFIELD_RANGE(3, 5); + uint32_t DisableSlice0Subslice2 : BITFIELD_RANGE(6, 6); + uint32_t Reserved_103 : BITFIELD_RANGE(7, 7); + uint32_t NumberOfUrbEntries : BITFIELD_RANGE(8, 15); + uint32_t MaximumNumberOfThreads : BITFIELD_RANGE(16, 31); + uint32_t MaximumNumberOfDual_Subslices : BITFIELD_RANGE(0, 7); + uint32_t Reserved_136 : BITFIELD_RANGE(8, 31); + uint32_t CurbeAllocationSize : BITFIELD_RANGE(0, 15); + uint32_t UrbEntryAllocationSize : BITFIELD_RANGE(16, 31); + uint32_t Reserved_192; + uint32_t Reserved_224; + uint32_t Reserved_256; + } Common; + uint32_t RawData[9]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x7, + } DWORD_LENGTH; + typedef enum tagSUBOPCODE { + SUBOPCODE_MEDIA_VFE_STATE_SUBOP = 0x0, + } SUBOPCODE; + typedef enum tagMEDIA_COMMAND_OPCODE { + MEDIA_COMMAND_OPCODE_MEDIA_VFE_STATE = 0x0, + } MEDIA_COMMAND_OPCODE; + typedef enum tagPIPELINE { + PIPELINE_MEDIA = 0x2, + } PIPELINE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagDISPATCH_LOAD_BALANCE { + DISPATCH_LOAD_BALANCE_LEAST_LOADED = 0x0, + DISPATCH_LOAD_BALANCE_COLOR_LSB = 0x1, + } DISPATCH_LOAD_BALANCE; + typedef enum tagPATCH_CONSTANTS { + SCRATCHSPACEBASEPOINTER_BYTEOFFSET = 0x4, + SCRATCHSPACEBASEPOINTER_INDEX = 0x1, + SCRATCHSPACEBASEPOINTERHIGH_BYTEOFFSET = 0x8, + SCRATCHSPACEBASEPOINTERHIGH_INDEX = 0x2, + } PATCH_CONSTANTS; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common.Subopcode = SUBOPCODE_MEDIA_VFE_STATE_SUBOP; + TheStructure.Common.MediaCommandOpcode = MEDIA_COMMAND_OPCODE_MEDIA_VFE_STATE; + TheStructure.Common.Pipeline = PIPELINE_MEDIA; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + TheStructure.Common.DispatchLoadBalance = DISPATCH_LOAD_BALANCE_LEAST_LOADED; + } + static tagMEDIA_VFE_STATE sInit(void) { + MEDIA_VFE_STATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 9); + return TheStructure.RawData[index]; + } + inline void setPerThreadScratchSpace(const uint32_t value) { + TheStructure.Common.PerThreadScratchSpace = value; + } + inline uint32_t getPerThreadScratchSpace(void) const { + return (TheStructure.Common.PerThreadScratchSpace); + } + inline void setStackSize(const uint32_t value) { + TheStructure.Common.StackSize = value; + } + inline uint32_t getStackSize(void) const { + return (TheStructure.Common.StackSize); + } + typedef enum tagSCRATCHSPACEBASEPOINTER { + SCRATCHSPACEBASEPOINTER_BIT_SHIFT = 0xa, + SCRATCHSPACEBASEPOINTER_ALIGN_SIZE = 0x400, + } SCRATCHSPACEBASEPOINTER; + inline void setScratchSpaceBasePointer(const uint32_t value) { + TheStructure.Common.ScratchSpaceBasePointer = value >> SCRATCHSPACEBASEPOINTER_BIT_SHIFT; + } + inline uint32_t getScratchSpaceBasePointer(void) const { + return (TheStructure.Common.ScratchSpaceBasePointer << SCRATCHSPACEBASEPOINTER_BIT_SHIFT); + } + inline void setScratchSpaceBasePointerHigh(const uint32_t value) { + TheStructure.Common.ScratchSpaceBasePointerHigh = value; + } + inline uint32_t getScratchSpaceBasePointerHigh(void) const { + return (TheStructure.Common.ScratchSpaceBasePointerHigh); + } + inline void setDispatchLoadBalance(const DISPATCH_LOAD_BALANCE value) { + TheStructure.Common.DispatchLoadBalance = value; + } + inline DISPATCH_LOAD_BALANCE getDispatchLoadBalance(void) const { + return static_cast(TheStructure.Common.DispatchLoadBalance); + } + inline void setDisableSlice0Subslice2(const bool value) { + TheStructure.Common.DisableSlice0Subslice2 = value; + } + inline bool getDisableSlice0Subslice2(void) const { + return (TheStructure.Common.DisableSlice0Subslice2); + } + inline void setNumberOfUrbEntries(const uint32_t value) { + TheStructure.Common.NumberOfUrbEntries = value; + } + inline uint32_t getNumberOfUrbEntries(void) const { + return (TheStructure.Common.NumberOfUrbEntries); + } + inline void setMaximumNumberOfThreads(const uint32_t value) { + TheStructure.Common.MaximumNumberOfThreads = value - 1; + } + inline uint32_t getMaximumNumberOfThreads(void) const { + return (TheStructure.Common.MaximumNumberOfThreads + 1); + } + inline void setMaximumNumberOfDualSubslices(const uint32_t value) { + TheStructure.Common.MaximumNumberOfDual_Subslices = value; + } + inline uint32_t getMaximumNumberOfDualSubslices(void) const { + return (TheStructure.Common.MaximumNumberOfDual_Subslices); + } + inline void setCurbeAllocationSize(const uint32_t value) { + TheStructure.Common.CurbeAllocationSize = value; + } + inline uint32_t getCurbeAllocationSize(void) const { + return (TheStructure.Common.CurbeAllocationSize); + } + inline void setUrbEntryAllocationSize(const uint32_t value) { + TheStructure.Common.UrbEntryAllocationSize = value; + } + inline uint32_t getUrbEntryAllocationSize(void) const { + return (TheStructure.Common.UrbEntryAllocationSize); + } +} MEDIA_VFE_STATE; +STATIC_ASSERT(36 == sizeof(MEDIA_VFE_STATE)); + +typedef struct tagMI_ARB_CHECK { + union tagTheStructure { + struct tagCommon { + uint32_t Pre_FetchDisable : BITFIELD_RANGE(0, 0); + uint32_t Reserved_1 : BITFIELD_RANGE(1, 7); + uint32_t MaskBits : BITFIELD_RANGE(8, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_ARB_CHECK = 0x5, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_ARB_CHECK; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_ARB_CHECK sInit(void) { + MI_ARB_CHECK state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 1); + return TheStructure.RawData[index]; + } + inline void setPreFetchDisable(const uint32_t value) { + TheStructure.Common.Pre_FetchDisable = value; + } + inline uint32_t getPreFetchDisable(void) const { + return TheStructure.Common.Pre_FetchDisable; + } + inline void setMaskBits(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xff00); + TheStructure.Common.MaskBits = value; + } + inline uint32_t getMaskBits(void) const { + return TheStructure.Common.MaskBits; + } +} MI_ARB_CHECK; +STATIC_ASSERT(4 == sizeof(MI_ARB_CHECK)); + +typedef struct tagMI_ATOMIC { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t AtomicOpcode : BITFIELD_RANGE(8, 15); + uint32_t ReturnDataControl : BITFIELD_RANGE(16, 16); + uint32_t CsStall : BITFIELD_RANGE(17, 17); + uint32_t InlineData : BITFIELD_RANGE(18, 18); + uint32_t DataSize : BITFIELD_RANGE(19, 20); + uint32_t Post_SyncOperation : BITFIELD_RANGE(21, 21); + uint32_t MemoryType : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint32_t MemoryAddress : BITFIELD_RANGE(2, 31); + uint32_t MemoryAddressHigh : BITFIELD_RANGE(0, 15); + uint32_t Reserved_80 : BITFIELD_RANGE(16, 31); + uint32_t Operand1DataDword0; + uint32_t Operand2DataDword0; + uint32_t Operand1DataDword1; + uint32_t Operand2DataDword1; + uint32_t Operand1DataDword2; + uint32_t Operand2DataDword2; + uint32_t Operand1DataDword3; + uint32_t Operand2DataDword3; + } Common; + uint32_t RawData[11]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_INLINE_DATA_0 = 0x1, + DWORD_LENGTH_INLINE_DATA_1 = 0x9, + } DWORD_LENGTH; + typedef enum tagDATA_SIZE { + DATA_SIZE_DWORD = 0x0, + DATA_SIZE_QWORD = 0x1, + DATA_SIZE_OCTWORD = 0x2, + } DATA_SIZE; + typedef enum tagPOST_SYNC_OPERATION { + POST_SYNC_OPERATION_NO_POST_SYNC_OPERATION = 0x0, + POST_SYNC_OPERATION_POST_SYNC_OPERATION = 0x1, + } POST_SYNC_OPERATION; + typedef enum tagMEMORY_TYPE { + MEMORY_TYPE_PER_PROCESS_GRAPHICS_ADDRESS = 0x0, + MEMORY_TYPE_GLOBAL_GRAPHICS_ADDRESS = 0x1, + } MEMORY_TYPE; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_ATOMIC = 0x2f, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + typedef enum tagATOMIC_OPCODES { + ATOMIC_4B_DECREMENT = 0x6, + ATOMIC_8B_INCREMENT = 0x25, + ATOMIC_8B_DECREMENT = 0x26, + } ATOMIC_OPCODES; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_INLINE_DATA_0; + TheStructure.Common.DataSize = DATA_SIZE_DWORD; + TheStructure.Common.Post_SyncOperation = + POST_SYNC_OPERATION_NO_POST_SYNC_OPERATION; + TheStructure.Common.MemoryType = MEMORY_TYPE_PER_PROCESS_GRAPHICS_ADDRESS; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_ATOMIC; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_ATOMIC sInit(void) { + MI_ATOMIC state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 11); + return TheStructure.RawData[index]; + } + inline void setDwordLength(const DWORD_LENGTH value) { + TheStructure.Common.DwordLength = value; + } + inline DWORD_LENGTH getDwordLength(void) const { + return static_cast(TheStructure.Common.DwordLength); + } + inline void setAtomicOpcode(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xff00); + TheStructure.Common.AtomicOpcode = value; + } + inline uint32_t getAtomicOpcode(void) const { + return TheStructure.Common.AtomicOpcode; + } + inline void setReturnDataControl(const uint32_t value) { + TheStructure.Common.ReturnDataControl = value; + } + inline uint32_t getReturnDataControl(void) const { + return TheStructure.Common.ReturnDataControl; + } + inline void setCsStall(const uint32_t value) { + TheStructure.Common.CsStall = value; + } + inline uint32_t getCsStall(void) const { return TheStructure.Common.CsStall; } + inline void setInlineData(const uint32_t value) { + TheStructure.Common.InlineData = value; + } + inline uint32_t getInlineData(void) const { + return TheStructure.Common.InlineData; + } + inline void setDataSize(const DATA_SIZE value) { + TheStructure.Common.DataSize = value; + } + inline DATA_SIZE getDataSize(void) const { + return static_cast(TheStructure.Common.DataSize); + } + inline void setPostSyncOperation(const POST_SYNC_OPERATION value) { + TheStructure.Common.Post_SyncOperation = value; + } + inline POST_SYNC_OPERATION getPostSyncOperation(void) const { + return static_cast( + TheStructure.Common.Post_SyncOperation); + } + inline void setMemoryType(const MEMORY_TYPE value) { + TheStructure.Common.MemoryType = value; + } + inline MEMORY_TYPE getMemoryType(void) const { + return static_cast(TheStructure.Common.MemoryType); + } + typedef enum tagMEMORYADDRESS { + MEMORYADDRESS_BIT_SHIFT = 0x2, + MEMORYADDRESS_ALIGN_SIZE = 0x4, + } MEMORYADDRESS; + inline void setMemoryAddress(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xfffffffcL); + TheStructure.Common.MemoryAddress = value >> MEMORYADDRESS_BIT_SHIFT; + } + inline uint32_t getMemoryAddress(void) const { + return TheStructure.Common.MemoryAddress << MEMORYADDRESS_BIT_SHIFT; + } + inline void setMemoryAddressHigh(const uint32_t value) { + TheStructure.Common.MemoryAddressHigh = value; + } + inline uint32_t getMemoryAddressHigh(void) const { + return TheStructure.Common.MemoryAddressHigh; + } + inline void setOperand1DataDword0(const uint32_t value) { + TheStructure.Common.Operand1DataDword0 = value; + } + inline uint32_t getOperand1DataDword0(void) const { + return TheStructure.Common.Operand1DataDword0; + } + inline void setOperand2DataDword0(const uint32_t value) { + TheStructure.Common.Operand2DataDword0 = value; + } + inline uint32_t getOperand2DataDword0(void) const { + return TheStructure.Common.Operand2DataDword0; + } + inline void setOperand1DataDword1(const uint32_t value) { + TheStructure.Common.Operand1DataDword1 = value; + } + inline uint32_t getOperand1DataDword1(void) const { + return TheStructure.Common.Operand1DataDword1; + } + inline void setOperand2DataDword1(const uint32_t value) { + TheStructure.Common.Operand2DataDword1 = value; + } + inline uint32_t getOperand2DataDword1(void) const { + return TheStructure.Common.Operand2DataDword1; + } + inline void setOperand1DataDword2(const uint32_t value) { + TheStructure.Common.Operand1DataDword2 = value; + } + inline uint32_t getOperand1DataDword2(void) const { + return TheStructure.Common.Operand1DataDword2; + } + inline void setOperand2DataDword2(const uint32_t value) { + TheStructure.Common.Operand2DataDword2 = value; + } + inline uint32_t getOperand2DataDword2(void) const { + return TheStructure.Common.Operand2DataDword2; + } + inline void setOperand1DataDword3(const uint32_t value) { + TheStructure.Common.Operand1DataDword3 = value; + } + inline uint32_t getOperand1DataDword3(void) const { + return TheStructure.Common.Operand1DataDword3; + } + inline void setOperand2DataDword3(const uint32_t value) { + TheStructure.Common.Operand2DataDword3 = value; + } + inline uint32_t getOperand2DataDword3(void) const { + return TheStructure.Common.Operand2DataDword3; + } +} MI_ATOMIC; +STATIC_ASSERT(44 == sizeof(MI_ATOMIC)); + +typedef struct tagMI_BATCH_BUFFER_END { + union tagTheStructure { + struct tagCommon { + uint32_t EndContext : BITFIELD_RANGE(0, 0); + uint32_t Reserved_1 : BITFIELD_RANGE(1, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_BATCH_BUFFER_END = 0xa, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_BATCH_BUFFER_END; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_BATCH_BUFFER_END sInit(void) { + MI_BATCH_BUFFER_END state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 1); + return TheStructure.RawData[index]; + } + inline void setEndContext(const bool value) { + TheStructure.Common.EndContext = value; + } + inline bool getEndContext(void) const { + return (TheStructure.Common.EndContext); + } +} MI_BATCH_BUFFER_END; +STATIC_ASSERT(4 == sizeof(MI_BATCH_BUFFER_END)); + +typedef struct tagMI_BATCH_BUFFER_START { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t AddressSpaceIndicator : BITFIELD_RANGE(8, 8); + uint32_t Reserved_9 : BITFIELD_RANGE(9, 9); + uint32_t ResourceStreamerEnable : BITFIELD_RANGE(10, 10); + uint32_t Reserved_11 : BITFIELD_RANGE(11, 14); + uint32_t PredicationEnable : BITFIELD_RANGE(15, 15); + uint32_t AddOffsetEnable : BITFIELD_RANGE(16, 16); + uint32_t Reserved_17 : BITFIELD_RANGE(17, 18); + uint32_t EnableCommandCache : BITFIELD_RANGE(19, 19); + uint32_t PoshEnable : BITFIELD_RANGE(20, 20); + uint32_t PoshStart : BITFIELD_RANGE(21, 21); + uint32_t SecondLevelBatchBuffer : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint64_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint64_t BatchBufferStartAddress : BITFIELD_RANGE(2, 47); + uint64_t BatchBufferStartAddress_Reserved_80 : BITFIELD_RANGE(48, 63); + } Common; + struct tagMi_Mode_Nestedbatchbufferenableis0 { + uint32_t Reserved_0 : BITFIELD_RANGE(0, 21); + uint32_t SecondLevelBatchBuffer : BITFIELD_RANGE(22, 22); + uint32_t Reserved_23 : BITFIELD_RANGE(23, 31); + uint64_t Reserved_32 : BITFIELD_RANGE(0, 47); + uint64_t Reserved_80 : BITFIELD_RANGE(48, 63); + } Mi_Mode_Nestedbatchbufferenableis0; + struct tagMi_Mode_Nestedbatchbufferenableis1 { + uint32_t Reserved_0 : BITFIELD_RANGE(0, 21); + uint32_t NestedLevelBatchBuffer : BITFIELD_RANGE(22, 22); + uint32_t Reserved_23 : BITFIELD_RANGE(23, 31); + uint64_t Reserved_32 : BITFIELD_RANGE(0, 47); + uint64_t Reserved_80 : BITFIELD_RANGE(48, 63); + } Mi_Mode_Nestedbatchbufferenableis1; + uint32_t RawData[3]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x1, + } DWORD_LENGTH; + typedef enum tagADDRESS_SPACE_INDICATOR { + ADDRESS_SPACE_INDICATOR_GGTT = 0x0, + ADDRESS_SPACE_INDICATOR_PPGTT = 0x1, + } ADDRESS_SPACE_INDICATOR; + typedef enum tagNESTED_LEVEL_BATCH_BUFFER { + NESTED_LEVEL_BATCH_BUFFER_CHAIN = 0x0, + NESTED_LEVEL_BATCH_BUFFER_NESTED = 0x1, + } NESTED_LEVEL_BATCH_BUFFER; + typedef enum tagSECOND_LEVEL_BATCH_BUFFER { + SECOND_LEVEL_BATCH_BUFFER_FIRST_LEVEL_BATCH = 0x0, + SECOND_LEVEL_BATCH_BUFFER_SECOND_LEVEL_BATCH = 0x1, + } SECOND_LEVEL_BATCH_BUFFER; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_BATCH_BUFFER_START = 0x31, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.AddressSpaceIndicator = ADDRESS_SPACE_INDICATOR_GGTT; + TheStructure.Common.SecondLevelBatchBuffer = SECOND_LEVEL_BATCH_BUFFER_FIRST_LEVEL_BATCH; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_BATCH_BUFFER_START; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + TheStructure.Mi_Mode_Nestedbatchbufferenableis1.NestedLevelBatchBuffer = NESTED_LEVEL_BATCH_BUFFER_CHAIN; + } + static tagMI_BATCH_BUFFER_START sInit(void) { + MI_BATCH_BUFFER_START state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 3); + return TheStructure.RawData[index]; + } + inline void setAddressSpaceIndicator(const ADDRESS_SPACE_INDICATOR value) { + TheStructure.Common.AddressSpaceIndicator = value; + } + inline ADDRESS_SPACE_INDICATOR getAddressSpaceIndicator(void) const { + return static_cast(TheStructure.Common.AddressSpaceIndicator); + } + inline void setResourceStreamerEnable(const bool value) { + TheStructure.Common.ResourceStreamerEnable = value; + } + inline bool getResourceStreamerEnable(void) const { + return TheStructure.Common.ResourceStreamerEnable; + } + inline void setPredicationEnable(const uint32_t value) { + TheStructure.Common.PredicationEnable = value; + } + inline uint32_t getPredicationEnable(void) const { + return TheStructure.Common.PredicationEnable; + } + inline void setAddOffsetEnable(const bool value) { + TheStructure.Common.AddOffsetEnable = value; + } + inline bool getAddOffsetEnable(void) const { + return TheStructure.Common.AddOffsetEnable; + } + inline void setEnableCommandCache(const uint32_t value) { + TheStructure.Common.EnableCommandCache = value; + } + inline uint32_t getEnableCommandCache(void) const { + return TheStructure.Common.EnableCommandCache; + } + inline void setPoshEnable(const uint32_t value) { + TheStructure.Common.PoshEnable = value; + } + inline uint32_t getPoshEnable(void) const { + return TheStructure.Common.PoshEnable; + } + inline void setPoshStart(const uint32_t value) { + TheStructure.Common.PoshStart = value; + } + inline uint32_t getPoshStart(void) const { + return TheStructure.Common.PoshStart; + } + inline void setSecondLevelBatchBuffer(const SECOND_LEVEL_BATCH_BUFFER value) { + TheStructure.Common.SecondLevelBatchBuffer = value; + } + inline SECOND_LEVEL_BATCH_BUFFER getSecondLevelBatchBuffer(void) const { + return static_cast(TheStructure.Common.SecondLevelBatchBuffer); + } + typedef enum tagBATCHBUFFERSTARTADDRESS { + BATCHBUFFERSTARTADDRESS_BIT_SHIFT = 0x2, + BATCHBUFFERSTARTADDRESS_ALIGN_SIZE = 0x4, + } BATCHBUFFERSTARTADDRESS; + inline void setBatchBufferStartAddress(const uint64_t value) { + TheStructure.Common.BatchBufferStartAddress = value >> BATCHBUFFERSTARTADDRESS_BIT_SHIFT; + } + inline void setBatchBufferStartAddressGraphicsaddress472(const uint64_t value) { + TheStructure.Common.BatchBufferStartAddress = value >> BATCHBUFFERSTARTADDRESS_BIT_SHIFT; + } + inline uint64_t getBatchBufferStartAddress(void) const { + return TheStructure.Common.BatchBufferStartAddress << BATCHBUFFERSTARTADDRESS_BIT_SHIFT; + } + inline uint64_t getBatchBufferStartAddressGraphicsaddress472(void) const { + return TheStructure.Common.BatchBufferStartAddress << BATCHBUFFERSTARTADDRESS_BIT_SHIFT; + } + inline void setNestedLevelBatchBuffer(const NESTED_LEVEL_BATCH_BUFFER value) { + TheStructure.Mi_Mode_Nestedbatchbufferenableis1.NestedLevelBatchBuffer = value; + } + inline NESTED_LEVEL_BATCH_BUFFER getNestedLevelBatchBuffer(void) const { + return static_cast(TheStructure.Mi_Mode_Nestedbatchbufferenableis1.NestedLevelBatchBuffer); + } +} MI_BATCH_BUFFER_START; +STATIC_ASSERT(12 == sizeof(MI_BATCH_BUFFER_START)); + +typedef struct tagMI_LOAD_REGISTER_IMM { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t ByteWriteDisables : BITFIELD_RANGE(8, 11); + uint32_t Reserved_12 : BITFIELD_RANGE(12, 16); + uint32_t MmioRemapEnable : BITFIELD_RANGE(17, 17); + uint32_t Reserved_13 : BITFIELD_RANGE(18, 18); + uint32_t AddCsMmioStartOffset : BITFIELD_RANGE(19, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint32_t RegisterOffset : BITFIELD_RANGE(2, 22); + uint32_t Reserved_55 : BITFIELD_RANGE(23, 31); + uint32_t DataDword; + } Common; + uint32_t RawData[3]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x1, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_LOAD_REGISTER_IMM = 0x22, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_LOAD_REGISTER_IMM; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_LOAD_REGISTER_IMM sInit(void) { + MI_LOAD_REGISTER_IMM state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 3); + return TheStructure.RawData[index]; + } + inline void setByteWriteDisables(const uint32_t value) { + TheStructure.Common.ByteWriteDisables = value; + } + inline uint32_t getByteWriteDisables(void) const { + return (TheStructure.Common.ByteWriteDisables); + } + inline void setAddCsMmioStartOffset(const uint32_t value) { + TheStructure.Common.AddCsMmioStartOffset = value; + } + inline uint32_t getAddCsMmioStartOffset(void) const { + return (TheStructure.Common.AddCsMmioStartOffset); + } + typedef enum tagREGISTEROFFSET { + REGISTEROFFSET_BIT_SHIFT = 0x2, + REGISTEROFFSET_ALIGN_SIZE = 0x4, + } REGISTEROFFSET; + inline void setRegisterOffset(const uint32_t value) { + TheStructure.Common.RegisterOffset = value >> REGISTEROFFSET_BIT_SHIFT; + } + inline uint32_t getRegisterOffset(void) const { + return (TheStructure.Common.RegisterOffset << REGISTEROFFSET_BIT_SHIFT); + } + inline void setDataDword(const uint32_t value) { + TheStructure.Common.DataDword = value; + } + inline uint32_t getDataDword(void) const { + return (TheStructure.Common.DataDword); + } + inline void setMmioRemapEnable(const bool value) { + TheStructure.Common.MmioRemapEnable = value; + } + inline bool getMmioRemapEnable(void) const { + return TheStructure.Common.MmioRemapEnable; + } +} MI_LOAD_REGISTER_IMM; +STATIC_ASSERT(12 == sizeof(MI_LOAD_REGISTER_IMM)); + +typedef struct tagMI_LOAD_REGISTER_MEM { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 16); + uint32_t MmioRemapEnable : BITFIELD_RANGE(17, 17); + uint32_t Reserved_18 : BITFIELD_RANGE(18, 18); + uint32_t AddCsMmioStartOffset : BITFIELD_RANGE(19, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 20); + uint32_t AsyncModeEnable : BITFIELD_RANGE(21, 21); + uint32_t UseGlobalGtt : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint32_t RegisterAddress : BITFIELD_RANGE(2, 22); + uint32_t Reserved_55 : BITFIELD_RANGE(23, 31); + uint64_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint64_t MemoryAddress : BITFIELD_RANGE(2, 63); + } Common; + uint32_t RawData[4]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x2, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_LOAD_REGISTER_MEM = 0x29, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_LOAD_REGISTER_MEM; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_LOAD_REGISTER_MEM sInit(void) { + MI_LOAD_REGISTER_MEM state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setMmioRemapEnable(const bool value) { + TheStructure.Common.MmioRemapEnable = value; + } + inline bool getMmioRemapEnable(void) const { + return TheStructure.Common.MmioRemapEnable; + } + inline void setAddCsMmioStartOffset(const uint32_t value) { + TheStructure.Common.AddCsMmioStartOffset = value; + } + inline uint32_t getAddCsMmioStartOffset(void) const { + return TheStructure.Common.AddCsMmioStartOffset; + } + inline void setAsyncModeEnable(const bool value) { + TheStructure.Common.AsyncModeEnable = value; + } + inline bool getAsyncModeEnable(void) const { + return TheStructure.Common.AsyncModeEnable; + } + inline void setUseGlobalGtt(const bool value) { + TheStructure.Common.UseGlobalGtt = value; + } + inline bool getUseGlobalGtt(void) const { + return TheStructure.Common.UseGlobalGtt; + } + typedef enum tagREGISTERADDRESS { + REGISTERADDRESS_BIT_SHIFT = 0x2, + REGISTERADDRESS_ALIGN_SIZE = 0x4, + } REGISTERADDRESS; + inline void setRegisterAddress(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x7ffffc); + TheStructure.Common.RegisterAddress = value >> REGISTERADDRESS_BIT_SHIFT; + } + inline uint32_t getRegisterAddress(void) const { + return TheStructure.Common.RegisterAddress << REGISTERADDRESS_BIT_SHIFT; + } + typedef enum tagMEMORYADDRESS { + MEMORYADDRESS_BIT_SHIFT = 0x2, + MEMORYADDRESS_ALIGN_SIZE = 0x4, + } MEMORYADDRESS; + inline void setMemoryAddress(const uint64_t value) { + DEBUG_BREAK_IF(value > 0xfffffffffffffffcL); + TheStructure.Common.MemoryAddress = value >> MEMORYADDRESS_BIT_SHIFT; + } + inline uint64_t getMemoryAddress(void) const { + return TheStructure.Common.MemoryAddress << MEMORYADDRESS_BIT_SHIFT; + } +} MI_LOAD_REGISTER_MEM; +STATIC_ASSERT(16 == sizeof(MI_LOAD_REGISTER_MEM)); + +typedef struct tagMI_LOAD_REGISTER_REG { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t MmioRemapEnableSource : BITFIELD_RANGE(16, 16); + uint32_t MmioRemapEnableDestination : BITFIELD_RANGE(17, 17); + uint32_t AddCsMmioStartOffsetSource : BITFIELD_RANGE(18, 18); + uint32_t AddCsMmioStartOffsetDestination : BITFIELD_RANGE(19, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint32_t SourceRegisterAddress : BITFIELD_RANGE(2, 22); + uint32_t Reserved_55 : BITFIELD_RANGE(23, 31); + uint32_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint32_t DestinationRegisterAddress : BITFIELD_RANGE(2, 22); + uint32_t Reserved_87 : BITFIELD_RANGE(23, 31); + } Common; + uint32_t RawData[3]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x1, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_LOAD_REGISTER_REG = 0x2a, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_LOAD_REGISTER_REG; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_LOAD_REGISTER_REG sInit(void) { + MI_LOAD_REGISTER_REG state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 3); + return TheStructure.RawData[index]; + } + inline void setMmioRemapEnableSource(const bool value) { + TheStructure.Common.MmioRemapEnableSource = value; + } + inline bool getMmioRemapEnableSource(void) const { + return TheStructure.Common.MmioRemapEnableSource; + } + inline void setMmioRemapEnableDestination(const bool value) { + TheStructure.Common.MmioRemapEnableDestination = value; + } + inline bool getMmioRemapEnableDestination(void) const { + return TheStructure.Common.MmioRemapEnableDestination; + } + inline void setAddCsMmioStartOffsetSource(const uint32_t value) { + TheStructure.Common.AddCsMmioStartOffsetSource = value; + } + inline uint32_t getAddCsMmioStartOffsetSource(void) const { + return TheStructure.Common.AddCsMmioStartOffsetSource; + } + inline void setAddCsMmioStartOffsetDestination(const uint32_t value) { + TheStructure.Common.AddCsMmioStartOffsetDestination = value; + } + inline uint32_t getAddCsMmioStartOffsetDestination(void) const { + return TheStructure.Common.AddCsMmioStartOffsetDestination; + } + typedef enum tagSOURCEREGISTERADDRESS { + SOURCEREGISTERADDRESS_BIT_SHIFT = 0x2, + SOURCEREGISTERADDRESS_ALIGN_SIZE = 0x4, + } SOURCEREGISTERADDRESS; + inline void setSourceRegisterAddress(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x7ffffc); + TheStructure.Common.SourceRegisterAddress = value >> SOURCEREGISTERADDRESS_BIT_SHIFT; + } + inline uint32_t getSourceRegisterAddress(void) const { + return TheStructure.Common.SourceRegisterAddress << SOURCEREGISTERADDRESS_BIT_SHIFT; + } + typedef enum tagDESTINATIONREGISTERADDRESS { + DESTINATIONREGISTERADDRESS_BIT_SHIFT = 0x2, + DESTINATIONREGISTERADDRESS_ALIGN_SIZE = 0x4, + } DESTINATIONREGISTERADDRESS; + inline void setDestinationRegisterAddress(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x7ffffc); + TheStructure.Common.DestinationRegisterAddress = value >> DESTINATIONREGISTERADDRESS_BIT_SHIFT; + } + inline uint32_t getDestinationRegisterAddress(void) const { + return TheStructure.Common.DestinationRegisterAddress << DESTINATIONREGISTERADDRESS_BIT_SHIFT; + } +} MI_LOAD_REGISTER_REG; +STATIC_ASSERT(12 == sizeof(MI_LOAD_REGISTER_REG)); + +typedef struct tagMI_NOOP { + union tagTheStructure { + struct tagCommon { + uint32_t IdentificationNumber : BITFIELD_RANGE(0, 21); + uint32_t IdentificationNumberRegisterWriteEnable : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_NOOP = 0x0, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_NOOP; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_NOOP sInit(void) { + MI_NOOP state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 1); + return TheStructure.RawData[index]; + } + inline void setIdentificationNumber(const uint32_t value) { + TheStructure.Common.IdentificationNumber = value; + } + inline uint32_t getIdentificationNumber(void) const { + return (TheStructure.Common.IdentificationNumber); + } + inline void setIdentificationNumberRegisterWriteEnable(const bool value) { + TheStructure.Common.IdentificationNumberRegisterWriteEnable = value; + } + inline bool getIdentificationNumberRegisterWriteEnable(void) const { + return (TheStructure.Common.IdentificationNumberRegisterWriteEnable); + } +} MI_NOOP; +STATIC_ASSERT(4 == sizeof(MI_NOOP)); + +typedef struct tagMI_STORE_REGISTER_MEM { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 16); + uint32_t MmioRemapEnable : BITFIELD_RANGE(17, 17); + uint32_t Reserved_18 : BITFIELD_RANGE(18, 18); + uint32_t AddCsMmioStartOffset : BITFIELD_RANGE(19, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 20); + uint32_t PredicateEnable : BITFIELD_RANGE(21, 21); + uint32_t UseGlobalGtt : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint32_t RegisterAddress : BITFIELD_RANGE(2, 22); + uint32_t Reserved_55 : BITFIELD_RANGE(23, 31); + uint64_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint64_t MemoryAddress : BITFIELD_RANGE(2, 63); + } Common; + uint32_t RawData[4]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x2, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_STORE_REGISTER_MEM = 0x24, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_STORE_REGISTER_MEM; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_STORE_REGISTER_MEM sInit(void) { + MI_STORE_REGISTER_MEM state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setMmioRemapEnable(const bool value) { + TheStructure.Common.MmioRemapEnable = value; + } + inline bool getMmioRemapEnable(void) const { + return TheStructure.Common.MmioRemapEnable; + } + inline void setAddCsMmioStartOffset(const uint32_t value) { + TheStructure.Common.AddCsMmioStartOffset = value; + } + inline uint32_t getAddCsMmioStartOffset(void) const { + return TheStructure.Common.AddCsMmioStartOffset; + } + inline void setPredicateEnable(const bool value) { + TheStructure.Common.PredicateEnable = value; + } + inline bool getPredicateEnable(void) const { + return TheStructure.Common.PredicateEnable; + } + inline void setUseGlobalGtt(const bool value) { + TheStructure.Common.UseGlobalGtt = value; + } + inline bool getUseGlobalGtt(void) const { + return TheStructure.Common.UseGlobalGtt; + } + typedef enum tagREGISTERADDRESS { + REGISTERADDRESS_BIT_SHIFT = 0x2, + REGISTERADDRESS_ALIGN_SIZE = 0x4, + } REGISTERADDRESS; + inline void setRegisterAddress(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x7ffffc); + TheStructure.Common.RegisterAddress = value >> REGISTERADDRESS_BIT_SHIFT; + } + inline uint32_t getRegisterAddress(void) const { + return TheStructure.Common.RegisterAddress << REGISTERADDRESS_BIT_SHIFT; + } + typedef enum tagMEMORYADDRESS { + MEMORYADDRESS_BIT_SHIFT = 0x2, + MEMORYADDRESS_ALIGN_SIZE = 0x4, + } MEMORYADDRESS; + inline void setMemoryAddress(const uint64_t value) { + DEBUG_BREAK_IF(value > 0xfffffffffffffffcL); + TheStructure.Common.MemoryAddress = value >> MEMORYADDRESS_BIT_SHIFT; + } + inline uint64_t getMemoryAddress(void) const { + return TheStructure.Common.MemoryAddress << MEMORYADDRESS_BIT_SHIFT; + } +} MI_STORE_REGISTER_MEM; +STATIC_ASSERT(16 == sizeof(MI_STORE_REGISTER_MEM)); + +typedef struct tagPIPELINE_SELECT { + union tagTheStructure { + struct tagCommon { + uint32_t PipelineSelection : BITFIELD_RANGE(0, 1); + uint32_t RenderSliceCommonPowerGateEnable : BITFIELD_RANGE(2, 2); + uint32_t RenderSamplerPowerGateEnable : BITFIELD_RANGE(3, 3); + uint32_t MediaSamplerDopClockGateEnable : BITFIELD_RANGE(4, 4); + uint32_t ForceMediaAwake : BITFIELD_RANGE(5, 5); + uint32_t MediaSamplerPowerClockGateDisable : BITFIELD_RANGE(6, 6); + uint32_t Reserved : BITFIELD_RANGE(7, 7); + uint32_t MaskBits : BITFIELD_RANGE(8, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + typedef enum tagPIPELINE_SELECTION { + PIPELINE_SELECTION_3D = 0x0, + PIPELINE_SELECTION_MEDIA = 0x1, + PIPELINE_SELECTION_GPGPU = 0x2, + } PIPELINE_SELECTION; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_PIPELINE_SELECT = 0x4, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED = 0x1, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_SINGLE_DW = 0x1, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.PipelineSelection = PIPELINE_SELECTION_3D; + TheStructure.Common._3DCommandSubOpcode = + _3D_COMMAND_SUB_OPCODE_PIPELINE_SELECT; + TheStructure.Common._3DCommandOpcode = + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_SINGLE_DW; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + } + static tagPIPELINE_SELECT sInit(void) { + PIPELINE_SELECT state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 1); + return TheStructure.RawData[index]; + } + inline void setPipelineSelection(const PIPELINE_SELECTION value) { + TheStructure.Common.PipelineSelection = value; + } + inline PIPELINE_SELECTION getPipelineSelection(void) const { + return static_cast( + TheStructure.Common.PipelineSelection); + } + inline void setRenderSliceCommonPowerGateEnable(const bool value) { + TheStructure.Common.RenderSliceCommonPowerGateEnable = value; + } + inline bool getRenderSliceCommonPowerGateEnable(void) const { + return TheStructure.Common.RenderSliceCommonPowerGateEnable; + } + inline void setRenderSamplerPowerGateEnable(const bool value) { + TheStructure.Common.RenderSamplerPowerGateEnable = value; + } + inline bool getRenderSamplerPowerGateEnable(void) const { + return TheStructure.Common.RenderSamplerPowerGateEnable; + } + inline void setMediaSamplerDopClockGateEnable(const bool value) { + TheStructure.Common.MediaSamplerDopClockGateEnable = value; + } + inline bool getMediaSamplerDopClockGateEnable(void) const { + return TheStructure.Common.MediaSamplerDopClockGateEnable; + } + inline void setForceMediaAwake(const bool value) { + TheStructure.Common.ForceMediaAwake = value; + } + inline bool getForceMediaAwake(void) const { + return TheStructure.Common.ForceMediaAwake; + } + inline void setMediaSamplerPowerClockGateDisable(const uint32_t value) { + TheStructure.Common.MediaSamplerPowerClockGateDisable = value; + } + inline uint32_t getMediaSamplerPowerClockGateDisable(void) const { + return TheStructure.Common.MediaSamplerPowerClockGateDisable; + } + inline void setMaskBits(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xff00); + TheStructure.Common.MaskBits = value; + } + inline uint32_t getMaskBits(void) const { + return TheStructure.Common.MaskBits; + } +} PIPELINE_SELECT; +STATIC_ASSERT(4 == sizeof(PIPELINE_SELECT)); + +typedef struct tagRENDER_SURFACE_STATE { + union tagTheStructure { + struct tagCommon { + uint32_t Reserved_0 : BITFIELD_RANGE(0, 5); + uint32_t MediaBoundaryPixelMode : BITFIELD_RANGE(6, 7); + uint32_t RenderCacheReadWriteMode : BITFIELD_RANGE(8, 8); + uint32_t SamplerL2OutOfOrderModeDisable : BITFIELD_RANGE(9, 9); + uint32_t VerticalLineStrideOffset : BITFIELD_RANGE(10, 10); + uint32_t VerticalLineStride : BITFIELD_RANGE(11, 11); + uint32_t TileMode : BITFIELD_RANGE(12, 13); + uint32_t SurfaceHorizontalAlignment : BITFIELD_RANGE(14, 15); + uint32_t SurfaceVerticalAlignment : BITFIELD_RANGE(16, 17); + uint32_t SurfaceFormat : BITFIELD_RANGE(18, 26); + uint32_t AstcEnable : BITFIELD_RANGE(27, 27); + uint32_t SurfaceArray : BITFIELD_RANGE(28, 28); + uint32_t SurfaceType : BITFIELD_RANGE(29, 31); + uint32_t SurfaceQpitch : BITFIELD_RANGE(0, 14); + uint32_t SampleTapDiscardDisable : BITFIELD_RANGE(15, 15); + uint32_t Reserved_48 : BITFIELD_RANGE(16, 17); + uint32_t CornerTexelMode : BITFIELD_RANGE(18, 18); + uint32_t BaseMipLevel : BITFIELD_RANGE(19, 23); + uint32_t MemoryObjectControlStateReserved_56 : BITFIELD_RANGE(24, 24); + uint32_t MemoryObjectControlStateIndexToMocsTables + : BITFIELD_RANGE(25, 30); + uint32_t EnableUnormPathInColorPipe : BITFIELD_RANGE(31, 31); + uint32_t Width : BITFIELD_RANGE(0, 13); + uint32_t Reserved_78 : BITFIELD_RANGE(14, 15); + uint32_t Height : BITFIELD_RANGE(16, 29); + uint32_t Reserved_94 : BITFIELD_RANGE(30, 31); + uint32_t SurfacePitch : BITFIELD_RANGE(0, 17); + uint32_t Reserved_114 : BITFIELD_RANGE(18, 18); + uint32_t StandardTilingModeExtensions : BITFIELD_RANGE(19, 19); + uint32_t TileAddressMappingMode : BITFIELD_RANGE(20, 20); + uint32_t Depth : BITFIELD_RANGE(21, 31); + uint32_t Reserved_128; + uint32_t MipCountLod : BITFIELD_RANGE(0, 3); + uint32_t SurfaceMinLod : BITFIELD_RANGE(4, 7); + uint32_t MipTailStartLod : BITFIELD_RANGE(8, 11); + uint32_t Reserved_172 : BITFIELD_RANGE(12, 13); + uint32_t CoherencyType : BITFIELD_RANGE(14, 14); + uint32_t Reserved_175 : BITFIELD_RANGE(15, 17); + uint32_t TiledResourceMode : BITFIELD_RANGE(18, 19); + uint32_t EwaDisableForCube : BITFIELD_RANGE(20, 20); + uint32_t YOffset : BITFIELD_RANGE(21, 23); + uint32_t Reserved_184 : BITFIELD_RANGE(24, 24); + uint32_t XOffset : BITFIELD_RANGE(25, 31); + uint32_t Reserved_192 : BITFIELD_RANGE(0, 14); + uint32_t YuvInterpolationEnable : BITFIELD_RANGE(15, 15); + uint32_t Reserved_208 : BITFIELD_RANGE(16, 31); + uint32_t ResourceMinLod : BITFIELD_RANGE(0, 11); + uint32_t Reserved_236 : BITFIELD_RANGE(12, 15); + uint32_t ShaderChannelSelectAlpha : BITFIELD_RANGE(16, 18); + uint32_t ShaderChannelSelectBlue : BITFIELD_RANGE(19, 21); + uint32_t ShaderChannelSelectGreen : BITFIELD_RANGE(22, 24); + uint32_t ShaderChannelSelectRed : BITFIELD_RANGE(25, 27); + uint32_t Reserved_252 : BITFIELD_RANGE(28, 29); + uint32_t MemoryCompressionEnable : BITFIELD_RANGE(30, 30); + uint32_t MemoryCompressionMode : BITFIELD_RANGE(31, 31); + uint64_t SurfaceBaseAddress; + uint64_t QuiltWidth : BITFIELD_RANGE(0, 4); + uint64_t QuiltHeight : BITFIELD_RANGE(5, 9); + uint64_t ClearValueAddressEnable : BITFIELD_RANGE(10, 10); + uint64_t Reserved_331 : BITFIELD_RANGE(11, 63); + uint32_t Reserved_384; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } Common; + struct tagSurfaceTypeIsSurftype_Cube { + uint32_t CubeFaceEnablePositiveZ : BITFIELD_RANGE(0, 0); + uint32_t CubeFaceEnableNegativeZ : BITFIELD_RANGE(1, 1); + uint32_t CubeFaceEnablePositiveY : BITFIELD_RANGE(2, 2); + uint32_t CubeFaceEnableNegativeY : BITFIELD_RANGE(3, 3); + uint32_t CubeFaceEnablePositiveX : BITFIELD_RANGE(4, 4); + uint32_t CubeFaceEnableNegativeX : BITFIELD_RANGE(5, 5); + uint32_t Reserved_6 : BITFIELD_RANGE(6, 31); + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t Reserved_384; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } SurfaceTypeIsSurftype_Cube; + struct tagSurfaceTypeIsnotSurftype_Cube { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t Reserved_384; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } SurfaceTypeIsnotSurftype_Cube; + struct tagSurfaceTypeIsnotSurftype_Strbuf { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t MultisamplePositionPaletteIndex : BITFIELD_RANGE(0, 2); + uint32_t NumberOfMultisamples : BITFIELD_RANGE(3, 5); + uint32_t MultisampledSurfaceStorageFormat : BITFIELD_RANGE(6, 6); + uint32_t RenderTargetViewExtent : BITFIELD_RANGE(7, 17); + uint32_t MinimumArrayElement : BITFIELD_RANGE(18, 28); + uint32_t RenderTargetAndSampleUnormRotation : BITFIELD_RANGE(29, 30); + uint32_t Reserved_159 : BITFIELD_RANGE(31, 31); + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t Reserved_384; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } SurfaceTypeIsnotSurftype_Strbuf; + struct tagSurfaceTypeIsSurftype_Strbuf { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t Reserved_384; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } SurfaceTypeIsSurftype_Strbuf; + struct tag_SurfaceFormatIsnotPlanar { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t AuxiliarySurfaceMode : BITFIELD_RANGE(0, 2); + uint32_t AuxiliarySurfacePitch : BITFIELD_RANGE(3, 11); + uint32_t Reserved_204 : BITFIELD_RANGE(12, 15); + uint32_t AuxiliarySurfaceQpitch : BITFIELD_RANGE(16, 30); + uint32_t Reserved_223 : BITFIELD_RANGE(31, 31); + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t Reserved_384; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } _SurfaceFormatIsnotPlanar; + struct tag_SurfaceFormatIsPlanar { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t YOffsetForUOrUvPlane : BITFIELD_RANGE(0, 13); + uint32_t Reserved_206 : BITFIELD_RANGE(14, 15); + uint32_t XOffsetForUOrUvPlane : BITFIELD_RANGE(16, 29); + uint32_t HalfPitchForChroma : BITFIELD_RANGE(30, 30); + uint32_t SeparateUvPlaneEnable : BITFIELD_RANGE(31, 31); + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320 : BITFIELD_RANGE(0, 31); + uint64_t YOffsetForVPlane : BITFIELD_RANGE(32, 45); + uint64_t Reserved_366 : BITFIELD_RANGE(46, 47); + uint64_t XOffsetForVPlane : BITFIELD_RANGE(48, 61); + uint64_t Reserved_382 : BITFIELD_RANGE(62, 63); + uint32_t Reserved_384; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } _SurfaceFormatIsPlanar; + struct tag_SurfaceFormatIsnotPlanarAndMemoryCompressionEnableIs0 { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320 : BITFIELD_RANGE(0, 11); + uint64_t AuxiliarySurfaceBaseAddress : BITFIELD_RANGE(12, 63); + uint32_t Reserved_384; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } _SurfaceFormatIsnotPlanarAndMemoryCompressionEnableIs0; + struct tagMemoryCompressionEnableIs1 { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320 : BITFIELD_RANGE(0, 11); + uint64_t AuxiliaryTableIndexForMediaCompressedSurface + : BITFIELD_RANGE(21, 31); + uint64_t Reserved_352 : BITFIELD_RANGE(32, 63); + uint32_t Reserved_384; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } MemoryCompressionEnableIs1; + struct tagClearValueAddressEnableIsEnable { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t Reserved_384 : BITFIELD_RANGE(0, 5); + uint32_t ClearColorAddress : BITFIELD_RANGE(6, 31); + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } ClearValueAddressEnableIsEnable; + struct + tag_AuxiliarySurfaceModeIsAux_HizAnd_ClearValueAddressEnableIsEnable { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t Reserved_384 : BITFIELD_RANGE(0, 5); + uint32_t ClearDepthAddressLow : BITFIELD_RANGE(6, 31); + uint32_t ClearDepthAddressHigh : BITFIELD_RANGE(0, 15); + uint32_t Reserved_432 : BITFIELD_RANGE(16, 31); + uint32_t Reserved_448; + uint32_t Reserved_480; + } _AuxiliarySurfaceModeIsAux_HizAnd_ClearValueAddressEnableIsEnable; + struct + tag_AuxiliarySurfaceModeIsnotAux_Ccs_DAnd_AuxiliarySurfaceModeIsnotAux_Ccs_EAnd_AuxiliarySurfaceModeIsnotAux_Hiz { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t Reserved_384; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } _AuxiliarySurfaceModeIsnotAux_Ccs_DAnd_AuxiliarySurfaceModeIsnotAux_Ccs_EAnd_AuxiliarySurfaceModeIsnotAux_Hiz; + struct tagAuxiliarySurfaceModeIsAux_Hiz { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + float HierarchicalDepthClearValue; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } AuxiliarySurfaceModeIsAux_Hiz; + struct tagAuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_E { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t RedClearColor; + uint32_t GreenClearColor; + uint32_t BlueClearColor; + uint32_t AlphaClearColor; + } AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_E; + struct + tag__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EOrAuxiliarySurfaceModeIsAux_HizAndClearValueAddressEnableIsDisable { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t RedClearColor; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } __AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EOrAuxiliarySurfaceModeIsAux_HizAndClearValueAddressEnableIsDisable; + struct + tag__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsEnable { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t Reserved_384 : BITFIELD_RANGE(0, 4); + uint32_t ClearColorConversionEnable : BITFIELD_RANGE(5, 5); + uint32_t Reserved_390 : BITFIELD_RANGE(6, 31); + uint32_t ClearColorAddressHigh : BITFIELD_RANGE(0, 15); + uint32_t Reserved_432 : BITFIELD_RANGE(16, 31); + uint32_t Reserved_448; + uint32_t Reserved_480; + } __AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsEnable; + struct + tag__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EOrAuxiliarySurfaceModeIsAux_HizAndClearValueAddressEnableIsEnable { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t Reserved_384; + uint32_t Reserved_416; + uint32_t Reserved_448; + uint32_t Reserved_480; + } __AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EOrAuxiliarySurfaceModeIsAux_HizAndClearValueAddressEnableIsEnable; + struct + tag__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsDisable { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + uint64_t Reserved_256; + uint64_t Reserved_320; + uint32_t Reserved_384; + uint32_t GreenClearColor; + uint32_t BlueClearColor; + uint32_t AlphaClearColor; + } __AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsDisable; + uint32_t RawData[16]; + } TheStructure; + typedef enum tagMEDIA_BOUNDARY_PIXEL_MODE { + MEDIA_BOUNDARY_PIXEL_MODE_NORMAL_MODE = 0x0, + MEDIA_BOUNDARY_PIXEL_MODE_PROGRESSIVE_FRAME = 0x2, + MEDIA_BOUNDARY_PIXEL_MODE_INTERLACED_FRAME = 0x3, + } MEDIA_BOUNDARY_PIXEL_MODE; + typedef enum tagRENDER_CACHE_READ_WRITE_MODE { + RENDER_CACHE_READ_WRITE_MODE_WRITE_ONLY_CACHE = 0x0, + RENDER_CACHE_READ_WRITE_MODE_READ_WRITE_CACHE = 0x1, + } RENDER_CACHE_READ_WRITE_MODE; + typedef enum tagTILE_MODE { + TILE_MODE_LINEAR = 0x0, + TILE_MODE_WMAJOR = 0x1, + TILE_MODE_XMAJOR = 0x2, + TILE_MODE_YMAJOR = 0x3, + } TILE_MODE; + typedef enum tagSURFACE_HORIZONTAL_ALIGNMENT { + SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_4 = 0x1, + SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_8 = 0x2, + SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_16 = 0x3, + } SURFACE_HORIZONTAL_ALIGNMENT; + typedef enum tagSURFACE_VERTICAL_ALIGNMENT { + SURFACE_VERTICAL_ALIGNMENT_VALIGN_4 = 0x1, + SURFACE_VERTICAL_ALIGNMENT_VALIGN_8 = 0x2, + SURFACE_VERTICAL_ALIGNMENT_VALIGN_16 = 0x3, + } SURFACE_VERTICAL_ALIGNMENT; + typedef enum tagSURFACE_FORMAT { + SURFACE_FORMAT_R32G32B32A32_FLOAT = 0x0, + SURFACE_FORMAT_R32G32B32A32_SINT = 0x1, + SURFACE_FORMAT_R32G32B32A32_UINT = 0x2, + SURFACE_FORMAT_R32G32B32A32_UNORM = 0x3, + SURFACE_FORMAT_R32G32B32A32_SNORM = 0x4, + SURFACE_FORMAT_R64G64_FLOAT = 0x5, + SURFACE_FORMAT_R32G32B32X32_FLOAT = 0x6, + SURFACE_FORMAT_R32G32B32A32_SSCALED = 0x7, + SURFACE_FORMAT_R32G32B32A32_USCALED = 0x8, + SURFACE_FORMAT_R32G32B32A32_SFIXED = 0x20, + SURFACE_FORMAT_R64G64_PASSTHRU = 0x21, + SURFACE_FORMAT_R32G32B32_FLOAT = 0x40, + SURFACE_FORMAT_R32G32B32_SINT = 0x41, + SURFACE_FORMAT_R32G32B32_UINT = 0x42, + SURFACE_FORMAT_R32G32B32_UNORM = 0x43, + SURFACE_FORMAT_R32G32B32_SNORM = 0x44, + SURFACE_FORMAT_R32G32B32_SSCALED = 0x45, + SURFACE_FORMAT_R32G32B32_USCALED = 0x46, + SURFACE_FORMAT_R32G32B32_SFIXED = 0x50, + SURFACE_FORMAT_R16G16B16A16_UNORM = 0x80, + SURFACE_FORMAT_R16G16B16A16_SNORM = 0x81, + SURFACE_FORMAT_R16G16B16A16_SINT = 0x82, + SURFACE_FORMAT_R16G16B16A16_UINT = 0x83, + SURFACE_FORMAT_R16G16B16A16_FLOAT = 0x84, + SURFACE_FORMAT_R32G32_FLOAT = 0x85, + SURFACE_FORMAT_R32G32_SINT = 0x86, + SURFACE_FORMAT_R32G32_UINT = 0x87, + SURFACE_FORMAT_R32_FLOAT_X8X24_TYPELESS = 0x88, + SURFACE_FORMAT_X32_TYPELESS_G8X24_UINT = 0x89, + SURFACE_FORMAT_L32A32_FLOAT = 0x8a, + SURFACE_FORMAT_R32G32_UNORM = 0x8b, + SURFACE_FORMAT_R32G32_SNORM = 0x8c, + SURFACE_FORMAT_R64_FLOAT = 0x8d, + SURFACE_FORMAT_R16G16B16X16_UNORM = 0x8e, + SURFACE_FORMAT_R16G16B16X16_FLOAT = 0x8f, + SURFACE_FORMAT_A32X32_FLOAT = 0x90, + SURFACE_FORMAT_L32X32_FLOAT = 0x91, + SURFACE_FORMAT_I32X32_FLOAT = 0x92, + SURFACE_FORMAT_R16G16B16A16_SSCALED = 0x93, + SURFACE_FORMAT_R16G16B16A16_USCALED = 0x94, + SURFACE_FORMAT_R32G32_SSCALED = 0x95, + SURFACE_FORMAT_R32G32_USCALED = 0x96, + SURFACE_FORMAT_R32G32_SFIXED = 0xa0, + SURFACE_FORMAT_R64_PASSTHRU = 0xa1, + SURFACE_FORMAT_B8G8R8A8_UNORM = 0xc0, + SURFACE_FORMAT_B8G8R8A8_UNORM_SRGB = 0xc1, + SURFACE_FORMAT_R10G10B10A2_UNORM = 0xc2, + SURFACE_FORMAT_R10G10B10A2_UNORM_SRGB = 0xc3, + SURFACE_FORMAT_R10G10B10A2_UINT = 0xc4, + SURFACE_FORMAT_R10G10B10_SNORM_A2_UNORM = 0xc5, + SURFACE_FORMAT_R8G8B8A8_UNORM = 0xc7, + SURFACE_FORMAT_R8G8B8A8_UNORM_SRGB = 0xc8, + SURFACE_FORMAT_R8G8B8A8_SNORM = 0xc9, + SURFACE_FORMAT_R8G8B8A8_SINT = 0xca, + SURFACE_FORMAT_R8G8B8A8_UINT = 0xcb, + SURFACE_FORMAT_R16G16_UNORM = 0xcc, + SURFACE_FORMAT_R16G16_SNORM = 0xcd, + SURFACE_FORMAT_R16G16_SINT = 0xce, + SURFACE_FORMAT_R16G16_UINT = 0xcf, + SURFACE_FORMAT_R16G16_FLOAT = 0xd0, + SURFACE_FORMAT_B10G10R10A2_UNORM = 0xd1, + SURFACE_FORMAT_B10G10R10A2_UNORM_SRGB = 0xd2, + SURFACE_FORMAT_R11G11B10_FLOAT = 0xd3, + SURFACE_FORMAT_R10G10B10_FLOAT_A2_UNORM = 0xd5, + SURFACE_FORMAT_R32_SINT = 0xd6, + SURFACE_FORMAT_R32_UINT = 0xd7, + SURFACE_FORMAT_R32_FLOAT = 0xd8, + SURFACE_FORMAT_R24_UNORM_X8_TYPELESS = 0xd9, + SURFACE_FORMAT_X24_TYPELESS_G8_UINT = 0xda, + SURFACE_FORMAT_L32_UNORM = 0xdd, + SURFACE_FORMAT_A32_UNORM = 0xde, + SURFACE_FORMAT_L16A16_UNORM = 0xdf, + SURFACE_FORMAT_I24X8_UNORM = 0xe0, + SURFACE_FORMAT_L24X8_UNORM = 0xe1, + SURFACE_FORMAT_A24X8_UNORM = 0xe2, + SURFACE_FORMAT_I32_FLOAT = 0xe3, + SURFACE_FORMAT_L32_FLOAT = 0xe4, + SURFACE_FORMAT_A32_FLOAT = 0xe5, + SURFACE_FORMAT_X8B8_UNORM_G8R8_SNORM = 0xe6, + SURFACE_FORMAT_A8X8_UNORM_G8R8_SNORM = 0xe7, + SURFACE_FORMAT_B8X8_UNORM_G8R8_SNORM = 0xe8, + SURFACE_FORMAT_B8G8R8X8_UNORM = 0xe9, + SURFACE_FORMAT_B8G8R8X8_UNORM_SRGB = 0xea, + SURFACE_FORMAT_R8G8B8X8_UNORM = 0xeb, + SURFACE_FORMAT_R8G8B8X8_UNORM_SRGB = 0xec, + SURFACE_FORMAT_R9G9B9E5_SHAREDEXP = 0xed, + SURFACE_FORMAT_B10G10R10X2_UNORM = 0xee, + SURFACE_FORMAT_L16A16_FLOAT = 0xf0, + SURFACE_FORMAT_R32_UNORM = 0xf1, + SURFACE_FORMAT_R32_SNORM = 0xf2, + SURFACE_FORMAT_R10G10B10X2_USCALED = 0xf3, + SURFACE_FORMAT_R8G8B8A8_SSCALED = 0xf4, + SURFACE_FORMAT_R8G8B8A8_USCALED = 0xf5, + SURFACE_FORMAT_R16G16_SSCALED = 0xf6, + SURFACE_FORMAT_R16G16_USCALED = 0xf7, + SURFACE_FORMAT_R32_SSCALED = 0xf8, + SURFACE_FORMAT_R32_USCALED = 0xf9, + SURFACE_FORMAT_B5G6R5_UNORM = 0x100, + SURFACE_FORMAT_B5G6R5_UNORM_SRGB = 0x101, + SURFACE_FORMAT_B5G5R5A1_UNORM = 0x102, + SURFACE_FORMAT_B5G5R5A1_UNORM_SRGB = 0x103, + SURFACE_FORMAT_B4G4R4A4_UNORM = 0x104, + SURFACE_FORMAT_B4G4R4A4_UNORM_SRGB = 0x105, + SURFACE_FORMAT_R8G8_UNORM = 0x106, + SURFACE_FORMAT_R8G8_SNORM = 0x107, + SURFACE_FORMAT_R8G8_SINT = 0x108, + SURFACE_FORMAT_R8G8_UINT = 0x109, + SURFACE_FORMAT_R16_UNORM = 0x10a, + SURFACE_FORMAT_R16_SNORM = 0x10b, + SURFACE_FORMAT_R16_SINT = 0x10c, + SURFACE_FORMAT_R16_UINT = 0x10d, + SURFACE_FORMAT_R16_FLOAT = 0x10e, + SURFACE_FORMAT_A8P8_UNORM_PALETTE0 = 0x10f, + SURFACE_FORMAT_A8P8_UNORM_PALETTE1 = 0x110, + SURFACE_FORMAT_I16_UNORM = 0x111, + SURFACE_FORMAT_L16_UNORM = 0x112, + SURFACE_FORMAT_A16_UNORM = 0x113, + SURFACE_FORMAT_L8A8_UNORM = 0x114, + SURFACE_FORMAT_I16_FLOAT = 0x115, + SURFACE_FORMAT_L16_FLOAT = 0x116, + SURFACE_FORMAT_A16_FLOAT = 0x117, + SURFACE_FORMAT_L8A8_UNORM_SRGB = 0x118, + SURFACE_FORMAT_R5G5_SNORM_B6_UNORM = 0x119, + SURFACE_FORMAT_B5G5R5X1_UNORM = 0x11a, + SURFACE_FORMAT_B5G5R5X1_UNORM_SRGB = 0x11b, + SURFACE_FORMAT_R8G8_SSCALED = 0x11c, + SURFACE_FORMAT_R8G8_USCALED = 0x11d, + SURFACE_FORMAT_R16_SSCALED = 0x11e, + SURFACE_FORMAT_R16_USCALED = 0x11f, + SURFACE_FORMAT_P8A8_UNORM_PALETTE0 = 0x122, + SURFACE_FORMAT_P8A8_UNORM_PALETTE1 = 0x123, + SURFACE_FORMAT_A1B5G5R5_UNORM = 0x124, + SURFACE_FORMAT_A4B4G4R4_UNORM = 0x125, + SURFACE_FORMAT_L8A8_UINT = 0x126, + SURFACE_FORMAT_L8A8_SINT = 0x127, + SURFACE_FORMAT_R8_UNORM = 0x140, + SURFACE_FORMAT_R8_SNORM = 0x141, + SURFACE_FORMAT_R8_SINT = 0x142, + SURFACE_FORMAT_R8_UINT = 0x143, + SURFACE_FORMAT_A8_UNORM = 0x144, + SURFACE_FORMAT_I8_UNORM = 0x145, + SURFACE_FORMAT_L8_UNORM = 0x146, + SURFACE_FORMAT_P4A4_UNORM_PALETTE0 = 0x147, + SURFACE_FORMAT_A4P4_UNORM_PALETTE0 = 0x148, + SURFACE_FORMAT_R8_SSCALED = 0x149, + SURFACE_FORMAT_R8_USCALED = 0x14a, + SURFACE_FORMAT_P8_UNORM_PALETTE0 = 0x14b, + SURFACE_FORMAT_L8_UNORM_SRGB = 0x14c, + SURFACE_FORMAT_P8_UNORM_PALETTE1 = 0x14d, + SURFACE_FORMAT_P4A4_UNORM_PALETTE1 = 0x14e, + SURFACE_FORMAT_A4P4_UNORM_PALETTE1 = 0x14f, + SURFACE_FORMAT_Y8_UNORM = 0x150, + SURFACE_FORMAT_L8_UINT = 0x152, + SURFACE_FORMAT_L8_SINT = 0x153, + SURFACE_FORMAT_I8_UINT = 0x154, + SURFACE_FORMAT_I8_SINT = 0x155, + SURFACE_FORMAT_DXT1_RGB_SRGB = 0x180, + SURFACE_FORMAT_R1_UNORM = 0x181, + SURFACE_FORMAT_YCRCB_NORMAL = 0x182, + SURFACE_FORMAT_YCRCB_SWAPUVY = 0x183, + SURFACE_FORMAT_P2_UNORM_PALETTE0 = 0x184, + SURFACE_FORMAT_P2_UNORM_PALETTE1 = 0x185, + SURFACE_FORMAT_BC1_UNORM = 0x186, + SURFACE_FORMAT_BC2_UNORM = 0x187, + SURFACE_FORMAT_BC3_UNORM = 0x188, + SURFACE_FORMAT_BC4_UNORM = 0x189, + SURFACE_FORMAT_BC5_UNORM = 0x18a, + SURFACE_FORMAT_BC1_UNORM_SRGB = 0x18b, + SURFACE_FORMAT_BC2_UNORM_SRGB = 0x18c, + SURFACE_FORMAT_BC3_UNORM_SRGB = 0x18d, + SURFACE_FORMAT_MONO8 = 0x18e, + SURFACE_FORMAT_YCRCB_SWAPUV = 0x18f, + SURFACE_FORMAT_YCRCB_SWAPY = 0x190, + SURFACE_FORMAT_DXT1_RGB = 0x191, + SURFACE_FORMAT_FXT1 = 0x192, + SURFACE_FORMAT_R8G8B8_UNORM = 0x193, + SURFACE_FORMAT_R8G8B8_SNORM = 0x194, + SURFACE_FORMAT_R8G8B8_SSCALED = 0x195, + SURFACE_FORMAT_R8G8B8_USCALED = 0x196, + SURFACE_FORMAT_R64G64B64A64_FLOAT = 0x197, + SURFACE_FORMAT_R64G64B64_FLOAT = 0x198, + SURFACE_FORMAT_BC4_SNORM = 0x199, + SURFACE_FORMAT_BC5_SNORM = 0x19a, + SURFACE_FORMAT_R16G16B16_FLOAT = 0x19b, + SURFACE_FORMAT_R16G16B16_UNORM = 0x19c, + SURFACE_FORMAT_R16G16B16_SNORM = 0x19d, + SURFACE_FORMAT_R16G16B16_SSCALED = 0x19e, + SURFACE_FORMAT_R16G16B16_USCALED = 0x19f, + SURFACE_FORMAT_BC6H_SF16 = 0x1a1, + SURFACE_FORMAT_BC7_UNORM = 0x1a2, + SURFACE_FORMAT_BC7_UNORM_SRGB = 0x1a3, + SURFACE_FORMAT_BC6H_UF16 = 0x1a4, + SURFACE_FORMAT_PLANAR_420_8 = 0x1a5, + SURFACE_FORMAT_PLANAR_420_16 = 0x1a6, + SURFACE_FORMAT_R8G8B8_UNORM_SRGB = 0x1a8, + SURFACE_FORMAT_ETC1_RGB8 = 0x1a9, + SURFACE_FORMAT_ETC2_RGB8 = 0x1aa, + SURFACE_FORMAT_EAC_R11 = 0x1ab, + SURFACE_FORMAT_EAC_RG11 = 0x1ac, + SURFACE_FORMAT_EAC_SIGNED_R11 = 0x1ad, + SURFACE_FORMAT_EAC_SIGNED_RG11 = 0x1ae, + SURFACE_FORMAT_ETC2_SRGB8 = 0x1af, + SURFACE_FORMAT_R16G16B16_UINT = 0x1b0, + SURFACE_FORMAT_R16G16B16_SINT = 0x1b1, + SURFACE_FORMAT_R32_SFIXED = 0x1b2, + SURFACE_FORMAT_R10G10B10A2_SNORM = 0x1b3, + SURFACE_FORMAT_R10G10B10A2_USCALED = 0x1b4, + SURFACE_FORMAT_R10G10B10A2_SSCALED = 0x1b5, + SURFACE_FORMAT_R10G10B10A2_SINT = 0x1b6, + SURFACE_FORMAT_B10G10R10A2_SNORM = 0x1b7, + SURFACE_FORMAT_B10G10R10A2_USCALED = 0x1b8, + SURFACE_FORMAT_B10G10R10A2_SSCALED = 0x1b9, + SURFACE_FORMAT_B10G10R10A2_UINT = 0x1ba, + SURFACE_FORMAT_B10G10R10A2_SINT = 0x1bb, + SURFACE_FORMAT_R64G64B64A64_PASSTHRU = 0x1bc, + SURFACE_FORMAT_R64G64B64_PASSTHRU = 0x1bd, + SURFACE_FORMAT_ETC2_RGB8_PTA = 0x1c0, + SURFACE_FORMAT_ETC2_SRGB8_PTA = 0x1c1, + SURFACE_FORMAT_ETC2_EAC_RGBA8 = 0x1c2, + SURFACE_FORMAT_ETC2_EAC_SRGB8_A8 = 0x1c3, + SURFACE_FORMAT_R8G8B8_UINT = 0x1c8, + SURFACE_FORMAT_R8G8B8_SINT = 0x1c9, + SURFACE_FORMAT_RAW = 0x1ff, + } SURFACE_FORMAT; + typedef enum tagSURFACE_TYPE { + SURFACE_TYPE_SURFTYPE_1D = 0x0, + SURFACE_TYPE_SURFTYPE_2D = 0x1, + SURFACE_TYPE_SURFTYPE_3D = 0x2, + SURFACE_TYPE_SURFTYPE_CUBE = 0x3, + SURFACE_TYPE_SURFTYPE_BUFFER = 0x4, + SURFACE_TYPE_SURFTYPE_STRBUF = 0x5, + SURFACE_TYPE_SURFTYPE_NULL = 0x7, + } SURFACE_TYPE; + typedef enum tagSAMPLE_TAP_DISCARD_DISABLE { + SAMPLE_TAP_DISCARD_DISABLE_DISABLE = 0x0, + SAMPLE_TAP_DISCARD_DISABLE_ENABLE = 0x1, + } SAMPLE_TAP_DISCARD_DISABLE; + typedef enum tagSTANDARD_TILING_MODE_EXTENSIONS { + STANDARD_TILING_MODE_EXTENSIONS_DISABLE = 0x0, + STANDARD_TILING_MODE_EXTENSIONS_ENABLE = 0x1, + } STANDARD_TILING_MODE_EXTENSIONS; + typedef enum tagTILE_ADDRESS_MAPPING_MODE { + TILE_ADDRESS_MAPPING_MODE_GEN9 = 0x0, + TILE_ADDRESS_MAPPING_MODE_GEN10 = 0x1, + } TILE_ADDRESS_MAPPING_MODE; + typedef enum tagNUMBER_OF_MULTISAMPLES { + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_1 = 0x0, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_2 = 0x1, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_4 = 0x2, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_8 = 0x3, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_16 = 0x4, + } NUMBER_OF_MULTISAMPLES; + typedef enum tagMULTISAMPLED_SURFACE_STORAGE_FORMAT { + MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS = 0x0, + MULTISAMPLED_SURFACE_STORAGE_FORMAT_DEPTH_STENCIL = 0x1, + } MULTISAMPLED_SURFACE_STORAGE_FORMAT; + typedef enum tagRENDER_TARGET_AND_SAMPLE_UNORM_ROTATION { + RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG = 0x0, + RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_90DEG = 0x1, + RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_180DEG = 0x2, + RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_270DEG = 0x3, + } RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION; + typedef enum tagCOHERENCY_TYPE { + COHERENCY_TYPE_GPU_COHERENT = 0x0, + COHERENCY_TYPE_IA_COHERENT = 0x1, + } COHERENCY_TYPE; + typedef enum tagTILED_RESOURCE_MODE { + TILED_RESOURCE_MODE_NONE = 0x0, + TILED_RESOURCE_MODE_4KB = 0x1, + TILED_RESOURCE_MODE_TILEYF = 0x1, + TILED_RESOURCE_MODE_64KB = 0x2, + TILED_RESOURCE_MODE_TILEYS = 0x2, + } TILED_RESOURCE_MODE; + typedef enum tagAUXILIARY_SURFACE_MODE { + AUXILIARY_SURFACE_MODE_AUX_NONE = 0x0, + AUXILIARY_SURFACE_MODE_AUX_CCS_D = 0x1, + AUXILIARY_SURFACE_MODE_AUX_APPEND = 0x2, + AUXILIARY_SURFACE_MODE_AUX_MCS_LCE = 0x4, + AUXILIARY_SURFACE_MODE_AUX_CCS_E = 0x5, + } AUXILIARY_SURFACE_MODE; + typedef enum tagHALF_PITCH_FOR_CHROMA { + HALF_PITCH_FOR_CHROMA_DISABLE = 0x0, + HALF_PITCH_FOR_CHROMA_ENABLE = 0x1, + } HALF_PITCH_FOR_CHROMA; + typedef enum tagSHADER_CHANNEL_SELECT { + SHADER_CHANNEL_SELECT_ZERO = 0x0, + SHADER_CHANNEL_SELECT_ONE = 0x1, + SHADER_CHANNEL_SELECT_RED = 0x4, + SHADER_CHANNEL_SELECT_GREEN = 0x5, + SHADER_CHANNEL_SELECT_BLUE = 0x6, + SHADER_CHANNEL_SELECT_ALPHA = 0x7, + } SHADER_CHANNEL_SELECT; + typedef enum tagMEMORY_COMPRESSION_MODE { + MEMORY_COMPRESSION_MODE_HORIZONTAL = 0x0, + MEMORY_COMPRESSION_MODE_VERTICAL = 0x1, + } MEMORY_COMPRESSION_MODE; + typedef enum tagCLEAR_COLOR_CONVERSION_ENABLE { + CLEAR_COLOR_CONVERSION_ENABLE_DISABLE = 0x0, + CLEAR_COLOR_CONVERSION_ENABLE_ENABLE = 0x1, + } CLEAR_COLOR_CONVERSION_ENABLE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.MediaBoundaryPixelMode = + MEDIA_BOUNDARY_PIXEL_MODE_NORMAL_MODE; + TheStructure.Common.RenderCacheReadWriteMode = + RENDER_CACHE_READ_WRITE_MODE_WRITE_ONLY_CACHE; + TheStructure.Common.TileMode = TILE_MODE_LINEAR; + TheStructure.Common.SurfaceType = SURFACE_TYPE_SURFTYPE_1D; + TheStructure.Common.SampleTapDiscardDisable = + SAMPLE_TAP_DISCARD_DISABLE_DISABLE; + TheStructure.Common.StandardTilingModeExtensions = + STANDARD_TILING_MODE_EXTENSIONS_DISABLE; + TheStructure.Common.TileAddressMappingMode = TILE_ADDRESS_MAPPING_MODE_GEN9; + TheStructure.Common.CoherencyType = COHERENCY_TYPE_GPU_COHERENT; + TheStructure.Common.TiledResourceMode = TILED_RESOURCE_MODE_NONE; + TheStructure.Common.ShaderChannelSelectAlpha = + SHADER_CHANNEL_SELECT_ZERO; + TheStructure.Common.ShaderChannelSelectBlue = + SHADER_CHANNEL_SELECT_ZERO; + TheStructure.Common.ShaderChannelSelectGreen = + SHADER_CHANNEL_SELECT_ZERO; + TheStructure.Common.ShaderChannelSelectRed = SHADER_CHANNEL_SELECT_ZERO; + TheStructure.Common.MemoryCompressionMode = + MEMORY_COMPRESSION_MODE_HORIZONTAL; + TheStructure.SurfaceTypeIsnotSurftype_Strbuf.NumberOfMultisamples = + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_1; + TheStructure.SurfaceTypeIsnotSurftype_Strbuf + .MultisampledSurfaceStorageFormat = + MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS; + TheStructure.SurfaceTypeIsnotSurftype_Strbuf + .RenderTargetAndSampleUnormRotation = + RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG; + TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceMode = + AUXILIARY_SURFACE_MODE_AUX_NONE; + TheStructure._SurfaceFormatIsPlanar.HalfPitchForChroma = + HALF_PITCH_FOR_CHROMA_DISABLE; + TheStructure.AuxiliarySurfaceModeIsAux_Hiz.HierarchicalDepthClearValue = + 0.0; + TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsEnable + .ClearColorConversionEnable = CLEAR_COLOR_CONVERSION_ENABLE_ENABLE; + } + static tagRENDER_SURFACE_STATE sInit(void) { + RENDER_SURFACE_STATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 16); + return TheStructure.RawData[index]; + } + inline void setMediaBoundaryPixelMode(const MEDIA_BOUNDARY_PIXEL_MODE value) { + TheStructure.Common.MediaBoundaryPixelMode = value; + } + inline MEDIA_BOUNDARY_PIXEL_MODE getMediaBoundaryPixelMode(void) const { + return static_cast( + TheStructure.Common.MediaBoundaryPixelMode); + } + inline void + setRenderCacheReadWriteMode(const RENDER_CACHE_READ_WRITE_MODE value) { + TheStructure.Common.RenderCacheReadWriteMode = value; + } + inline RENDER_CACHE_READ_WRITE_MODE getRenderCacheReadWriteMode(void) const { + return static_cast( + TheStructure.Common.RenderCacheReadWriteMode); + } + inline void setSamplerL2OutOfOrderModeDisable(const bool value) { + TheStructure.Common.SamplerL2OutOfOrderModeDisable = value; + } + inline bool getSamplerL2OutOfOrderModeDisable(void) const { + return TheStructure.Common.SamplerL2OutOfOrderModeDisable; + } + inline void setVerticalLineStrideOffset(const uint32_t value) { + TheStructure.Common.VerticalLineStrideOffset = value; + } + inline uint32_t getVerticalLineStrideOffset(void) const { + return TheStructure.Common.VerticalLineStrideOffset; + } + inline void setVerticalLineStride(const uint32_t value) { + TheStructure.Common.VerticalLineStride = value; + } + inline uint32_t getVerticalLineStride(void) const { + return TheStructure.Common.VerticalLineStride; + } + inline void setTileMode(const TILE_MODE value) { + TheStructure.Common.TileMode = value; + } + inline TILE_MODE getTileMode(void) const { + return static_cast(TheStructure.Common.TileMode); + } + inline void + setSurfaceHorizontalAlignment(const SURFACE_HORIZONTAL_ALIGNMENT value) { + TheStructure.Common.SurfaceHorizontalAlignment = value; + } + inline SURFACE_HORIZONTAL_ALIGNMENT + getSurfaceHorizontalAlignment(void) const { + return static_cast( + TheStructure.Common.SurfaceHorizontalAlignment); + } + inline void + setSurfaceVerticalAlignment(const SURFACE_VERTICAL_ALIGNMENT value) { + TheStructure.Common.SurfaceVerticalAlignment = value; + } + inline SURFACE_VERTICAL_ALIGNMENT getSurfaceVerticalAlignment(void) const { + return static_cast( + TheStructure.Common.SurfaceVerticalAlignment); + } + inline void setSurfaceFormat(const SURFACE_FORMAT value) { + TheStructure.Common.SurfaceFormat = value; + } + inline SURFACE_FORMAT getSurfaceFormat(void) const { + return static_cast(TheStructure.Common.SurfaceFormat); + } + inline void setAstcEnable(const bool value) { + TheStructure.Common.AstcEnable = value; + } + inline bool getAstcEnable(void) const { + return TheStructure.Common.AstcEnable; + } + inline void setSurfaceArray(const bool value) { + TheStructure.Common.SurfaceArray = value; + } + inline bool getSurfaceArray(void) const { + return TheStructure.Common.SurfaceArray; + } + inline void setSurfaceType(const SURFACE_TYPE value) { + TheStructure.Common.SurfaceType = value; + } + inline SURFACE_TYPE getSurfaceType(void) const { + return static_cast(TheStructure.Common.SurfaceType); + } + typedef enum tagSURFACEQPITCH { + SURFACEQPITCH_BIT_SHIFT = 0x2, + SURFACEQPITCH_ALIGN_SIZE = 0x4, + } SURFACEQPITCH; + inline void setSurfaceQpitch(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x7fff); + TheStructure.Common.SurfaceQpitch = value >> SURFACEQPITCH_BIT_SHIFT; + } + inline uint32_t getSurfaceQpitch(void) const { + return TheStructure.Common.SurfaceQpitch << SURFACEQPITCH_BIT_SHIFT; + } + inline void + setSampleTapDiscardDisable(const SAMPLE_TAP_DISCARD_DISABLE value) { + TheStructure.Common.SampleTapDiscardDisable = value; + } + inline SAMPLE_TAP_DISCARD_DISABLE getSampleTapDiscardDisable(void) const { + return static_cast( + TheStructure.Common.SampleTapDiscardDisable); + } + inline void setCornerTexelMode(const bool value) { + TheStructure.Common.CornerTexelMode = value; + } + inline bool getCornerTexelMode(void) const { + return TheStructure.Common.CornerTexelMode; + } + inline void setBaseMipLevel(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xf80000); + TheStructure.Common.BaseMipLevel = value; + } + inline uint32_t getBaseMipLevel(void) const { + return TheStructure.Common.BaseMipLevel; + } + inline void + setMemoryObjectControlStateIndexToMocsTables(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x7e000000L); + TheStructure.Common.MemoryObjectControlStateIndexToMocsTables = value >> 1; + } + inline uint32_t getMemoryObjectControlStateIndexToMocsTables(void) const { + return (TheStructure.Common.MemoryObjectControlStateIndexToMocsTables << 1); + } + inline void setMemoryObjectControlState(const uint32_t value) { + TheStructure.Common.MemoryObjectControlStateReserved_56 = value; + TheStructure.Common.MemoryObjectControlStateIndexToMocsTables = (value >> 1); + } + inline uint32_t getMemoryObjectControlState(void) const { + uint32_t mocs = TheStructure.Common.MemoryObjectControlStateReserved_56; + mocs |= (TheStructure.Common.MemoryObjectControlStateIndexToMocsTables << 1); + return (mocs); + } + inline void setEnableUnormPathInColorPipe(const uint32_t value) { + TheStructure.Common.EnableUnormPathInColorPipe = value; + } + inline uint32_t getEnableUnormPathInColorPipe(void) const { + return TheStructure.Common.EnableUnormPathInColorPipe; + } + inline void setWidth(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x3fff); + TheStructure.Common.Width = value - 1; + } + inline uint32_t getWidth(void) const { return TheStructure.Common.Width + 1; } + inline void setHeight(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x3fff0000); + TheStructure.Common.Height = value - 1; + } + inline uint32_t getHeight(void) const { + return TheStructure.Common.Height + 1; + } + inline void setSurfacePitch(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x3ffff); + TheStructure.Common.SurfacePitch = value - 1; + } + inline uint32_t getSurfacePitch(void) const { + return TheStructure.Common.SurfacePitch + 1; + } + inline void + setStandardTilingModeExtensions(const STANDARD_TILING_MODE_EXTENSIONS value) { + TheStructure.Common.StandardTilingModeExtensions = value; + } + inline STANDARD_TILING_MODE_EXTENSIONS + getStandardTilingModeExtensions(void) const { + return static_cast( + TheStructure.Common.StandardTilingModeExtensions); + } + inline void setTileAddressMappingMode(const TILE_ADDRESS_MAPPING_MODE value) { + TheStructure.Common.TileAddressMappingMode = value; + } + inline TILE_ADDRESS_MAPPING_MODE getTileAddressMappingMode(void) const { + return static_cast( + TheStructure.Common.TileAddressMappingMode); + } + inline void setDepth(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xffe00000L); + TheStructure.Common.Depth = value - 1; + } + inline uint32_t getDepth(void) const { return TheStructure.Common.Depth + 1; } + inline void setMipCountLod(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xf); + TheStructure.Common.MipCountLod = value; + } + inline uint32_t getMipCountLod(void) const { + return TheStructure.Common.MipCountLod; + } + inline void setSurfaceMinLod(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xf0); + TheStructure.Common.SurfaceMinLod = value; + } + inline uint32_t getSurfaceMinLod(void) const { + return TheStructure.Common.SurfaceMinLod; + } + inline void setMipTailStartLod(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xf00); + TheStructure.Common.MipTailStartLod = value; + } + inline uint32_t getMipTailStartLod(void) const { + return TheStructure.Common.MipTailStartLod; + } + inline void setCoherencyType(const COHERENCY_TYPE value) { + TheStructure.Common.CoherencyType = value; + } + inline COHERENCY_TYPE getCoherencyType(void) const { + return static_cast(TheStructure.Common.CoherencyType); + } + inline void setTiledResourceMode(const TILED_RESOURCE_MODE value) { + TheStructure.Common.TiledResourceMode = value; + } + inline TILED_RESOURCE_MODE getTiledResourceMode(void) const { + return static_cast( + TheStructure.Common.TiledResourceMode); + } + inline void setEwaDisableForCube(const bool value) { + TheStructure.Common.EwaDisableForCube = value; + } + inline bool getEwaDisableForCube(void) const { + return TheStructure.Common.EwaDisableForCube; + } + typedef enum tagYOFFSET { + YOFFSET_BIT_SHIFT = 0x2, + YOFFSET_ALIGN_SIZE = 0x4, + } YOFFSET; + inline void setYOffset(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xe00000); + TheStructure.Common.YOffset = value >> YOFFSET_BIT_SHIFT; + } + inline uint32_t getYOffset(void) const { + return TheStructure.Common.YOffset << YOFFSET_BIT_SHIFT; + } + typedef enum tagXOFFSET { + XOFFSET_BIT_SHIFT = 0x2, + XOFFSET_ALIGN_SIZE = 0x4, + } XOFFSET; + inline void setXOffset(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xfe000000L); + TheStructure.Common.XOffset = value >> XOFFSET_BIT_SHIFT; + } + inline uint32_t getXOffset(void) const { + return TheStructure.Common.XOffset << XOFFSET_BIT_SHIFT; + } + inline void setYuvInterpolationEnable(const bool value) { + TheStructure.Common.YuvInterpolationEnable = value; + } + inline bool getYuvInterpolationEnable(void) const { + return TheStructure.Common.YuvInterpolationEnable; + } + inline void setResourceMinLod(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xfff); + TheStructure.Common.ResourceMinLod = value; + } + inline uint32_t getResourceMinLod(void) const { + return TheStructure.Common.ResourceMinLod; + } + inline void setShaderChannelSelectAlpha(const SHADER_CHANNEL_SELECT value) { + TheStructure.Common.ShaderChannelSelectAlpha = value; + } + inline SHADER_CHANNEL_SELECT getShaderChannelSelectAlpha(void) const { + return static_cast( + TheStructure.Common.ShaderChannelSelectAlpha); + } + inline void setShaderChannelSelectBlue(const SHADER_CHANNEL_SELECT value) { + TheStructure.Common.ShaderChannelSelectBlue = value; + } + inline SHADER_CHANNEL_SELECT getShaderChannelSelectBlue(void) const { + return static_cast( + TheStructure.Common.ShaderChannelSelectBlue); + } + inline void setShaderChannelSelectGreen(const SHADER_CHANNEL_SELECT value) { + TheStructure.Common.ShaderChannelSelectGreen = value; + } + inline SHADER_CHANNEL_SELECT getShaderChannelSelectGreen(void) const { + return static_cast( + TheStructure.Common.ShaderChannelSelectGreen); + } + inline void setShaderChannelSelectRed(const SHADER_CHANNEL_SELECT value) { + TheStructure.Common.ShaderChannelSelectRed = value; + } + inline SHADER_CHANNEL_SELECT getShaderChannelSelectRed(void) const { + return static_cast( + TheStructure.Common.ShaderChannelSelectRed); + } + inline void setMemoryCompressionEnable(const bool value) { + TheStructure.Common.MemoryCompressionEnable = value; + } + inline bool getMemoryCompressionEnable(void) const { + return TheStructure.Common.MemoryCompressionEnable; + } + inline void setMemoryCompressionMode(const MEMORY_COMPRESSION_MODE value) { + TheStructure.Common.MemoryCompressionMode = value; + } + inline MEMORY_COMPRESSION_MODE getMemoryCompressionMode(void) const { + return static_cast( + TheStructure.Common.MemoryCompressionMode); + } + inline void setSurfaceBaseAddress(const uint64_t value) { + TheStructure.Common.SurfaceBaseAddress = value; + } + inline uint64_t getSurfaceBaseAddress(void) const { + return TheStructure.Common.SurfaceBaseAddress; + } + inline void setQuiltWidth(const uint64_t value) { + DEBUG_BREAK_IF(value > 0x1f); + TheStructure.Common.QuiltWidth = value; + } + inline uint64_t getQuiltWidth(void) const { + return TheStructure.Common.QuiltWidth; + } + inline void setQuiltHeight(const uint64_t value) { + DEBUG_BREAK_IF(value > 0x3e0); + TheStructure.Common.QuiltHeight = value; + } + inline uint64_t getQuiltHeight(void) const { + return TheStructure.Common.QuiltHeight; + } + inline void setClearValueAddressEnable(const bool value) { + TheStructure.Common.ClearValueAddressEnable = value; + } + inline bool getClearValueAddressEnable(void) const { + return TheStructure.Common.ClearValueAddressEnable; + } + inline void setCubeFaceEnablePositiveZ(const bool value) { + TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnablePositiveZ = value; + } + inline bool getCubeFaceEnablePositiveZ(void) const { + return TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnablePositiveZ; + } + inline void setCubeFaceEnableNegativeZ(const bool value) { + TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnableNegativeZ = value; + } + inline bool getCubeFaceEnableNegativeZ(void) const { + return TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnableNegativeZ; + } + inline void setCubeFaceEnablePositiveY(const bool value) { + TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnablePositiveY = value; + } + inline bool getCubeFaceEnablePositiveY(void) const { + return TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnablePositiveY; + } + inline void setCubeFaceEnableNegativeY(const bool value) { + TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnableNegativeY = value; + } + inline bool getCubeFaceEnableNegativeY(void) const { + return TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnableNegativeY; + } + inline void setCubeFaceEnablePositiveX(const bool value) { + TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnablePositiveX = value; + } + inline bool getCubeFaceEnablePositiveX(void) const { + return TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnablePositiveX; + } + inline void setCubeFaceEnableNegativeX(const bool value) { + TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnableNegativeX = value; + } + inline bool getCubeFaceEnableNegativeX(void) const { + return TheStructure.SurfaceTypeIsSurftype_Cube.CubeFaceEnableNegativeX; + } + inline void setMultisamplePositionPaletteIndex(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x7); + TheStructure.SurfaceTypeIsnotSurftype_Strbuf + .MultisamplePositionPaletteIndex = value; + } + inline uint32_t getMultisamplePositionPaletteIndex(void) const { + return TheStructure.SurfaceTypeIsnotSurftype_Strbuf + .MultisamplePositionPaletteIndex; + } + inline void setNumberOfMultisamples(const NUMBER_OF_MULTISAMPLES value) { + TheStructure.SurfaceTypeIsnotSurftype_Strbuf.NumberOfMultisamples = value; + } + inline NUMBER_OF_MULTISAMPLES getNumberOfMultisamples(void) const { + return static_cast( + TheStructure.SurfaceTypeIsnotSurftype_Strbuf.NumberOfMultisamples); + } + inline void setMultisampledSurfaceStorageFormat( + const MULTISAMPLED_SURFACE_STORAGE_FORMAT value) { + TheStructure.SurfaceTypeIsnotSurftype_Strbuf + .MultisampledSurfaceStorageFormat = value; + } + inline MULTISAMPLED_SURFACE_STORAGE_FORMAT + getMultisampledSurfaceStorageFormat(void) const { + return static_cast( + TheStructure.SurfaceTypeIsnotSurftype_Strbuf + .MultisampledSurfaceStorageFormat); + } + inline void setRenderTargetViewExtent(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x3ff80); + TheStructure.SurfaceTypeIsnotSurftype_Strbuf.RenderTargetViewExtent = + value - 1; + } + inline uint32_t getRenderTargetViewExtent(void) const { + return TheStructure.SurfaceTypeIsnotSurftype_Strbuf.RenderTargetViewExtent + + 1; + } + inline void setMinimumArrayElement(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x1ffc0000); + TheStructure.SurfaceTypeIsnotSurftype_Strbuf.MinimumArrayElement = value; + } + inline uint32_t getMinimumArrayElement(void) const { + return TheStructure.SurfaceTypeIsnotSurftype_Strbuf.MinimumArrayElement; + } + inline void setRenderTargetAndSampleUnormRotation( + const RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION value) { + TheStructure.SurfaceTypeIsnotSurftype_Strbuf + .RenderTargetAndSampleUnormRotation = value; + } + inline RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION + getRenderTargetAndSampleUnormRotation(void) const { + return static_cast( + TheStructure.SurfaceTypeIsnotSurftype_Strbuf + .RenderTargetAndSampleUnormRotation); + } + inline void setAuxiliarySurfaceMode(const AUXILIARY_SURFACE_MODE value) { + TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceMode = value; + } + inline AUXILIARY_SURFACE_MODE getAuxiliarySurfaceMode(void) const { + return static_cast( + TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceMode); + } + inline void setAuxiliarySurfacePitch(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xff8); + TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfacePitch = value - 1; + } + inline uint32_t getAuxiliarySurfacePitch(void) const { + return TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfacePitch + 1; + } + typedef enum tagAUXILIARYSURFACEQPITCH { + AUXILIARYSURFACEQPITCH_BIT_SHIFT = 0x2, + AUXILIARYSURFACEQPITCH_ALIGN_SIZE = 0x4, + } AUXILIARYSURFACEQPITCH; + inline void setAuxiliarySurfaceQpitch(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x7fff0000L); + TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch = + value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT; + } + inline uint32_t getAuxiliarySurfaceQpitch(void) const { + return TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch + << AUXILIARYSURFACEQPITCH_BIT_SHIFT; + } + inline void setYOffsetForUOrUvPlane(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x3fff); + TheStructure._SurfaceFormatIsPlanar.YOffsetForUOrUvPlane = value; + } + inline uint32_t getYOffsetForUOrUvPlane(void) const { + return TheStructure._SurfaceFormatIsPlanar.YOffsetForUOrUvPlane; + } + inline void setXOffsetForUOrUvPlane(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x3fff0000); + TheStructure._SurfaceFormatIsPlanar.XOffsetForUOrUvPlane = value; + } + inline uint32_t getXOffsetForUOrUvPlane(void) const { + return TheStructure._SurfaceFormatIsPlanar.XOffsetForUOrUvPlane; + } + inline void setHalfPitchForChroma(const HALF_PITCH_FOR_CHROMA value) { + TheStructure._SurfaceFormatIsPlanar.HalfPitchForChroma = value; + } + inline HALF_PITCH_FOR_CHROMA getHalfPitchForChroma(void) const { + return static_cast( + TheStructure._SurfaceFormatIsPlanar.HalfPitchForChroma); + } + inline void setSeparateUvPlaneEnable(const bool value) { + TheStructure._SurfaceFormatIsPlanar.SeparateUvPlaneEnable = value; + } + inline bool getSeparateUvPlaneEnable(void) const { + return TheStructure._SurfaceFormatIsPlanar.SeparateUvPlaneEnable; + } + inline void setYOffsetForVPlane(const uint64_t value) { + DEBUG_BREAK_IF(value > 0x3fff00000000L); + TheStructure._SurfaceFormatIsPlanar.YOffsetForVPlane = value; + } + inline uint64_t getYOffsetForVPlane(void) const { + return TheStructure._SurfaceFormatIsPlanar.YOffsetForVPlane; + } + inline void setXOffsetForVPlane(const uint64_t value) { + DEBUG_BREAK_IF(value > 0x3fff000000000000L); + TheStructure._SurfaceFormatIsPlanar.XOffsetForVPlane = value; + } + inline uint64_t getXOffsetForVPlane(void) const { + return TheStructure._SurfaceFormatIsPlanar.XOffsetForVPlane; + } + typedef enum tagAUXILIARYSURFACEBASEADDRESS { + AUXILIARYSURFACEBASEADDRESS_BIT_SHIFT = 0xc, + AUXILIARYSURFACEBASEADDRESS_ALIGN_SIZE = 0x1000, + } AUXILIARYSURFACEBASEADDRESS; + inline void setAuxiliarySurfaceBaseAddress(const uint64_t value) { + DEBUG_BREAK_IF(value > 0xfffffffffffff000L); + TheStructure._SurfaceFormatIsnotPlanarAndMemoryCompressionEnableIs0 + .AuxiliarySurfaceBaseAddress = + value >> AUXILIARYSURFACEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getAuxiliarySurfaceBaseAddress(void) const { + return TheStructure._SurfaceFormatIsnotPlanarAndMemoryCompressionEnableIs0 + .AuxiliarySurfaceBaseAddress + << AUXILIARYSURFACEBASEADDRESS_BIT_SHIFT; + } + inline void + setAuxiliaryTableIndexForMediaCompressedSurface(const uint64_t value) { + DEBUG_BREAK_IF(value > 0xffe00000L); + TheStructure.MemoryCompressionEnableIs1 + .AuxiliaryTableIndexForMediaCompressedSurface = value; + } + inline uint64_t getAuxiliaryTableIndexForMediaCompressedSurface(void) const { + return TheStructure.MemoryCompressionEnableIs1 + .AuxiliaryTableIndexForMediaCompressedSurface; + } + typedef enum tagCLEARCOLORADDRESS { + CLEARCOLORADDRESS_BIT_SHIFT = 0x6, + CLEARCOLORADDRESS_ALIGN_SIZE = 0x40, + } CLEARCOLORADDRESS; + inline void setClearColorAddress(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xffffffc0L); + TheStructure.ClearValueAddressEnableIsEnable.ClearColorAddress = + value >> CLEARCOLORADDRESS_BIT_SHIFT; + } + inline uint32_t getClearColorAddress(void) const { + return TheStructure.ClearValueAddressEnableIsEnable.ClearColorAddress + << CLEARCOLORADDRESS_BIT_SHIFT; + } + typedef enum tagCLEARDEPTHADDRESSLOW { + CLEARDEPTHADDRESSLOW_BIT_SHIFT = 0x6, + CLEARDEPTHADDRESSLOW_ALIGN_SIZE = 0x40, + } CLEARDEPTHADDRESSLOW; + inline void setClearDepthAddressLow(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xffffffc0L); + TheStructure + ._AuxiliarySurfaceModeIsAux_HizAnd_ClearValueAddressEnableIsEnable + .ClearDepthAddressLow = value >> CLEARDEPTHADDRESSLOW_BIT_SHIFT; + } + inline uint32_t getClearDepthAddressLow(void) const { + return TheStructure + ._AuxiliarySurfaceModeIsAux_HizAnd_ClearValueAddressEnableIsEnable + .ClearDepthAddressLow + << CLEARDEPTHADDRESSLOW_BIT_SHIFT; + } + inline void setClearDepthAddressHigh(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xffff); + TheStructure + ._AuxiliarySurfaceModeIsAux_HizAnd_ClearValueAddressEnableIsEnable + .ClearDepthAddressHigh = value; + } + inline uint32_t getClearDepthAddressHigh(void) const { + return TheStructure + ._AuxiliarySurfaceModeIsAux_HizAnd_ClearValueAddressEnableIsEnable + .ClearDepthAddressHigh; + } + inline void setHierarchicalDepthClearValue(const float value) { + TheStructure.AuxiliarySurfaceModeIsAux_Hiz.HierarchicalDepthClearValue = + value; + } + inline float getHierarchicalDepthClearValue(void) const { + return TheStructure.AuxiliarySurfaceModeIsAux_Hiz + .HierarchicalDepthClearValue; + } + inline void setRedClearColor(const uint32_t value) { + TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EOrAuxiliarySurfaceModeIsAux_HizAndClearValueAddressEnableIsDisable + .RedClearColor = value; + } + inline uint32_t getRedClearColor(void) const { + return TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EOrAuxiliarySurfaceModeIsAux_HizAndClearValueAddressEnableIsDisable + .RedClearColor; + } + inline void + setClearColorConversionEnable(const CLEAR_COLOR_CONVERSION_ENABLE value) { + TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsEnable + .ClearColorConversionEnable = value; + } + inline CLEAR_COLOR_CONVERSION_ENABLE + getClearColorConversionEnable(void) const { + return static_cast( + TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsEnable + .ClearColorConversionEnable); + } + inline void setClearColorAddressHigh(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff); + TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsEnable + .ClearColorAddressHigh = value; + } + inline uint32_t getClearColorAddressHigh(void) const { + return TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsEnable + .ClearColorAddressHigh; + } + inline void setGreenClearColor(const uint32_t value) { + TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsDisable + .GreenClearColor = value; + } + inline uint32_t getGreenClearColor(void) const { + return TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsDisable + .GreenClearColor; + } + inline void setBlueClearColor(const uint32_t value) { + TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsDisable + .BlueClearColor = value; + } + inline uint32_t getBlueClearColor(void) const { + return TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsDisable + .BlueClearColor; + } + inline void setAlphaClearColor(const uint32_t value) { + TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsDisable + .AlphaClearColor = value; + } + inline uint32_t getAlphaClearColor(void) const { + return TheStructure + .__AuxiliarySurfaceModeIsAux_Ccs_DOrAuxiliarySurfaceModeIsAux_Ccs_EAndClearValueAddressEnableIsDisable + .AlphaClearColor; + } +} RENDER_SURFACE_STATE; +STATIC_ASSERT(64 == sizeof(RENDER_SURFACE_STATE)); + +typedef struct tagSAMPLER_STATE { + union tagTheStructure { + struct tagCommon { + uint32_t LodAlgorithm : BITFIELD_RANGE(0, 0); + uint32_t TextureLodBias : BITFIELD_RANGE(1, 13); + uint32_t MinModeFilter : BITFIELD_RANGE(14, 16); + uint32_t MagModeFilter : BITFIELD_RANGE(17, 19); + uint32_t MipModeFilter : BITFIELD_RANGE(20, 21); + uint32_t Reserved_22 : BITFIELD_RANGE(22, 25); + uint32_t LowQualityCubeCornerMode : BITFIELD_RANGE(26, 26); + uint32_t LodPreclampMode : BITFIELD_RANGE(27, 28); + uint32_t TextureBorderColorMode : BITFIELD_RANGE(29, 29); + uint32_t CpsLodCompensationEnable : BITFIELD_RANGE(30, 30); + uint32_t SamplerDisable : BITFIELD_RANGE(31, 31); + uint32_t CubeSurfaceControlMode : BITFIELD_RANGE(0, 0); + uint32_t ShadowFunction : BITFIELD_RANGE(1, 3); + uint32_t ChromakeyMode : BITFIELD_RANGE(4, 4); + uint32_t ChromakeyIndex : BITFIELD_RANGE(5, 6); + uint32_t ChromakeyEnable : BITFIELD_RANGE(7, 7); + uint32_t MaxLod : BITFIELD_RANGE(8, 19); + uint32_t MinLod : BITFIELD_RANGE(20, 31); + uint32_t LodClampMagnificationMode : BITFIELD_RANGE(0, 0); + uint32_t SrgbDecode : BITFIELD_RANGE(1, 1); + uint32_t ReturnFilterWeightForNullTexels : BITFIELD_RANGE(2, 2); + uint32_t ReturnFilterWeightForBorderTexels : BITFIELD_RANGE(3, 3); + uint32_t Reserved_68 : BITFIELD_RANGE(4, 5); + uint32_t IndirectStatePointer : BITFIELD_RANGE(6, 23); + uint32_t Reserved_88 : BITFIELD_RANGE(24, 31); + uint32_t TczAddressControlMode : BITFIELD_RANGE(0, 2); + uint32_t TcyAddressControlMode : BITFIELD_RANGE(3, 5); + uint32_t TcxAddressControlMode : BITFIELD_RANGE(6, 8); + uint32_t ReductionTypeEnable : BITFIELD_RANGE(9, 9); + uint32_t NonNormalizedCoordinateEnable : BITFIELD_RANGE(10, 10); + uint32_t TrilinearFilterQuality : BITFIELD_RANGE(11, 12); + uint32_t RAddressMinFilterRoundingEnable : BITFIELD_RANGE(13, 13); + uint32_t RAddressMagFilterRoundingEnable : BITFIELD_RANGE(14, 14); + uint32_t VAddressMinFilterRoundingEnable : BITFIELD_RANGE(15, 15); + uint32_t VAddressMagFilterRoundingEnable : BITFIELD_RANGE(16, 16); + uint32_t UAddressMinFilterRoundingEnable : BITFIELD_RANGE(17, 17); + uint32_t UAddressMagFilterRoundingEnable : BITFIELD_RANGE(18, 18); + uint32_t MaximumAnisotropy : BITFIELD_RANGE(19, 21); + uint32_t ReductionType : BITFIELD_RANGE(22, 23); + uint32_t AllowLowQualityLodCalculation : BITFIELD_RANGE(24, 24); + uint32_t Reserved_121 : BITFIELD_RANGE(25, 25); + uint32_t LowQualityFilter : BITFIELD_RANGE(26, 26); + uint32_t Reserved_123 : BITFIELD_RANGE(27, 31); + } Common; + uint32_t RawData[4]; + } TheStructure; + typedef enum tagLOD_ALGORITHM { + LOD_ALGORITHM_LEGACY = 0x0, + LOD_ALGORITHM_EWA_APPROXIMATION = 0x1, + } LOD_ALGORITHM; + typedef enum tagMIN_MODE_FILTER { + MIN_MODE_FILTER_NEAREST = 0x0, + MIN_MODE_FILTER_LINEAR = 0x1, + MIN_MODE_FILTER_ANISOTROPIC = 0x2, + MIN_MODE_FILTER_MONO = 0x6, + } MIN_MODE_FILTER; + typedef enum tagMAG_MODE_FILTER { + MAG_MODE_FILTER_NEAREST = 0x0, + MAG_MODE_FILTER_LINEAR = 0x1, + MAG_MODE_FILTER_ANISOTROPIC = 0x2, + MAG_MODE_FILTER_MONO = 0x6, + } MAG_MODE_FILTER; + typedef enum tagMIP_MODE_FILTER { + MIP_MODE_FILTER_NONE = 0x0, + MIP_MODE_FILTER_NEAREST = 0x1, + MIP_MODE_FILTER_LINEAR = 0x3, + } MIP_MODE_FILTER; + typedef enum tagLOW_QUALITY_CUBE_CORNER_MODE { + LOW_QUALITY_CUBE_CORNER_MODE_DISABLE = 0x0, + LOW_QUALITY_CUBE_CORNER_MODE_ENABLE = 0x1, + } LOW_QUALITY_CUBE_CORNER_MODE; + typedef enum tagLOD_PRECLAMP_MODE { + LOD_PRECLAMP_MODE_NONE = 0x0, + LOD_PRECLAMP_MODE_OGL = 0x2, + } LOD_PRECLAMP_MODE; + typedef enum tagTEXTURE_BORDER_COLOR_MODE { + TEXTURE_BORDER_COLOR_MODE_OGL = 0x0, + TEXTURE_BORDER_COLOR_MODE_8BIT = 0x1, + } TEXTURE_BORDER_COLOR_MODE; + typedef enum tagCUBE_SURFACE_CONTROL_MODE { + CUBE_SURFACE_CONTROL_MODE_PROGRAMMED = 0x0, + CUBE_SURFACE_CONTROL_MODE_OVERRIDE = 0x1, + } CUBE_SURFACE_CONTROL_MODE; + typedef enum tagSHADOW_FUNCTION { + SHADOW_FUNCTION_PREFILTEROP_ALWAYS = 0x0, + SHADOW_FUNCTION_PREFILTEROP_NEVER = 0x1, + SHADOW_FUNCTION_PREFILTEROP_LESS = 0x2, + SHADOW_FUNCTION_PREFILTEROP_EQUAL = 0x3, + SHADOW_FUNCTION_PREFILTEROP_LEQUAL = 0x4, + SHADOW_FUNCTION_PREFILTEROP_GREATER = 0x5, + SHADOW_FUNCTION_PREFILTEROP_NOTEQUAL = 0x6, + SHADOW_FUNCTION_PREFILTEROP_GEQUAL = 0x7, + } SHADOW_FUNCTION; + typedef enum tagCHROMAKEY_MODE { + CHROMAKEY_MODE_KEYFILTER_KILL_ON_ANY_MATCH = 0x0, + CHROMAKEY_MODE_KEYFILTER_REPLACE_BLACK = 0x1, + } CHROMAKEY_MODE; + typedef enum tagLOD_CLAMP_MAGNIFICATION_MODE { + LOD_CLAMP_MAGNIFICATION_MODE_MIPNONE = 0x0, + LOD_CLAMP_MAGNIFICATION_MODE_MIPFILTER = 0x1, + } LOD_CLAMP_MAGNIFICATION_MODE; + typedef enum tagSRGB_DECODE { + SRGB_DECODE_DECODE_EXT = 0x0, + SRGB_DECODE_SKIP_DECODE_EXT = 0x1, + } SRGB_DECODE; + typedef enum tagRETURN_FILTER_WEIGHT_FOR_NULL_TEXELS { + RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_DISABLE = 0x0, + RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_ENABLE = 0x1, + } RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS; + typedef enum tagRETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS { + RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_DISABLE = 0x0, + RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_ENABLE = 0x1, + } RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS; + typedef enum tagTEXTURE_COORDINATE_MODE { + TEXTURE_COORDINATE_MODE_WRAP = 0x0, + TEXTURE_COORDINATE_MODE_MIRROR = 0x1, + TEXTURE_COORDINATE_MODE_CLAMP = 0x2, + TEXTURE_COORDINATE_MODE_CUBE = 0x3, + TEXTURE_COORDINATE_MODE_CLAMP_BORDER = 0x4, + TEXTURE_COORDINATE_MODE_MIRROR_ONCE = 0x5, + TEXTURE_COORDINATE_MODE_HALF_BORDER = 0x6, + TEXTURE_COORDINATE_MODE_MIRROR_101 = 0x7, + } TEXTURE_COORDINATE_MODE; + typedef enum tagTRILINEAR_FILTER_QUALITY { + TRILINEAR_FILTER_QUALITY_FULL = 0x0, + TRILINEAR_FILTER_QUALITY_TRIQUAL_HIGHMAG_CLAMP_MIPFILTER = 0x1, + TRILINEAR_FILTER_QUALITY_MED = 0x2, + TRILINEAR_FILTER_QUALITY_LOW = 0x3, + } TRILINEAR_FILTER_QUALITY; + typedef enum tagMAXIMUM_ANISOTROPY { + MAXIMUM_ANISOTROPY_RATIO_21 = 0x0, + MAXIMUM_ANISOTROPY_RATIO_41 = 0x1, + MAXIMUM_ANISOTROPY_RATIO_61 = 0x2, + MAXIMUM_ANISOTROPY_RATIO_81 = 0x3, + MAXIMUM_ANISOTROPY_RATIO_101 = 0x4, + MAXIMUM_ANISOTROPY_RATIO_121 = 0x5, + MAXIMUM_ANISOTROPY_RATIO_141 = 0x6, + MAXIMUM_ANISOTROPY_RATIO_161 = 0x7, + } MAXIMUM_ANISOTROPY; + typedef enum tagREDUCTION_TYPE { + REDUCTION_TYPE_STD_FILTER = 0x0, + REDUCTION_TYPE_COMPARISON = 0x1, + REDUCTION_TYPE_MINIMUM = 0x2, + REDUCTION_TYPE_MAXIMUM = 0x3, + } REDUCTION_TYPE; + typedef enum tagLOW_QUALITY_FILTER { + LOW_QUALITY_FILTER_DISABLE = 0x0, + LOW_QUALITY_FILTER_ENABLE = 0x1, + } LOW_QUALITY_FILTER; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.LodAlgorithm = LOD_ALGORITHM_LEGACY; + TheStructure.Common.MinModeFilter = MIN_MODE_FILTER_NEAREST; + TheStructure.Common.MagModeFilter = MAG_MODE_FILTER_NEAREST; + TheStructure.Common.MipModeFilter = MIP_MODE_FILTER_NONE; + TheStructure.Common.LowQualityCubeCornerMode = LOW_QUALITY_CUBE_CORNER_MODE_ENABLE; + TheStructure.Common.LodPreclampMode = LOD_PRECLAMP_MODE_NONE; + TheStructure.Common.TextureBorderColorMode = TEXTURE_BORDER_COLOR_MODE_OGL; + TheStructure.Common.CubeSurfaceControlMode = CUBE_SURFACE_CONTROL_MODE_PROGRAMMED; + TheStructure.Common.ShadowFunction = SHADOW_FUNCTION_PREFILTEROP_ALWAYS; + TheStructure.Common.ChromakeyMode = CHROMAKEY_MODE_KEYFILTER_KILL_ON_ANY_MATCH; + TheStructure.Common.LodClampMagnificationMode = LOD_CLAMP_MAGNIFICATION_MODE_MIPNONE; + TheStructure.Common.SrgbDecode = SRGB_DECODE_DECODE_EXT; + TheStructure.Common.ReturnFilterWeightForNullTexels = RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_DISABLE; + TheStructure.Common.ReturnFilterWeightForBorderTexels = RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_DISABLE; + TheStructure.Common.TczAddressControlMode = TEXTURE_COORDINATE_MODE_WRAP; + TheStructure.Common.TcyAddressControlMode = TEXTURE_COORDINATE_MODE_WRAP; + TheStructure.Common.TcxAddressControlMode = TEXTURE_COORDINATE_MODE_WRAP; + TheStructure.Common.TrilinearFilterQuality = TRILINEAR_FILTER_QUALITY_FULL; + TheStructure.Common.MaximumAnisotropy = MAXIMUM_ANISOTROPY_RATIO_21; + TheStructure.Common.ReductionType = REDUCTION_TYPE_STD_FILTER; + TheStructure.Common.LowQualityFilter = LOW_QUALITY_FILTER_DISABLE; + } + static tagSAMPLER_STATE sInit(void) { + SAMPLER_STATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setLodAlgorithm(const LOD_ALGORITHM value) { + TheStructure.Common.LodAlgorithm = value; + } + inline LOD_ALGORITHM getLodAlgorithm(void) const { + return static_cast(TheStructure.Common.LodAlgorithm); + } + inline void setTextureLodBias(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x3ffe); + TheStructure.Common.TextureLodBias = value; + } + inline uint32_t getTextureLodBias(void) const { + return TheStructure.Common.TextureLodBias; + } + inline void setMinModeFilter(const MIN_MODE_FILTER value) { + TheStructure.Common.MinModeFilter = value; + } + inline MIN_MODE_FILTER getMinModeFilter(void) const { + return static_cast(TheStructure.Common.MinModeFilter); + } + inline void setMagModeFilter(const MAG_MODE_FILTER value) { + TheStructure.Common.MagModeFilter = value; + } + inline MAG_MODE_FILTER getMagModeFilter(void) const { + return static_cast(TheStructure.Common.MagModeFilter); + } + inline void setMipModeFilter(const MIP_MODE_FILTER value) { + TheStructure.Common.MipModeFilter = value; + } + inline MIP_MODE_FILTER getMipModeFilter(void) const { + return static_cast(TheStructure.Common.MipModeFilter); + } + inline void setLowQualityCubeCornerMode(const LOW_QUALITY_CUBE_CORNER_MODE value) { + TheStructure.Common.LowQualityCubeCornerMode = value; + } + inline LOW_QUALITY_CUBE_CORNER_MODE getLowQualityCubeCornerMode(void) const { + return static_cast(TheStructure.Common.LowQualityCubeCornerMode); + } + inline void setLodPreclampMode(const LOD_PRECLAMP_MODE value) { + TheStructure.Common.LodPreclampMode = value; + } + inline LOD_PRECLAMP_MODE getLodPreclampMode(void) const { + return static_cast(TheStructure.Common.LodPreclampMode); + } + inline void setTextureBorderColorMode(const TEXTURE_BORDER_COLOR_MODE value) { + TheStructure.Common.TextureBorderColorMode = value; + } + inline TEXTURE_BORDER_COLOR_MODE getTextureBorderColorMode(void) const { + return static_cast(TheStructure.Common.TextureBorderColorMode); + } + inline void setCpsLodCompensationEnable(const bool value) { + TheStructure.Common.CpsLodCompensationEnable = value; + } + inline bool getCpsLodCompensationEnable(void) const { + return TheStructure.Common.CpsLodCompensationEnable; + } + inline void setSamplerDisable(const bool value) { + TheStructure.Common.SamplerDisable = value; + } + inline bool getSamplerDisable(void) const { + return TheStructure.Common.SamplerDisable; + } + inline void setCubeSurfaceControlMode(const CUBE_SURFACE_CONTROL_MODE value) { + TheStructure.Common.CubeSurfaceControlMode = value; + } + inline CUBE_SURFACE_CONTROL_MODE getCubeSurfaceControlMode(void) const { + return static_cast(TheStructure.Common.CubeSurfaceControlMode); + } + inline void setShadowFunction(const SHADOW_FUNCTION value) { + TheStructure.Common.ShadowFunction = value; + } + inline SHADOW_FUNCTION getShadowFunction(void) const { + return static_cast(TheStructure.Common.ShadowFunction); + } + inline void setChromakeyMode(const CHROMAKEY_MODE value) { + TheStructure.Common.ChromakeyMode = value; + } + inline CHROMAKEY_MODE getChromakeyMode(void) const { + return static_cast(TheStructure.Common.ChromakeyMode); + } + inline void setChromakeyIndex(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x60); + TheStructure.Common.ChromakeyIndex = value; + } + inline uint32_t getChromakeyIndex(void) const { + return TheStructure.Common.ChromakeyIndex; + } + inline void setChromakeyEnable(const bool value) { + TheStructure.Common.ChromakeyEnable = value; + } + inline bool getChromakeyEnable(void) const { + return TheStructure.Common.ChromakeyEnable; + } + inline void setMaxLod(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xfff00); + TheStructure.Common.MaxLod = value; + } + inline uint32_t getMaxLod(void) const { + return TheStructure.Common.MaxLod; + } + inline void setMinLod(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xfff00000L); + TheStructure.Common.MinLod = value; + } + inline uint32_t getMinLod(void) const { + return TheStructure.Common.MinLod; + } + inline void setLodClampMagnificationMode(const LOD_CLAMP_MAGNIFICATION_MODE value) { + TheStructure.Common.LodClampMagnificationMode = value; + } + inline LOD_CLAMP_MAGNIFICATION_MODE getLodClampMagnificationMode(void) const { + return static_cast(TheStructure.Common.LodClampMagnificationMode); + } + inline void setSrgbDecode(const SRGB_DECODE value) { + TheStructure.Common.SrgbDecode = value; + } + inline SRGB_DECODE getSrgbDecode(void) const { + return static_cast(TheStructure.Common.SrgbDecode); + } + inline void setReturnFilterWeightForNullTexels(const RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS value) { + TheStructure.Common.ReturnFilterWeightForNullTexels = value; + } + inline RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS getReturnFilterWeightForNullTexels(void) const { + return static_cast(TheStructure.Common.ReturnFilterWeightForNullTexels); + } + inline void setReturnFilterWeightForBorderTexels(const RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS value) { + TheStructure.Common.ReturnFilterWeightForBorderTexels = value; + } + inline RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS getReturnFilterWeightForBorderTexels(void) const { + return static_cast(TheStructure.Common.ReturnFilterWeightForBorderTexels); + } + typedef enum tagINDIRECTSTATEPOINTER { + INDIRECTSTATEPOINTER_BIT_SHIFT = 0x6, + INDIRECTSTATEPOINTER_ALIGN_SIZE = 0x40, + } INDIRECTSTATEPOINTER; + inline void setIndirectStatePointer(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xffffc0); + TheStructure.Common.IndirectStatePointer = static_cast(value) >> INDIRECTSTATEPOINTER_BIT_SHIFT; + } + inline uint32_t getIndirectStatePointer(void) const { + return TheStructure.Common.IndirectStatePointer << INDIRECTSTATEPOINTER_BIT_SHIFT; + } + inline void setTczAddressControlMode(const TEXTURE_COORDINATE_MODE value) { + TheStructure.Common.TczAddressControlMode = value; + } + inline TEXTURE_COORDINATE_MODE getTczAddressControlMode(void) const { + return static_cast(TheStructure.Common.TczAddressControlMode); + } + inline void setTcyAddressControlMode(const TEXTURE_COORDINATE_MODE value) { + TheStructure.Common.TcyAddressControlMode = value; + } + inline TEXTURE_COORDINATE_MODE getTcyAddressControlMode(void) const { + return static_cast(TheStructure.Common.TcyAddressControlMode); + } + inline void setTcxAddressControlMode(const TEXTURE_COORDINATE_MODE value) { + TheStructure.Common.TcxAddressControlMode = value; + } + inline TEXTURE_COORDINATE_MODE getTcxAddressControlMode(void) const { + return static_cast(TheStructure.Common.TcxAddressControlMode); + } + inline void setReductionTypeEnable(const bool value) { + TheStructure.Common.ReductionTypeEnable = value; + } + inline bool getReductionTypeEnable(void) const { + return TheStructure.Common.ReductionTypeEnable; + } + inline void setNonNormalizedCoordinateEnable(const bool value) { + TheStructure.Common.NonNormalizedCoordinateEnable = value; + } + inline bool getNonNormalizedCoordinateEnable(void) const { + return TheStructure.Common.NonNormalizedCoordinateEnable; + } + inline void setTrilinearFilterQuality(const TRILINEAR_FILTER_QUALITY value) { + TheStructure.Common.TrilinearFilterQuality = value; + } + inline TRILINEAR_FILTER_QUALITY getTrilinearFilterQuality(void) const { + return static_cast(TheStructure.Common.TrilinearFilterQuality); + } + inline void setRAddressMinFilterRoundingEnable(const bool value) { + TheStructure.Common.RAddressMinFilterRoundingEnable = value; + } + inline bool getRAddressMinFilterRoundingEnable(void) const { + return TheStructure.Common.RAddressMinFilterRoundingEnable; + } + inline void setRAddressMagFilterRoundingEnable(const bool value) { + TheStructure.Common.RAddressMagFilterRoundingEnable = value; + } + inline bool getRAddressMagFilterRoundingEnable(void) const { + return TheStructure.Common.RAddressMagFilterRoundingEnable; + } + inline void setVAddressMinFilterRoundingEnable(const bool value) { + TheStructure.Common.VAddressMinFilterRoundingEnable = value; + } + inline bool getVAddressMinFilterRoundingEnable(void) const { + return TheStructure.Common.VAddressMinFilterRoundingEnable; + } + inline void setVAddressMagFilterRoundingEnable(const bool value) { + TheStructure.Common.VAddressMagFilterRoundingEnable = value; + } + inline bool getVAddressMagFilterRoundingEnable(void) const { + return TheStructure.Common.VAddressMagFilterRoundingEnable; + } + inline void setUAddressMinFilterRoundingEnable(const bool value) { + TheStructure.Common.UAddressMinFilterRoundingEnable = value; + } + inline bool getUAddressMinFilterRoundingEnable(void) const { + return TheStructure.Common.UAddressMinFilterRoundingEnable; + } + inline void setUAddressMagFilterRoundingEnable(const bool value) { + TheStructure.Common.UAddressMagFilterRoundingEnable = value; + } + inline bool getUAddressMagFilterRoundingEnable(void) const { + return TheStructure.Common.UAddressMagFilterRoundingEnable; + } + inline void setMaximumAnisotropy(const MAXIMUM_ANISOTROPY value) { + TheStructure.Common.MaximumAnisotropy = value; + } + inline MAXIMUM_ANISOTROPY getMaximumAnisotropy(void) const { + return static_cast(TheStructure.Common.MaximumAnisotropy); + } + inline void setReductionType(const REDUCTION_TYPE value) { + TheStructure.Common.ReductionType = value; + } + inline REDUCTION_TYPE getReductionType(void) const { + return static_cast(TheStructure.Common.ReductionType); + } + inline void setLowQualityFilter(const LOW_QUALITY_FILTER value) { + TheStructure.Common.LowQualityFilter = value; + } + inline LOW_QUALITY_FILTER getLowQualityFilter(void) const { + return static_cast(TheStructure.Common.LowQualityFilter); + } + inline void setAllowLowQualityLodCalculation(const bool value) { + TheStructure.Common.AllowLowQualityLodCalculation = value; + } + inline bool getAllowLowQualityLodCalculation(void) const { + return TheStructure.Common.AllowLowQualityLodCalculation; + } +} SAMPLER_STATE; +STATIC_ASSERT(16 == sizeof(SAMPLER_STATE)); + +typedef struct tagSTATE_BASE_ADDRESS { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint64_t GeneralStateBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_33 : BITFIELD_RANGE(1, 3); + uint64_t GeneralStateMemoryObjectControlState_Reserved : BITFIELD_RANGE(4, 4); + uint64_t GeneralStateMemoryObjectControlState_IndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_43 : BITFIELD_RANGE(11, 11); + uint64_t GeneralStateBaseAddress : BITFIELD_RANGE(12, 63); + uint32_t Reserved_96 : BITFIELD_RANGE(0, 15); + uint32_t StatelessDataPortAccessMemoryObjectControlState_Reserved : BITFIELD_RANGE(16, 16); + uint32_t StatelessDataPortAccessMemoryObjectControlState_IndexToMocsTables : BITFIELD_RANGE(17, 22); + uint32_t Reserved_119 : BITFIELD_RANGE(23, 31); + uint64_t SurfaceStateBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_129 : BITFIELD_RANGE(1, 3); + uint64_t SurfaceStateMemoryObjectControlState_Reserved : BITFIELD_RANGE(4, 4); + uint64_t SurfaceStateMemoryObjectControlState_IndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_139 : BITFIELD_RANGE(11, 11); + uint64_t SurfaceStateBaseAddress : BITFIELD_RANGE(12, 63); + uint64_t DynamicStateBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_193 : BITFIELD_RANGE(1, 3); + uint64_t DynamicStateMemoryObjectControlState_Reserved : BITFIELD_RANGE(4, 4); + uint64_t DynamicStateMemoryObjectControlState_IndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_203 : BITFIELD_RANGE(11, 11); + uint64_t DynamicStateBaseAddress : BITFIELD_RANGE(12, 63); + uint64_t IndirectObjectBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_257 : BITFIELD_RANGE(1, 3); + uint64_t IndirectObjectMemoryObjectControlState_Reserved : BITFIELD_RANGE(4, 4); + uint64_t IndirectObjectMemoryObjectControlState_IndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_267 : BITFIELD_RANGE(11, 11); + uint64_t IndirectObjectBaseAddress : BITFIELD_RANGE(12, 63); + uint64_t InstructionBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_321 : BITFIELD_RANGE(1, 3); + uint64_t InstructionMemoryObjectControlState_Reserved : BITFIELD_RANGE(4, 4); + uint64_t InstructionMemoryObjectControlState_IndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_331 : BITFIELD_RANGE(11, 11); + uint64_t InstructionBaseAddress : BITFIELD_RANGE(12, 63); + uint32_t GeneralStateBufferSizeModifyEnable : BITFIELD_RANGE(0, 0); + uint32_t Reserved_385 : BITFIELD_RANGE(1, 11); + uint32_t GeneralStateBufferSize : BITFIELD_RANGE(12, 31); + uint32_t DynamicStateBufferSizeModifyEnable : BITFIELD_RANGE(0, 0); + uint32_t Reserved_417 : BITFIELD_RANGE(1, 11); + uint32_t DynamicStateBufferSize : BITFIELD_RANGE(12, 31); + uint32_t IndirectObjectBufferSizeModifyEnable : BITFIELD_RANGE(0, 0); + uint32_t Reserved_449 : BITFIELD_RANGE(1, 11); + uint32_t IndirectObjectBufferSize : BITFIELD_RANGE(12, 31); + uint32_t InstructionBufferSizeModifyEnable : BITFIELD_RANGE(0, 0); + uint32_t Reserved_481 : BITFIELD_RANGE(1, 11); + uint32_t InstructionBufferSize : BITFIELD_RANGE(12, 31); + uint64_t BindlessSurfaceStateBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_513 : BITFIELD_RANGE(1, 3); + uint64_t BindlessSurfaceStateMemoryObjectControlState_Reserved : BITFIELD_RANGE(4, 4); + uint64_t BindlessSurfaceStateMemoryObjectControlState_IndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_523 : BITFIELD_RANGE(11, 11); + uint64_t BindlessSurfaceStateBaseAddress : BITFIELD_RANGE(12, 63); + uint32_t Reserved_576 : BITFIELD_RANGE(0, 11); + uint32_t BindlessSurfaceStateSize : BITFIELD_RANGE(12, 31); + uint64_t BindlessSamplerStateBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_609 : BITFIELD_RANGE(1, 3); + uint64_t BindlessSamplerStateMemoryObjectControlState_Reserved : BITFIELD_RANGE(4, 4); + uint64_t BindlessSamplerStateMemoryObjectControlState_IndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_619 : BITFIELD_RANGE(11, 11); + uint64_t BindlessSamplerStateBaseAddress : BITFIELD_RANGE(12, 63); + uint32_t Reserved_672 : BITFIELD_RANGE(0, 11); + uint32_t BindlessSamplerStateBufferSize : BITFIELD_RANGE(12, 31); + } Common; + uint32_t RawData[22]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x14, + } DWORD_LENGTH; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_STATE_BASE_ADDRESS = 0x1, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED = 0x1, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_COMMON = 0x0, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagPATCH_CONSTANTS { + GENERALSTATEBASEADDRESS_BYTEOFFSET = 0x4, + GENERALSTATEBASEADDRESS_INDEX = 0x1, + SURFACESTATEBASEADDRESS_BYTEOFFSET = 0x10, + SURFACESTATEBASEADDRESS_INDEX = 0x4, + DYNAMICSTATEBASEADDRESS_BYTEOFFSET = 0x18, + DYNAMICSTATEBASEADDRESS_INDEX = 0x6, + INDIRECTOBJECTBASEADDRESS_BYTEOFFSET = 0x20, + INDIRECTOBJECTBASEADDRESS_INDEX = 0x8, + INSTRUCTIONBASEADDRESS_BYTEOFFSET = 0x28, + INSTRUCTIONBASEADDRESS_INDEX = 0xa, + BINDLESSSURFACESTATEBASEADDRESS_BYTEOFFSET = 0x40, + BINDLESSSURFACESTATEBASEADDRESS_INDEX = 0x10, + BINDLESSSAMPLERSTATEBASEADDRESS_BYTEOFFSET = 0x4c, + BINDLESSSAMPLERSTATEBASEADDRESS_INDEX = 0x13, + } PATCH_CONSTANTS; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_STATE_BASE_ADDRESS; + TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_COMMON; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + } + static tagSTATE_BASE_ADDRESS sInit(void) { + STATE_BASE_ADDRESS state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 22); + return TheStructure.RawData[index]; + } + inline void setGeneralStateBaseAddressModifyEnable(const bool value) { + TheStructure.Common.GeneralStateBaseAddressModifyEnable = value; + } + inline bool getGeneralStateBaseAddressModifyEnable(void) const { + return (TheStructure.Common.GeneralStateBaseAddressModifyEnable); + } + inline void setGeneralStateMemoryObjectControlStateReserved(const uint64_t value) { + TheStructure.Common.GeneralStateMemoryObjectControlState_Reserved = value; + } + inline uint64_t getGeneralStateMemoryObjectControlStateReserved(void) const { + return (TheStructure.Common.GeneralStateMemoryObjectControlState_Reserved); + } + inline void setGeneralStateMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + TheStructure.Common.GeneralStateMemoryObjectControlState_IndexToMocsTables = value >> 1; + } + inline uint64_t getGeneralStateMemoryObjectControlStateIndexToMocsTables(void) const { + return (TheStructure.Common.GeneralStateMemoryObjectControlState_IndexToMocsTables << 1); + } + typedef enum tagGENERALSTATEBASEADDRESS { + GENERALSTATEBASEADDRESS_BIT_SHIFT = 0xc, + GENERALSTATEBASEADDRESS_ALIGN_SIZE = 0x1000, + } GENERALSTATEBASEADDRESS; + inline void setGeneralStateBaseAddress(const uint64_t value) { + TheStructure.Common.GeneralStateBaseAddress = value >> GENERALSTATEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getGeneralStateBaseAddress(void) const { + return (TheStructure.Common.GeneralStateBaseAddress << GENERALSTATEBASEADDRESS_BIT_SHIFT); + } + inline void setStatelessDataPortAccessMemoryObjectControlStateReserved(const uint32_t value) { + TheStructure.Common.StatelessDataPortAccessMemoryObjectControlState_Reserved = value; + } + inline uint32_t getStatelessDataPortAccessMemoryObjectControlStateReserved(void) const { + return (TheStructure.Common.StatelessDataPortAccessMemoryObjectControlState_Reserved); + } + inline void setStatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables(const uint32_t value) { + TheStructure.Common.StatelessDataPortAccessMemoryObjectControlState_IndexToMocsTables = value >> 1; + } + inline uint32_t getStatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables(void) const { + return (TheStructure.Common.StatelessDataPortAccessMemoryObjectControlState_IndexToMocsTables << 1); + } + inline void setStatelessDataPortAccessMemoryObjectControlState(const uint32_t value) { + TheStructure.Common.StatelessDataPortAccessMemoryObjectControlState_Reserved = value; + TheStructure.Common.StatelessDataPortAccessMemoryObjectControlState_IndexToMocsTables = (value >> 1); + } + inline uint32_t getStatelessDataPortAccessMemoryObjectControlState(void) const { + uint32_t mocs = TheStructure.Common.StatelessDataPortAccessMemoryObjectControlState_Reserved; + mocs |= (TheStructure.Common.StatelessDataPortAccessMemoryObjectControlState_IndexToMocsTables << 1); + return (mocs); + } + inline void setSurfaceStateBaseAddressModifyEnable(const bool value) { + TheStructure.Common.SurfaceStateBaseAddressModifyEnable = value; + } + inline bool getSurfaceStateBaseAddressModifyEnable(void) const { + return (TheStructure.Common.SurfaceStateBaseAddressModifyEnable); + } + inline void setSurfaceStateMemoryObjectControlStateReserved(const uint64_t value) { + TheStructure.Common.SurfaceStateMemoryObjectControlState_Reserved = value; + } + inline uint64_t getSurfaceStateMemoryObjectControlStateReserved(void) const { + return (TheStructure.Common.SurfaceStateMemoryObjectControlState_Reserved); + } + inline void setSurfaceStateMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + TheStructure.Common.SurfaceStateMemoryObjectControlState_IndexToMocsTables = value >> 1; + } + inline uint64_t getSurfaceStateMemoryObjectControlStateIndexToMocsTables(void) const { + return (TheStructure.Common.SurfaceStateMemoryObjectControlState_IndexToMocsTables << 1); + } + typedef enum tagSURFACESTATEBASEADDRESS { + SURFACESTATEBASEADDRESS_BIT_SHIFT = 0xc, + SURFACESTATEBASEADDRESS_ALIGN_SIZE = 0x1000, + } SURFACESTATEBASEADDRESS; + inline void setSurfaceStateBaseAddress(const uint64_t value) { + TheStructure.Common.SurfaceStateBaseAddress = value >> SURFACESTATEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getSurfaceStateBaseAddress(void) const { + return (TheStructure.Common.SurfaceStateBaseAddress << SURFACESTATEBASEADDRESS_BIT_SHIFT); + } + inline void setDynamicStateBaseAddressModifyEnable(const bool value) { + TheStructure.Common.DynamicStateBaseAddressModifyEnable = value; + } + inline bool getDynamicStateBaseAddressModifyEnable(void) const { + return (TheStructure.Common.DynamicStateBaseAddressModifyEnable); + } + inline void setDynamicStateMemoryObjectControlStateReserved(const uint64_t value) { + TheStructure.Common.DynamicStateMemoryObjectControlState_Reserved = value; + } + inline uint64_t getDynamicStateMemoryObjectControlStateReserved(void) const { + return (TheStructure.Common.DynamicStateMemoryObjectControlState_Reserved); + } + inline void setDynamicStateMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + TheStructure.Common.DynamicStateMemoryObjectControlState_IndexToMocsTables = value >> 1; + } + inline uint64_t getDynamicStateMemoryObjectControlStateIndexToMocsTables(void) const { + return (TheStructure.Common.DynamicStateMemoryObjectControlState_IndexToMocsTables << 1); + } + typedef enum tagDYNAMICSTATEBASEADDRESS { + DYNAMICSTATEBASEADDRESS_BIT_SHIFT = 0xc, + DYNAMICSTATEBASEADDRESS_ALIGN_SIZE = 0x1000, + } DYNAMICSTATEBASEADDRESS; + inline void setDynamicStateBaseAddress(const uint64_t value) { + TheStructure.Common.DynamicStateBaseAddress = value >> DYNAMICSTATEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getDynamicStateBaseAddress(void) const { + return (TheStructure.Common.DynamicStateBaseAddress << DYNAMICSTATEBASEADDRESS_BIT_SHIFT); + } + inline void setIndirectObjectBaseAddressModifyEnable(const bool value) { + TheStructure.Common.IndirectObjectBaseAddressModifyEnable = value; + } + inline bool getIndirectObjectBaseAddressModifyEnable(void) const { + return (TheStructure.Common.IndirectObjectBaseAddressModifyEnable); + } + inline void setIndirectObjectMemoryObjectControlStateReserved(const uint64_t value) { + TheStructure.Common.IndirectObjectMemoryObjectControlState_Reserved = value; + } + inline uint64_t getIndirectObjectMemoryObjectControlStateReserved(void) const { + return (TheStructure.Common.IndirectObjectMemoryObjectControlState_Reserved); + } + inline void setIndirectObjectMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + TheStructure.Common.IndirectObjectMemoryObjectControlState_IndexToMocsTables = value >> 1; + } + inline uint64_t getIndirectObjectMemoryObjectControlStateIndexToMocsTables(void) const { + return (TheStructure.Common.IndirectObjectMemoryObjectControlState_IndexToMocsTables << 1); + } + typedef enum tagINDIRECTOBJECTBASEADDRESS { + INDIRECTOBJECTBASEADDRESS_BIT_SHIFT = 0xc, + INDIRECTOBJECTBASEADDRESS_ALIGN_SIZE = 0x1000, + } INDIRECTOBJECTBASEADDRESS; + inline void setIndirectObjectBaseAddress(const uint64_t value) { + TheStructure.Common.IndirectObjectBaseAddress = value >> INDIRECTOBJECTBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getIndirectObjectBaseAddress(void) const { + return (TheStructure.Common.IndirectObjectBaseAddress << INDIRECTOBJECTBASEADDRESS_BIT_SHIFT); + } + inline void setInstructionBaseAddressModifyEnable(const bool value) { + TheStructure.Common.InstructionBaseAddressModifyEnable = value; + } + inline bool getInstructionBaseAddressModifyEnable(void) const { + return (TheStructure.Common.InstructionBaseAddressModifyEnable); + } + inline void setInstructionMemoryObjectControlStateReserved(const uint64_t value) { + TheStructure.Common.InstructionMemoryObjectControlState_Reserved = value; + } + inline uint64_t getInstructionMemoryObjectControlStateReserved(void) const { + return (TheStructure.Common.InstructionMemoryObjectControlState_Reserved); + } + inline void setInstructionMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + TheStructure.Common.InstructionMemoryObjectControlState_IndexToMocsTables = value >> 1; + } + inline uint64_t getInstructionMemoryObjectControlStateIndexToMocsTables(void) const { + return (TheStructure.Common.InstructionMemoryObjectControlState_IndexToMocsTables << 1); + } + inline void setInstructionMemoryObjectControlState(const uint32_t value) { + uint64_t val = static_cast(value); + TheStructure.Common.InstructionMemoryObjectControlState_Reserved = val; + TheStructure.Common.InstructionMemoryObjectControlState_IndexToMocsTables = (val >> 1); + } + inline uint32_t getInstructionMemoryObjectControlState(void) const { + uint64_t mocs = TheStructure.Common.InstructionMemoryObjectControlState_Reserved; + mocs |= (TheStructure.Common.InstructionMemoryObjectControlState_IndexToMocsTables << 1); + return static_cast(mocs); + } + typedef enum tagINSTRUCTIONBASEADDRESS { + INSTRUCTIONBASEADDRESS_BIT_SHIFT = 0xc, + INSTRUCTIONBASEADDRESS_ALIGN_SIZE = 0x1000, + } INSTRUCTIONBASEADDRESS; + inline void setInstructionBaseAddress(const uint64_t value) { + TheStructure.Common.InstructionBaseAddress = value >> INSTRUCTIONBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getInstructionBaseAddress(void) const { + return (TheStructure.Common.InstructionBaseAddress << INSTRUCTIONBASEADDRESS_BIT_SHIFT); + } + inline void setGeneralStateBufferSizeModifyEnable(const bool value) { + TheStructure.Common.GeneralStateBufferSizeModifyEnable = value; + } + inline bool getGeneralStateBufferSizeModifyEnable(void) const { + return (TheStructure.Common.GeneralStateBufferSizeModifyEnable); + } + inline void setGeneralStateBufferSize(const uint32_t value) { + TheStructure.Common.GeneralStateBufferSize = value; + } + inline uint32_t getGeneralStateBufferSize(void) const { + return (TheStructure.Common.GeneralStateBufferSize); + } + inline void setDynamicStateBufferSizeModifyEnable(const bool value) { + TheStructure.Common.DynamicStateBufferSizeModifyEnable = value; + } + inline bool getDynamicStateBufferSizeModifyEnable(void) const { + return (TheStructure.Common.DynamicStateBufferSizeModifyEnable); + } + inline void setDynamicStateBufferSize(const uint32_t value) { + TheStructure.Common.DynamicStateBufferSize = value; + } + inline uint32_t getDynamicStateBufferSize(void) const { + return (TheStructure.Common.DynamicStateBufferSize); + } + inline void setIndirectObjectBufferSizeModifyEnable(const bool value) { + TheStructure.Common.IndirectObjectBufferSizeModifyEnable = value; + } + inline bool getIndirectObjectBufferSizeModifyEnable(void) const { + return (TheStructure.Common.IndirectObjectBufferSizeModifyEnable); + } + inline void setIndirectObjectBufferSize(const uint32_t value) { + TheStructure.Common.IndirectObjectBufferSize = value; + } + inline uint32_t getIndirectObjectBufferSize(void) const { + return (TheStructure.Common.IndirectObjectBufferSize); + } + inline void setInstructionBufferSizeModifyEnable(const bool value) { + TheStructure.Common.InstructionBufferSizeModifyEnable = value; + } + inline bool getInstructionBufferSizeModifyEnable(void) const { + return (TheStructure.Common.InstructionBufferSizeModifyEnable); + } + inline void setInstructionBufferSize(const uint32_t value) { + TheStructure.Common.InstructionBufferSize = value; + } + inline uint32_t getInstructionBufferSize(void) const { + return (TheStructure.Common.InstructionBufferSize); + } + inline void setBindlessSurfaceStateBaseAddressModifyEnable(const bool value) { + TheStructure.Common.BindlessSurfaceStateBaseAddressModifyEnable = value; + } + inline bool getBindlessSurfaceStateBaseAddressModifyEnable(void) const { + return (TheStructure.Common.BindlessSurfaceStateBaseAddressModifyEnable); + } + inline void setBindlessSurfaceStateMemoryObjectControlStateReserved(const uint64_t value) { + TheStructure.Common.BindlessSurfaceStateMemoryObjectControlState_Reserved = value; + } + inline uint64_t getBindlessSurfaceStateMemoryObjectControlStateReserved(void) const { + return (TheStructure.Common.BindlessSurfaceStateMemoryObjectControlState_Reserved); + } + inline void setBindlessSurfaceStateMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + TheStructure.Common.BindlessSurfaceStateMemoryObjectControlState_IndexToMocsTables = value >> 1; + } + inline uint64_t getBindlessSurfaceStateMemoryObjectControlStateIndexToMocsTables(void) const { + return (TheStructure.Common.BindlessSurfaceStateMemoryObjectControlState_IndexToMocsTables << 1); + } + typedef enum tagBINDLESSSURFACESTATEBASEADDRESS { + BINDLESSSURFACESTATEBASEADDRESS_BIT_SHIFT = 0xc, + BINDLESSSURFACESTATEBASEADDRESS_ALIGN_SIZE = 0x1000, + } BINDLESSSURFACESTATEBASEADDRESS; + inline void setBindlessSurfaceStateBaseAddress(const uint64_t value) { + TheStructure.Common.BindlessSurfaceStateBaseAddress = value >> BINDLESSSURFACESTATEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getBindlessSurfaceStateBaseAddress(void) const { + return (TheStructure.Common.BindlessSurfaceStateBaseAddress << BINDLESSSURFACESTATEBASEADDRESS_BIT_SHIFT); + } + inline void setBindlessSurfaceStateSize(const uint32_t value) { + TheStructure.Common.BindlessSurfaceStateSize = value; + } + inline uint32_t getBindlessSurfaceStateSize(void) const { + return (TheStructure.Common.BindlessSurfaceStateSize); + } + inline void setBindlessSamplerStateBaseAddressModifyEnable(const bool value) { + TheStructure.Common.BindlessSamplerStateBaseAddressModifyEnable = value; + } + inline bool getBindlessSamplerStateBaseAddressModifyEnable(void) const { + return (TheStructure.Common.BindlessSamplerStateBaseAddressModifyEnable); + } + inline void setBindlessSamplerStateMemoryObjectControlStateReserved(const uint64_t value) { + TheStructure.Common.BindlessSamplerStateMemoryObjectControlState_Reserved = value; + } + inline uint64_t getBindlessSamplerStateMemoryObjectControlStateReserved(void) const { + return (TheStructure.Common.BindlessSamplerStateMemoryObjectControlState_Reserved); + } + inline void setBindlessSamplerStateMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + TheStructure.Common.BindlessSamplerStateMemoryObjectControlState_IndexToMocsTables = value >> 1; + } + inline uint64_t getBindlessSamplerStateMemoryObjectControlStateIndexToMocsTables(void) const { + return (TheStructure.Common.BindlessSamplerStateMemoryObjectControlState_IndexToMocsTables << 1); + } + typedef enum tagBINDLESSSAMPLERSTATEBASEADDRESS { + BINDLESSSAMPLERSTATEBASEADDRESS_BIT_SHIFT = 0xc, + BINDLESSSAMPLERSTATEBASEADDRESS_ALIGN_SIZE = 0x1000, + } BINDLESSSAMPLERSTATEBASEADDRESS; + inline void setBindlessSamplerStateBaseAddress(const uint64_t value) { + TheStructure.Common.BindlessSamplerStateBaseAddress = value >> BINDLESSSAMPLERSTATEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getBindlessSamplerStateBaseAddress(void) const { + return (TheStructure.Common.BindlessSamplerStateBaseAddress << BINDLESSSAMPLERSTATEBASEADDRESS_BIT_SHIFT); + } + inline void setBindlessSamplerStateBufferSize(const uint32_t value) { + TheStructure.Common.BindlessSamplerStateBufferSize = value; + } + inline uint32_t getBindlessSamplerStateBufferSize(void) const { + return (TheStructure.Common.BindlessSamplerStateBufferSize); + } +} STATE_BASE_ADDRESS; +STATIC_ASSERT(88 == sizeof(STATE_BASE_ADDRESS)); + +typedef struct tagMI_REPORT_PERF_COUNT { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 5); + uint32_t Reserved_6 : BITFIELD_RANGE(6, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint64_t UseGlobalGtt : BITFIELD_RANGE(0, 0); + uint64_t Reserved_33 : BITFIELD_RANGE(1, 3); + uint64_t CoreModeEnable : BITFIELD_RANGE(4, 4); + uint64_t Reserved_37 : BITFIELD_RANGE(5, 5); + uint64_t MemoryAddress : BITFIELD_RANGE(6, 63); + uint32_t ReportId; + } Common; + uint32_t RawData[4]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x2, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_REPORT_PERF_COUNT = 0x28, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + typedef enum tagPATCH_CONSTANTS { + MEMORYADDRESS_BYTEOFFSET = 0x4, + MEMORYADDRESS_INDEX = 0x1, + } PATCH_CONSTANTS; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_REPORT_PERF_COUNT; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_REPORT_PERF_COUNT sInit(void) { + MI_REPORT_PERF_COUNT state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setUseGlobalGtt(const bool value) { + TheStructure.Common.UseGlobalGtt = value; + } + inline bool getUseGlobalGtt(void) const { + return (TheStructure.Common.UseGlobalGtt); + } + inline void setCoreModeEnable(const uint64_t value) { + TheStructure.Common.CoreModeEnable = value; + } + inline uint64_t getCoreModeEnable(void) const { + return (TheStructure.Common.CoreModeEnable); + } + typedef enum tagMEMORYADDRESS { + MEMORYADDRESS_BIT_SHIFT = 0x6, + MEMORYADDRESS_ALIGN_SIZE = 0x40, + } MEMORYADDRESS; + inline void setMemoryAddress(const uint64_t value) { + TheStructure.Common.MemoryAddress = value >> MEMORYADDRESS_BIT_SHIFT; + } + inline uint64_t getMemoryAddress(void) const { + return (TheStructure.Common.MemoryAddress << MEMORYADDRESS_BIT_SHIFT); + } + inline void setReportId(const uint32_t value) { + TheStructure.Common.ReportId = value; + } + inline uint32_t getReportId(void) const { + return (TheStructure.Common.ReportId); + } +} MI_REPORT_PERF_COUNT; +STATIC_ASSERT(16 == sizeof(MI_REPORT_PERF_COUNT)); + +typedef struct tagSTATE_COMPUTE_MODE { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t Reserved_32 : BITFIELD_RANGE(0, 2); + uint32_t ForceNonCoherent : BITFIELD_RANGE(3, 4); + uint32_t Reserved_37 : BITFIELD_RANGE(5, 9); + uint32_t BindingTableAlignment : BITFIELD_RANGE(10, 10); + uint32_t Reserved_43 : BITFIELD_RANGE(11, 11); + uint32_t CoherentAccessL1CacheDisable : BITFIELD_RANGE(12, 12); + uint32_t DisableL1InvalidateForNonL1CacheableWrites + : BITFIELD_RANGE(13, 13); + uint32_t Reserved_46 : BITFIELD_RANGE(14, 15); + uint32_t MaskBits : BITFIELD_RANGE(16, 31); + } Common; + uint32_t RawData[2]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x0, + } DWORD_LENGTH; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_STATE_COMPUTE_MODE = 0x5, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED = 0x1, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_COMMON = 0x0, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagFORCE_NON_COHERENT { + FORCE_NON_COHERENT_FORCE_DISABLED = 0x0, + FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT = 0x2, + } FORCE_NON_COHERENT; + typedef enum tagBINDING_TABLE_ALIGNMENT { + BINDING_TABLE_ALIGNMENT_LEGACY = 0x0, + } BINDING_TABLE_ALIGNMENT; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common._3DCommandSubOpcode = + _3D_COMMAND_SUB_OPCODE_STATE_COMPUTE_MODE; + TheStructure.Common._3DCommandOpcode = + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_COMMON; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + TheStructure.Common.ForceNonCoherent = FORCE_NON_COHERENT_FORCE_DISABLED; + TheStructure.Common.BindingTableAlignment = BINDING_TABLE_ALIGNMENT_LEGACY; + } + static tagSTATE_COMPUTE_MODE sInit(void) { + STATE_COMPUTE_MODE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 2); + return TheStructure.RawData[index]; + } + inline void setForceNonCoherent(const FORCE_NON_COHERENT value) { + TheStructure.Common.ForceNonCoherent = value; + } + inline FORCE_NON_COHERENT getForceNonCoherent(void) const { + return static_cast( + TheStructure.Common.ForceNonCoherent); + } + inline void setBindingTableAlignment(const BINDING_TABLE_ALIGNMENT value) { + TheStructure.Common.BindingTableAlignment = value; + } + inline BINDING_TABLE_ALIGNMENT getBindingTableAlignment(void) const { + return static_cast( + TheStructure.Common.BindingTableAlignment); + } + inline void setCoherentAccessL1CacheDisable(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x1000); + TheStructure.Common.CoherentAccessL1CacheDisable = value; + } + inline uint32_t getCoherentAccessL1CacheDisable(void) const { + return TheStructure.Common.CoherentAccessL1CacheDisable; + } + inline void + setDisableL1InvalidateForNonL1CacheableWrites(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x2000); + TheStructure.Common.DisableL1InvalidateForNonL1CacheableWrites = value; + } + inline uint32_t getDisableL1InvalidateForNonL1CacheableWrites(void) const { + return TheStructure.Common.DisableL1InvalidateForNonL1CacheableWrites; + } + inline void setMaskBits(const uint32_t value) { + DEBUG_BREAK_IF(value > 0xffff0000L); + TheStructure.Common.MaskBits = value; + } + inline uint32_t getMaskBits(void) const { + return TheStructure.Common.MaskBits; + } +} STATE_COMPUTE_MODE; +STATIC_ASSERT(8 == sizeof(STATE_COMPUTE_MODE)); + +struct MI_USER_INTERRUPT { + union tagTheStructure { + struct tagCommon { + uint32_t Reserved_0 : BITFIELD_RANGE(0, 22); + uint32_t MICommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + enum MI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_USER_INTERRUPT = 2, + }; + enum COMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0, + }; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.MICommandOpcode = MI_COMMAND_OPCODE_MI_USER_INTERRUPT; + } + static MI_USER_INTERRUPT sInit(void) { + MI_USER_INTERRUPT state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + return TheStructure.RawData[index]; + } +}; +STATIC_ASSERT(4 == sizeof(MI_USER_INTERRUPT)); + +typedef struct tagXY_SRC_COPY_BLT { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 10); + uint32_t DestTilingEnable : BITFIELD_RANGE(11, 11); + uint32_t Reserved_12 : BITFIELD_RANGE(12, 14); + uint32_t SrcTilingEnable : BITFIELD_RANGE(15, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 19); + uint32_t _32BppByteMask : BITFIELD_RANGE(20, 21); + uint32_t InstructionTarget_Opcode : BITFIELD_RANGE(22, 28); + uint32_t Client : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t DestinationPitch : BITFIELD_RANGE(0, 15); + uint32_t RasterOperation : BITFIELD_RANGE(16, 23); + uint32_t ColorDepth : BITFIELD_RANGE(24, 25); + uint32_t Reserved_58 : BITFIELD_RANGE(26, 29); + uint32_t ClippingEnabled : BITFIELD_RANGE(30, 30); + uint32_t Reserved_63 : BITFIELD_RANGE(31, 31); + // DWORD 2 + uint32_t DestinationX1Coordinate_Left : BITFIELD_RANGE(0, 15); + uint32_t DestinationY1Coordinate_Top : BITFIELD_RANGE(16, 31); + // DWORD 3 + uint32_t DestinationX2Coordinate_Right : BITFIELD_RANGE(0, 15); + uint32_t DestinationY2Coordinate_Bottom : BITFIELD_RANGE(16, 31); + // DWORD 4-5 + uint64_t DestinationBaseAddress; + // DWORD 6 + uint32_t SourceX1Coordinate_Left : BITFIELD_RANGE(0, 15); + uint32_t SourceY1Coordinate_Top : BITFIELD_RANGE(16, 31); + // DWORD 7 + uint32_t SourcePitch : BITFIELD_RANGE(0, 15); + uint32_t Reserved_240 : BITFIELD_RANGE(16, 31); + // DWORD 8-9 + uint64_t SourceBaseAddress; + } Common; + uint32_t RawData[10]; + } TheStructure; + typedef enum tagDEST_TILING_ENABLE { + DEST_TILING_ENABLE_TILING_DISABLED_LINEAR_BLIT = 0x0, + DEST_TILING_ENABLE_TILING_ENABLED = 0x1, + } DEST_TILING_ENABLE; + typedef enum tagSRC_TILING_ENABLE { + SRC_TILING_ENABLE_TILING_DISABLED_LINEAR = 0x0, + SRC_TILING_ENABLE_TILING_ENABLED = 0x1, + } SRC_TILING_ENABLE; + typedef enum tag_32BPP_BYTE_MASK { + _32BPP_BYTE_MASK_WRITE_RGB_CHANNEL = 0x1, + _32BPP_BYTE_MASK_WRITE_ALPHA_CHANNEL = 0x2, + } _32BPP_BYTE_MASK; + typedef enum tagCLIENT { + CLIENT_2D_PROCESSOR = 0x2, + } CLIENT; + typedef enum tagCOLOR_DEPTH { + COLOR_DEPTH_8_BIT_COLOR = 0x0, + COLOR_DEPTH_16_BIT_COLOR565 = 0x1, + COLOR_DEPTH_16_BIT_COLOR1555 = 0x2, + COLOR_DEPTH_32_BIT_COLOR = 0x3, + } COLOR_DEPTH; + typedef enum tagCLIPPING_ENABLED { + CLIPPING_ENABLED_DISABLED = 0x0, + CLIPPING_ENABLED_ENABLED = 0x1, + } CLIPPING_ENABLED; + typedef enum tagINSTRUCTIONTARGET_OPCODE { + INSTRUCTIONTARGET_OPCODE_OPCODE = 0x53, + } INSTRUCTIONTARGET_OPCODE; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x8, + } DWORD_LENGTH; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DestTilingEnable = DEST_TILING_ENABLE_TILING_DISABLED_LINEAR_BLIT; + TheStructure.Common.SrcTilingEnable = SRC_TILING_ENABLE_TILING_DISABLED_LINEAR; + TheStructure.Common.Client = CLIENT_2D_PROCESSOR; + TheStructure.Common.ColorDepth = COLOR_DEPTH_8_BIT_COLOR; + TheStructure.Common.ClippingEnabled = CLIPPING_ENABLED_DISABLED; + TheStructure.Common.InstructionTarget_Opcode = INSTRUCTIONTARGET_OPCODE_OPCODE; + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + } + static tagXY_SRC_COPY_BLT sInit(void) { + XY_SRC_COPY_BLT state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 10); + return TheStructure.RawData[index]; + } + inline void setDestTilingEnable(const DEST_TILING_ENABLE value) { + TheStructure.Common.DestTilingEnable = value; + } + inline DEST_TILING_ENABLE getDestTilingEnable(void) const { + return static_cast(TheStructure.Common.DestTilingEnable); + } + inline void setSrcTilingEnable(const SRC_TILING_ENABLE value) { + TheStructure.Common.SrcTilingEnable = value; + } + inline SRC_TILING_ENABLE getSrcTilingEnable(void) const { + return static_cast(TheStructure.Common.SrcTilingEnable); + } + inline void set32BppByteMask(const _32BPP_BYTE_MASK value) { + TheStructure.Common._32BppByteMask = value; + } + inline _32BPP_BYTE_MASK get32BppByteMask(void) const { + return static_cast<_32BPP_BYTE_MASK>(TheStructure.Common._32BppByteMask); + } + inline void setInstructionTargetOpcode(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x1fc00000); + TheStructure.Common.InstructionTarget_Opcode = value; + } + inline uint32_t getInstructionTargetOpcode(void) const { + return TheStructure.Common.InstructionTarget_Opcode; + } + inline void setClient(const CLIENT value) { + TheStructure.Common.Client = value; + } + inline CLIENT getClient(void) const { + return static_cast(TheStructure.Common.Client); + } + inline void setDestinationPitch(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff); + TheStructure.Common.DestinationPitch = value; + } + inline uint32_t getDestinationPitch(void) const { + return TheStructure.Common.DestinationPitch; + } + inline void setRasterOperation(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xff0000); + TheStructure.Common.RasterOperation = value; + } + inline uint32_t getRasterOperation(void) const { + return TheStructure.Common.RasterOperation; + } + inline void setColorDepth(const COLOR_DEPTH value) { + TheStructure.Common.ColorDepth = value; + } + inline COLOR_DEPTH getColorDepth(void) const { + return static_cast(TheStructure.Common.ColorDepth); + } + inline void setClippingEnabled(const CLIPPING_ENABLED value) { + TheStructure.Common.ClippingEnabled = value; + } + inline CLIPPING_ENABLED getClippingEnabled(void) const { + return static_cast(TheStructure.Common.ClippingEnabled); + } + inline void setDestinationX1CoordinateLeft(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff); + TheStructure.Common.DestinationX1Coordinate_Left = value; + } + inline uint32_t getDestinationX1CoordinateLeft(void) const { + return TheStructure.Common.DestinationX1Coordinate_Left; + } + inline void setDestinationY1CoordinateTop(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff0000); + TheStructure.Common.DestinationY1Coordinate_Top = value; + } + inline uint32_t getDestinationY1CoordinateTop(void) const { + return TheStructure.Common.DestinationY1Coordinate_Top; + } + inline void setDestinationX2CoordinateRight(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff); + TheStructure.Common.DestinationX2Coordinate_Right = value; + } + inline uint32_t getDestinationX2CoordinateRight(void) const { + return TheStructure.Common.DestinationX2Coordinate_Right; + } + inline void setDestinationY2CoordinateBottom(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff0000); + TheStructure.Common.DestinationY2Coordinate_Bottom = value; + } + inline uint32_t getDestinationY2CoordinateBottom(void) const { + return TheStructure.Common.DestinationY2Coordinate_Bottom; + } + inline void setDestinationBaseAddress(const uint64_t value) { + TheStructure.Common.DestinationBaseAddress = value; + } + inline uint64_t getDestinationBaseAddress(void) const { + return TheStructure.Common.DestinationBaseAddress; + } + inline void setSourceX1CoordinateLeft(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff); + TheStructure.Common.SourceX1Coordinate_Left = value; + } + inline uint32_t getSourceX1CoordinateLeft(void) const { + return TheStructure.Common.SourceX1Coordinate_Left; + } + inline void setSourceY1CoordinateTop(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff0000); + TheStructure.Common.SourceY1Coordinate_Top = value; + } + inline uint32_t getSourceY1CoordinateTop(void) const { + return TheStructure.Common.SourceY1Coordinate_Top; + } + inline void setSourcePitch(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff); + TheStructure.Common.SourcePitch = value; + } + inline uint32_t getSourcePitch(void) const { + return TheStructure.Common.SourcePitch; + } + inline void setSourceBaseAddress(const uint64_t value) { + TheStructure.Common.SourceBaseAddress = value; + } + inline uint64_t getSourceBaseAddress(void) const { + return TheStructure.Common.SourceBaseAddress; + } +} XY_SRC_COPY_BLT; +STATIC_ASSERT(40 == sizeof(XY_SRC_COPY_BLT)); + +struct MI_FLUSH_DW { + union tagData { + struct tagCommon { + /// DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 5); + uint32_t Reserved_6 : BITFIELD_RANGE(6, 7); + uint32_t NotifyEnable : BITFIELD_RANGE(8, 8); + uint32_t FlushLlc : BITFIELD_RANGE(9, 9); + uint32_t Reserved_10 : BITFIELD_RANGE(10, 13); + uint32_t PostSyncOperation : BITFIELD_RANGE(14, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 17); + uint32_t TlbInvalidate : BITFIELD_RANGE(18, 18); + uint32_t Reserved_19 : BITFIELD_RANGE(19, 20); + uint32_t StoreDataIndex : BITFIELD_RANGE(21, 21); + uint32_t Reserved_22 : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + + /// DWORD 1..2 + uint64_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint64_t DestinationAddress : BITFIELD_RANGE(2, 47); + uint64_t Reserved_80 : BITFIELD_RANGE(48, 63); + + /// DWORD 3..4 + uint64_t ImmediateData; + + } Common; + uint32_t RawData[5]; + } TheStructure; + + enum DWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 3, + }; + + enum POST_SYNC_OPERATION { + POST_SYNC_OPERATION_NO_WRITE = 0, + POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA_QWORD = 1, + POST_SYNC_OPERATION_WRITE_TIMESTAMP_REGISTER = 3, + }; + + enum MI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_FLUSH_DW = 38, + }; + + enum COMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0, + }; + + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH::DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE::MI_COMMAND_OPCODE_MI_FLUSH_DW; + } + + static MI_FLUSH_DW sInit(void) { + MI_FLUSH_DW state; + state.init(); + return state; + } + + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index < 5); + return TheStructure.RawData[index]; + } + + inline void setNotifyEnable(const uint32_t value) { + TheStructure.Common.NotifyEnable = value; + } + + inline uint32_t getNotifyEnable(void) const { + return (TheStructure.Common.NotifyEnable); + } + + inline void setFlushLlc(const uint32_t value) { + TheStructure.Common.FlushLlc = value; + } + + inline uint32_t getFlushLlc(void) const { + return (TheStructure.Common.FlushLlc); + } + + inline void setPostSyncOperation(const POST_SYNC_OPERATION value) { + TheStructure.Common.PostSyncOperation = value; + } + + inline POST_SYNC_OPERATION getPostSyncOperation(void) const { + return static_cast(TheStructure.Common.PostSyncOperation); + } + + inline void setTlbInvalidate(const uint32_t value) { + TheStructure.Common.TlbInvalidate = value; + } + + inline uint32_t getTlbInvalidate(void) const { + return (TheStructure.Common.TlbInvalidate); + } + + inline void setStoreDataIndex(const uint32_t value) { + TheStructure.Common.StoreDataIndex = value; + } + + inline uint32_t getStoreDataIndex(void) const { + return (TheStructure.Common.StoreDataIndex); + } + + typedef enum tagDESTINATIONADDRESS { + DESTINATIONADDRESS_BIT_SHIFT = 2, + DESTINATIONADDRESS_ALIGN_SIZE = 4, + } DESTINATIONADDRESS; + + inline void setDestinationAddress(const uint64_t value) { + TheStructure.Common.DestinationAddress = value >> DESTINATIONADDRESS_BIT_SHIFT; + } + + inline uint64_t getDestinationAddress(void) const { + return (TheStructure.Common.DestinationAddress << DESTINATIONADDRESS_BIT_SHIFT); + } + + inline void setImmediateData(const uint64_t value) { + TheStructure.Common.ImmediateData = value; + } + + inline uint64_t getImmediateData(void) const { + return (TheStructure.Common.ImmediateData); + } +}; +STATIC_ASSERT(20 == sizeof(MI_FLUSH_DW)); +#pragma pack() diff --git a/core/gen12lp/hw_cmds_generated_patched.inl b/core/gen12lp/hw_cmds_generated_patched.inl new file mode 100644 index 0000000000..f81ba66687 --- /dev/null +++ b/core/gen12lp/hw_cmds_generated_patched.inl @@ -0,0 +1,1017 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma pack(1) +typedef struct tagMEDIA_SURFACE_STATE { + union tagTheStructure { + struct tagCommon { + uint32_t Reserved_0 : BITFIELD_RANGE(0, 29); + uint32_t Rotation : BITFIELD_RANGE(30, 31); + uint32_t Cr_VCb_UPixelOffsetVDirection : BITFIELD_RANGE(0, 1); + uint32_t PictureStructure : BITFIELD_RANGE(2, 3); + uint32_t Width : BITFIELD_RANGE(4, 17); + uint32_t Height : BITFIELD_RANGE(18, 31); + uint32_t TileMode : BITFIELD_RANGE(0, 1); + uint32_t HalfPitchForChroma : BITFIELD_RANGE(2, 2); + uint32_t SurfacePitch : BITFIELD_RANGE(3, 20); + uint32_t AddressControl : BITFIELD_RANGE(21, 21); + uint32_t MemoryCompressionEnable : BITFIELD_RANGE(22, 22); + uint32_t MemoryCompressionMode : BITFIELD_RANGE(23, 23); + uint32_t Cr_VCb_UPixelOffsetVDirectionMsb : BITFIELD_RANGE(24, 24); + uint32_t Cr_VCb_UPixelOffsetUDirection : BITFIELD_RANGE(25, 25); + uint32_t InterleaveChroma : BITFIELD_RANGE(26, 26); + uint32_t SurfaceFormat : BITFIELD_RANGE(27, 31); + uint32_t YOffsetForU_Cb : BITFIELD_RANGE(0, 13); + uint32_t Reserved_110 : BITFIELD_RANGE(14, 15); + uint32_t XOffsetForU_Cb : BITFIELD_RANGE(16, 29); + uint32_t Reserved_126 : BITFIELD_RANGE(30, 31); + uint32_t Reserved_128; + uint32_t SurfaceMemoryObjectControlState_Reserved : BITFIELD_RANGE(0, 0); + uint32_t SurfaceMemoryObjectControlState_IndexToMocsTables : BITFIELD_RANGE(1, 6); + uint32_t Reserved_167 : BITFIELD_RANGE(7, 17); + uint32_t TiledResourceMode : BITFIELD_RANGE(18, 19); + uint32_t Depth : BITFIELD_RANGE(20, 23); + uint32_t Reserved_184 : BITFIELD_RANGE(24, 29); + uint32_t VerticalLineStrideOffset : BITFIELD_RANGE(30, 30); + uint32_t VerticalLineStride : BITFIELD_RANGE(31, 31); + uint32_t SurfaceBaseAddressLow; + uint32_t SurfaceBaseAddressHigh : BITFIELD_RANGE(0, 15); + uint32_t Reserved_240 : BITFIELD_RANGE(16, 31); + } Common; + struct tagSurfaceFormatIsNotOneOfPlanarFormats { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + } SurfaceFormatIsNotOneOfPlanarFormats; + struct tagSurfaceFormatIsOneOfPlanarFormats { + uint32_t Reserved_0 : BITFIELD_RANGE(0, 15); + uint32_t YOffset : BITFIELD_RANGE(16, 19); + uint32_t XOffset : BITFIELD_RANGE(20, 26); + uint32_t Reserved_27 : BITFIELD_RANGE(27, 31); + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t Reserved_128; + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + } SurfaceFormatIsOneOfPlanarFormats; + struct tag_SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0 { + uint32_t Reserved_0; + uint32_t Reserved_32; + uint32_t Reserved_64; + uint32_t Reserved_96; + uint32_t YOffsetForV_Cr : BITFIELD_RANGE(0, 14); + uint32_t Reserved_143 : BITFIELD_RANGE(15, 15); + uint32_t XOffsetForV_Cr : BITFIELD_RANGE(16, 29); + uint32_t Reserved_158 : BITFIELD_RANGE(30, 31); + uint32_t Reserved_160; + uint32_t Reserved_192; + uint32_t Reserved_224; + } _SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0; + uint32_t RawData[8]; + } TheStructure; + typedef enum tagROTATION { + ROTATION_NO_ROTATION_OR_0_DEGREE = 0x0, + ROTATION_90_DEGREE_ROTATION = 0x1, + ROTATION_180_DEGREE_ROTATION = 0x2, + ROTATION_270_DEGREE_ROTATION = 0x3, + } ROTATION; + typedef enum tagPICTURE_STRUCTURE { + PICTURE_STRUCTURE_FRAME_PICTURE = 0x0, + PICTURE_STRUCTURE_TOP_FIELD_PICTURE = 0x1, + PICTURE_STRUCTURE_BOTTOM_FIELD_PICTURE = 0x2, + PICTURE_STRUCTURE_INVALID_NOT_ALLOWED = 0x3, + } PICTURE_STRUCTURE; + typedef enum tagTILE_MODE { + TILE_MODE_TILEMODE_LINEAR = 0x0, + TILE_MODE_TILEMODE_XMAJOR = 0x2, + TILE_MODE_TILEMODE_YMAJOR = 0x3, + } TILE_MODE; + typedef enum tagADDRESS_CONTROL { + ADDRESS_CONTROL_CLAMP = 0x0, + ADDRESS_CONTROL_MIRROR = 0x1, + } ADDRESS_CONTROL; + typedef enum tagMEMORY_COMPRESSION_MODE { + MEMORY_COMPRESSION_MODE_HORIZONTAL_COMPRESSION_MODE = 0x0, + MEMORY_COMPRESSION_MODE_VERTICAL_COMPRESSION_MODE = 0x1, + } MEMORY_COMPRESSION_MODE; + typedef enum tagSURFACE_FORMAT { + SURFACE_FORMAT_YCRCB_NORMAL = 0x0, + SURFACE_FORMAT_YCRCB_SWAPUVY = 0x1, + SURFACE_FORMAT_YCRCB_SWAPUV = 0x2, + SURFACE_FORMAT_YCRCB_SWAPY = 0x3, + SURFACE_FORMAT_PLANAR_420_8 = 0x4, + SURFACE_FORMAT_Y8_UNORM_VA = 0x5, + SURFACE_FORMAT_Y16_SNORM = 0x6, + SURFACE_FORMAT_Y16_UNORM_VA = 0x7, + SURFACE_FORMAT_R10G10B10A2_UNORM = 0x8, + SURFACE_FORMAT_R8G8B8A8_UNORM = 0x9, + SURFACE_FORMAT_R8B8_UNORM_CRCB = 0xa, + SURFACE_FORMAT_R8_UNORM_CR_CB = 0xb, + SURFACE_FORMAT_Y8_UNORM = 0xc, + SURFACE_FORMAT_A8Y8U8V8_UNORM = 0xd, + SURFACE_FORMAT_B8G8R8A8_UNORM = 0xe, + SURFACE_FORMAT_R16G16B16A16 = 0xf, + SURFACE_FORMAT_Y1_UNORM = 0x10, + SURFACE_FORMAT_Y32_UNORM = 0x11, + SURFACE_FORMAT_PLANAR_422_8 = 0x12, + SURFACE_FORMAT_FM_STRBUF_Y1 = 0x13, + SURFACE_FORMAT_FM_STRBUF_Y8 = 0x14, + SURFACE_FORMAT_FM_STRBUF_Y16 = 0x15, + SURFACE_FORMAT_FM_STRBUF_Y32 = 0x16, + SURFACE_FORMAT_PLANAR_420_16 = 0x17, + SURFACE_FORMAT_R16B16_UNORM_CRCB = 0x18, + SURFACE_FORMAT_R16_UNORM_CR_CB = 0x19, + SURFACE_FORMAT_Y16_UNORM = 0x1a, + } SURFACE_FORMAT; + typedef enum tagSURFACE_MEMORY_OBJECT_CONTROL_STATE { + SURFACE_MEMORY_OBJECT_CONTROL_STATE_DEFAULTVAUEDESC = 0x0, + } SURFACE_MEMORY_OBJECT_CONTROL_STATE; + typedef enum tagTILED_RESOURCE_MODE { + TILED_RESOURCE_MODE_TRMODE_NONE = 0x0, + TILED_RESOURCE_MODE_TRMODE_TILEYF = 0x1, + TILED_RESOURCE_MODE_TRMODE_TILEYS = 0x2, + } TILED_RESOURCE_MODE; + typedef enum tagPATCH_CONSTANTS { + SURFACEBASEADDRESS_BYTEOFFSET = 0x18, + SURFACEBASEADDRESS_INDEX = 0x6, + SURFACEBASEADDRESSHIGH_BYTEOFFSET = 0x1c, + SURFACEBASEADDRESSHIGH_INDEX = 0x7, + } PATCH_CONSTANTS; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.Rotation = ROTATION_NO_ROTATION_OR_0_DEGREE; + TheStructure.Common.PictureStructure = PICTURE_STRUCTURE_FRAME_PICTURE; + TheStructure.Common.TileMode = TILE_MODE_TILEMODE_LINEAR; + TheStructure.Common.AddressControl = ADDRESS_CONTROL_CLAMP; + TheStructure.Common.MemoryCompressionMode = MEMORY_COMPRESSION_MODE_HORIZONTAL_COMPRESSION_MODE; + TheStructure.Common.SurfaceFormat = SURFACE_FORMAT_YCRCB_NORMAL; + TheStructure.Common.TiledResourceMode = TILED_RESOURCE_MODE_TRMODE_NONE; + } + static tagMEDIA_SURFACE_STATE sInit(void) { + MEDIA_SURFACE_STATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 8); + return TheStructure.RawData[index]; + } + inline void setRotation(const ROTATION value) { + TheStructure.Common.Rotation = value; + } + inline ROTATION getRotation(void) const { + return static_cast(TheStructure.Common.Rotation); + } + inline void setCrVCbUPixelOffsetVDirection(const uint32_t value) { + TheStructure.Common.Cr_VCb_UPixelOffsetVDirection = value; + } + inline uint32_t getCrVCbUPixelOffsetVDirection(void) const { + return (TheStructure.Common.Cr_VCb_UPixelOffsetVDirection); + } + inline void setPictureStructure(const PICTURE_STRUCTURE value) { + TheStructure.Common.PictureStructure = value; + } + inline PICTURE_STRUCTURE getPictureStructure(void) const { + return static_cast(TheStructure.Common.PictureStructure); + } + inline void setWidth(const uint32_t value) { + TheStructure.Common.Width = value - 1; + } + inline uint32_t getWidth(void) const { + return (TheStructure.Common.Width + 1); + } + inline void setHeight(const uint32_t value) { + TheStructure.Common.Height = value - 1; + } + inline uint32_t getHeight(void) const { + return (TheStructure.Common.Height + 1); + } + inline void setTileMode(const TILE_MODE value) { + TheStructure.Common.TileMode = value; + } + inline TILE_MODE getTileMode(void) const { + return static_cast(TheStructure.Common.TileMode); + } + inline void setHalfPitchForChroma(const bool value) { + TheStructure.Common.HalfPitchForChroma = value; + } + inline bool getHalfPitchForChroma(void) const { + return (TheStructure.Common.HalfPitchForChroma); + } + inline void setSurfacePitch(const uint32_t value) { + TheStructure.Common.SurfacePitch = value - 1; + } + inline uint32_t getSurfacePitch(void) const { + return (TheStructure.Common.SurfacePitch + 1); + } + inline void setAddressControl(const ADDRESS_CONTROL value) { + TheStructure.Common.AddressControl = value; + } + inline ADDRESS_CONTROL getAddressControl(void) const { + return static_cast(TheStructure.Common.AddressControl); + } + inline void setMemoryCompressionEnable(const bool value) { + TheStructure.Common.MemoryCompressionEnable = value; + } + inline bool getMemoryCompressionEnable(void) const { + return (TheStructure.Common.MemoryCompressionEnable); + } + inline void setMemoryCompressionMode(const MEMORY_COMPRESSION_MODE value) { + TheStructure.Common.MemoryCompressionMode = value; + } + inline MEMORY_COMPRESSION_MODE getMemoryCompressionMode(void) const { + return static_cast(TheStructure.Common.MemoryCompressionMode); + } + inline void setCrVCbUPixelOffsetVDirectionMsb(const uint32_t value) { + TheStructure.Common.Cr_VCb_UPixelOffsetVDirectionMsb = value; + } + inline uint32_t getCrVCbUPixelOffsetVDirectionMsb(void) const { + return (TheStructure.Common.Cr_VCb_UPixelOffsetVDirectionMsb); + } + inline void setCrVCbUPixelOffsetUDirection(const uint32_t value) { + TheStructure.Common.Cr_VCb_UPixelOffsetUDirection = value; + } + inline uint32_t getCrVCbUPixelOffsetUDirection(void) const { + return (TheStructure.Common.Cr_VCb_UPixelOffsetUDirection); + } + inline void setInterleaveChroma(const bool value) { + TheStructure.Common.InterleaveChroma = value; + } + inline bool getInterleaveChroma(void) const { + return (TheStructure.Common.InterleaveChroma); + } + inline void setSurfaceFormat(const SURFACE_FORMAT value) { + TheStructure.Common.SurfaceFormat = value; + } + inline SURFACE_FORMAT getSurfaceFormat(void) const { + return static_cast(TheStructure.Common.SurfaceFormat); + } + inline void setYOffsetForUCb(const uint32_t value) { + TheStructure.Common.YOffsetForU_Cb = value; + } + inline uint32_t getYOffsetForUCb(void) const { + return (TheStructure.Common.YOffsetForU_Cb); + } + inline void setXOffsetForUCb(const uint32_t value) { + TheStructure.Common.XOffsetForU_Cb = value; + } + inline uint32_t getXOffsetForUCb(void) const { + return (TheStructure.Common.XOffsetForU_Cb); + } + inline void setSurfaceMemoryObjectControlStateReserved(const uint32_t value) { + TheStructure.Common.SurfaceMemoryObjectControlState_Reserved = value; + } + inline uint32_t getSurfaceMemoryObjectControlStateReserved(void) const { + return (TheStructure.Common.SurfaceMemoryObjectControlState_Reserved); + } + inline void setSurfaceMemoryObjectControlStateIndexToMocsTables(const uint32_t value) { + TheStructure.Common.SurfaceMemoryObjectControlState_IndexToMocsTables = value >> 1; + } + inline uint32_t getSurfaceMemoryObjectControlStateIndexToMocsTables(void) const { + return (TheStructure.Common.SurfaceMemoryObjectControlState_IndexToMocsTables << 1); + } + inline void setTiledResourceMode(const TILED_RESOURCE_MODE value) { + TheStructure.Common.TiledResourceMode = value; + } + inline TILED_RESOURCE_MODE getTiledResourceMode(void) const { + return static_cast(TheStructure.Common.TiledResourceMode); + } + inline void setDepth(const uint32_t value) { + TheStructure.Common.Depth = value; + } + inline uint32_t getDepth(void) const { + return (TheStructure.Common.Depth); + } + inline void setVerticalLineStrideOffset(const uint32_t value) { + TheStructure.Common.VerticalLineStrideOffset = value; + } + inline uint32_t getVerticalLineStrideOffset(void) const { + return (TheStructure.Common.VerticalLineStrideOffset); + } + inline void setVerticalLineStride(const uint32_t value) { + TheStructure.Common.VerticalLineStride = value; + } + inline uint32_t getVerticalLineStride(void) const { + return (TheStructure.Common.VerticalLineStride); + } + inline void setSurfaceBaseAddress(const uint64_t value) { + TheStructure.Common.SurfaceBaseAddressLow = static_cast(value & 0xffffffff); + TheStructure.Common.SurfaceBaseAddressHigh = (value >> 32) & 0xffffffff; + } + inline uint64_t getSurfaceBaseAddress(void) const { + return (TheStructure.Common.SurfaceBaseAddressLow | + static_cast(TheStructure.Common.SurfaceBaseAddressHigh) << 32); + } + inline void setSurfaceBaseAddressHigh(const uint32_t value) { + TheStructure.Common.SurfaceBaseAddressHigh = value; + } + inline uint32_t getSurfaceBaseAddressHigh(void) const { + return (TheStructure.Common.SurfaceBaseAddressHigh); + } + typedef enum tagYOFFSET { + YOFFSET_BIT_SHIFT = 0x2, + YOFFSET_ALIGN_SIZE = 0x4, + } YOFFSET; + inline void setYOffset(const uint32_t value) { + TheStructure.SurfaceFormatIsOneOfPlanarFormats.YOffset = value >> YOFFSET_BIT_SHIFT; + } + inline uint32_t getYOffset(void) const { + return (TheStructure.SurfaceFormatIsOneOfPlanarFormats.YOffset << YOFFSET_BIT_SHIFT); + } + typedef enum tagXOFFSET { + XOFFSET_BIT_SHIFT = 0x2, + XOFFSET_ALIGN_SIZE = 0x4, + } XOFFSET; + inline void setXOffset(const uint32_t value) { + TheStructure.SurfaceFormatIsOneOfPlanarFormats.XOffset = value >> XOFFSET_BIT_SHIFT; + } + inline uint32_t getXOffset(void) const { + return (TheStructure.SurfaceFormatIsOneOfPlanarFormats.XOffset << XOFFSET_BIT_SHIFT); + } + inline void setYOffsetForVCr(const uint32_t value) { + TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.YOffsetForV_Cr = value; + } + inline uint32_t getYOffsetForVCr(void) const { + return (TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.YOffsetForV_Cr); + } + inline void setXOffsetForVCr(const uint32_t value) { + TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.XOffsetForV_Cr = value; + } + inline uint32_t getXOffsetForVCr(void) const { + return (TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.XOffsetForV_Cr); + } +} MEDIA_SURFACE_STATE; +STATIC_ASSERT(32 == sizeof(MEDIA_SURFACE_STATE)); +typedef struct tagMI_MATH { + union _DW0 { + struct _BitField { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved : BITFIELD_RANGE(8, 22); + uint32_t InstructionOpcode : BITFIELD_RANGE(23, 28); + uint32_t InstructionType : BITFIELD_RANGE(29, 31); + } BitField; + uint32_t Value; + } DW0; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_MATH = 0x1A, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; +} MI_MATH; +typedef struct tagMI_MATH_ALU_INST_INLINE { + union _DW0 { + struct _BitField { + uint32_t Operand2 : BITFIELD_RANGE(0, 9); + uint32_t Operand1 : BITFIELD_RANGE(10, 19); + uint32_t ALUOpcode : BITFIELD_RANGE(20, 31); + } BitField; + uint32_t Value; + } DW0; +} MI_MATH_ALU_INST_INLINE; +typedef struct tagPIPE_CONTROL { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 8); + uint32_t HdcFlushEnable : BITFIELD_RANGE(9, 9); + uint32_t Reserved_23 : BITFIELD_RANGE(10, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t DepthCacheFlushEnable : BITFIELD_RANGE(0, 0); + uint32_t StallAtPixelScoreboard : BITFIELD_RANGE(1, 1); + uint32_t StateCacheInvalidationEnable : BITFIELD_RANGE(2, 2); + uint32_t ConstantCacheInvalidationEnable : BITFIELD_RANGE(3, 3); + uint32_t VfCacheInvalidationEnable : BITFIELD_RANGE(4, 4); + uint32_t DcFlushEnable : BITFIELD_RANGE(5, 5); + uint32_t ProtectedMemoryApplicationId : BITFIELD_RANGE(6, 6); + uint32_t PipeControlFlushEnable : BITFIELD_RANGE(7, 7); + uint32_t NotifyEnable : BITFIELD_RANGE(8, 8); + uint32_t IndirectStatePointersDisable : BITFIELD_RANGE(9, 9); + uint32_t TextureCacheInvalidationEnable : BITFIELD_RANGE(10, 10); + uint32_t InstructionCacheInvalidateEnable : BITFIELD_RANGE(11, 11); + uint32_t RenderTargetCacheFlushEnable : BITFIELD_RANGE(12, 12); + uint32_t DepthStallEnable : BITFIELD_RANGE(13, 13); + uint32_t PostSyncOperation : BITFIELD_RANGE(14, 15); + uint32_t GenericMediaStateClear : BITFIELD_RANGE(16, 16); + uint32_t PsdSyncEnable : BITFIELD_RANGE(17, 17); + uint32_t TlbInvalidate : BITFIELD_RANGE(18, 18); + uint32_t GlobalSnapshotCountReset : BITFIELD_RANGE(19, 19); + uint32_t CommandStreamerStallEnable : BITFIELD_RANGE(20, 20); + uint32_t StoreDataIndex : BITFIELD_RANGE(21, 21); + uint32_t Reserved_54 : BITFIELD_RANGE(22, 22); + uint32_t LriPostSyncOperation : BITFIELD_RANGE(23, 23); + uint32_t DestinationAddressType : BITFIELD_RANGE(24, 24); + uint32_t Reserved_57 : BITFIELD_RANGE(25, 25); + uint32_t FlushLlc : BITFIELD_RANGE(26, 26); + uint32_t ProtectedMemoryDisable : BITFIELD_RANGE(27, 27); + uint32_t TileCacheFlushEnable : BITFIELD_RANGE(28, 28); + uint32_t Reserved_61 : BITFIELD_RANGE(29, 31); + uint32_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint32_t Address : BITFIELD_RANGE(2, 31); + uint32_t AddressHigh; + uint64_t ImmediateData; + } Common; + uint32_t RawData[6]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x4, + } DWORD_LENGTH; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_PIPE_CONTROL = 0x0, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_PIPE_CONTROL = 0x2, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_3D = 0x3, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagPOST_SYNC_OPERATION { + POST_SYNC_OPERATION_NO_WRITE = 0x0, + POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA = 0x1, + POST_SYNC_OPERATION_WRITE_PS_DEPTH_COUNT = 0x2, + POST_SYNC_OPERATION_WRITE_TIMESTAMP = 0x3, + } POST_SYNC_OPERATION; + typedef enum tagGLOBAL_SNAPSHOT_COUNT_RESET { + GLOBAL_SNAPSHOT_COUNT_RESET_DON_T_RESET = 0x0, + GLOBAL_SNAPSHOT_COUNT_RESET_RESET = 0x1, + } GLOBAL_SNAPSHOT_COUNT_RESET; + typedef enum tagLRI_POST_SYNC_OPERATION { + LRI_POST_SYNC_OPERATION_NO_LRI_OPERATION = 0x0, + LRI_POST_SYNC_OPERATION_MMIO_WRITE_IMMEDIATE_DATA = 0x1, + } LRI_POST_SYNC_OPERATION; + typedef enum tagDESTINATION_ADDRESS_TYPE { + DESTINATION_ADDRESS_TYPE_PPGTT = 0x0, + DESTINATION_ADDRESS_TYPE_GGTT = 0x1, + } DESTINATION_ADDRESS_TYPE; + typedef enum tagPATCH_CONSTANTS { + ADDRESS_BYTEOFFSET = 0x8, + ADDRESS_INDEX = 0x2, + ADDRESSHIGH_BYTEOFFSET = 0xc, + ADDRESSHIGH_INDEX = 0x3, + } PATCH_CONSTANTS; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_PIPE_CONTROL; + TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_PIPE_CONTROL; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_3D; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + TheStructure.Common.PostSyncOperation = POST_SYNC_OPERATION_NO_WRITE; + TheStructure.Common.GlobalSnapshotCountReset = GLOBAL_SNAPSHOT_COUNT_RESET_DON_T_RESET; + TheStructure.Common.LriPostSyncOperation = LRI_POST_SYNC_OPERATION_NO_LRI_OPERATION; + TheStructure.Common.DestinationAddressType = DESTINATION_ADDRESS_TYPE_PPGTT; + + TheStructure.Common.CommandStreamerStallEnable = 1u; + } + static tagPIPE_CONTROL sInit(void) { + PIPE_CONTROL state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 6); + return TheStructure.RawData[index]; + } + inline void setDepthCacheFlushEnable(const bool value) { + TheStructure.Common.DepthCacheFlushEnable = value; + } + inline bool getDepthCacheFlushEnable(void) const { + return (TheStructure.Common.DepthCacheFlushEnable); + } + inline void setStallAtPixelScoreboard(const bool value) { + TheStructure.Common.StallAtPixelScoreboard = value; + } + inline bool getStallAtPixelScoreboard(void) const { + return (TheStructure.Common.StallAtPixelScoreboard); + } + inline void setStateCacheInvalidationEnable(const bool value) { + TheStructure.Common.StateCacheInvalidationEnable = value; + } + inline bool getStateCacheInvalidationEnable(void) const { + return (TheStructure.Common.StateCacheInvalidationEnable); + } + inline void setConstantCacheInvalidationEnable(const bool value) { + TheStructure.Common.ConstantCacheInvalidationEnable = value; + } + inline bool getConstantCacheInvalidationEnable(void) const { + return (TheStructure.Common.ConstantCacheInvalidationEnable); + } + inline void setVfCacheInvalidationEnable(const bool value) { + TheStructure.Common.VfCacheInvalidationEnable = value; + } + inline bool getVfCacheInvalidationEnable(void) const { + return (TheStructure.Common.VfCacheInvalidationEnable); + } + inline void setDcFlushEnable(const bool value) { + TheStructure.Common.DcFlushEnable = value; + } + inline bool getDcFlushEnable(void) const { + return (TheStructure.Common.DcFlushEnable); + } + inline void setHdcFlushEnable(const bool value) { + TheStructure.Common.HdcFlushEnable = value; + } + inline bool getHdcFlushEnable(void) const { + return (TheStructure.Common.HdcFlushEnable); + } + inline void setProtectedMemoryApplicationId(const uint32_t value) { + TheStructure.Common.ProtectedMemoryApplicationId = value; + } + inline uint32_t getProtectedMemoryApplicationId(void) const { + return (TheStructure.Common.ProtectedMemoryApplicationId); + } + inline void setPipeControlFlushEnable(const bool value) { + TheStructure.Common.PipeControlFlushEnable = value; + } + inline bool getPipeControlFlushEnable(void) const { + return (TheStructure.Common.PipeControlFlushEnable); + } + inline void setNotifyEnable(const bool value) { + TheStructure.Common.NotifyEnable = value; + } + inline bool getNotifyEnable(void) const { + return (TheStructure.Common.NotifyEnable); + } + inline void setIndirectStatePointersDisable(const bool value) { + TheStructure.Common.IndirectStatePointersDisable = value; + } + inline bool getIndirectStatePointersDisable(void) const { + return (TheStructure.Common.IndirectStatePointersDisable); + } + inline void setTextureCacheInvalidationEnable(const bool value) { + TheStructure.Common.TextureCacheInvalidationEnable = value; + } + inline bool getTextureCacheInvalidationEnable(void) const { + return (TheStructure.Common.TextureCacheInvalidationEnable); + } + inline void setInstructionCacheInvalidateEnable(const bool value) { + TheStructure.Common.InstructionCacheInvalidateEnable = value; + } + inline bool getInstructionCacheInvalidateEnable(void) const { + return (TheStructure.Common.InstructionCacheInvalidateEnable); + } + inline void setRenderTargetCacheFlushEnable(const bool value) { + TheStructure.Common.RenderTargetCacheFlushEnable = value; + } + inline bool getRenderTargetCacheFlushEnable(void) const { + return (TheStructure.Common.RenderTargetCacheFlushEnable); + } + inline void setDepthStallEnable(const bool value) { + TheStructure.Common.DepthStallEnable = value; + } + inline bool getDepthStallEnable(void) const { + return (TheStructure.Common.DepthStallEnable); + } + inline void setPostSyncOperation(const POST_SYNC_OPERATION value) { + TheStructure.Common.PostSyncOperation = value; + } + inline POST_SYNC_OPERATION getPostSyncOperation(void) const { + return static_cast(TheStructure.Common.PostSyncOperation); + } + inline void setGenericMediaStateClear(const bool value) { + TheStructure.Common.GenericMediaStateClear = value; + } + inline bool getGenericMediaStateClear(void) const { + return (TheStructure.Common.GenericMediaStateClear); + } + inline void setPsdSyncEnable(const bool value) { + TheStructure.Common.PsdSyncEnable = value; + } + inline bool getPsdSyncEnable(void) const { + return (TheStructure.Common.PsdSyncEnable); + } + inline void setTlbInvalidate(const uint32_t value) { + TheStructure.Common.TlbInvalidate = value; + } + inline uint32_t getTlbInvalidate(void) const { + return (TheStructure.Common.TlbInvalidate); + } + inline void setGlobalSnapshotCountReset(const GLOBAL_SNAPSHOT_COUNT_RESET value) { + TheStructure.Common.GlobalSnapshotCountReset = value; + } + inline GLOBAL_SNAPSHOT_COUNT_RESET getGlobalSnapshotCountReset(void) const { + return static_cast(TheStructure.Common.GlobalSnapshotCountReset); + } + inline void setCommandStreamerStallEnable(const uint32_t value) { + TheStructure.Common.CommandStreamerStallEnable = value; + } + inline uint32_t getCommandStreamerStallEnable(void) const { + return (TheStructure.Common.CommandStreamerStallEnable); + } + inline void setStoreDataIndex(const uint32_t value) { + TheStructure.Common.StoreDataIndex = value; + } + inline uint32_t getStoreDataIndex(void) const { + return (TheStructure.Common.StoreDataIndex); + } + inline void setLriPostSyncOperation(const LRI_POST_SYNC_OPERATION value) { + TheStructure.Common.LriPostSyncOperation = value; + } + inline LRI_POST_SYNC_OPERATION getLriPostSyncOperation(void) const { + return static_cast(TheStructure.Common.LriPostSyncOperation); + } + inline void setDestinationAddressType(const DESTINATION_ADDRESS_TYPE value) { + TheStructure.Common.DestinationAddressType = value; + } + inline DESTINATION_ADDRESS_TYPE getDestinationAddressType(void) const { + return static_cast(TheStructure.Common.DestinationAddressType); + } + inline void setFlushLlc(const bool value) { + TheStructure.Common.FlushLlc = value; + } + inline bool getFlushLlc(void) const { + return (TheStructure.Common.FlushLlc); + } + inline void setProtectedMemoryDisable(const uint32_t value) { + TheStructure.Common.ProtectedMemoryDisable = value; + } + inline uint32_t getProtectedMemoryDisable(void) const { + return (TheStructure.Common.ProtectedMemoryDisable); + } + inline void setTileCacheFlushEnable(const uint32_t value) { + TheStructure.Common.TileCacheFlushEnable = value; + } + inline uint32_t getTileCacheFlushEnable(void) const { + return (TheStructure.Common.TileCacheFlushEnable); + } + typedef enum tagADDRESS { + ADDRESS_BIT_SHIFT = 0x2, + ADDRESS_ALIGN_SIZE = 0x4, + } ADDRESS; + inline void setAddress(const uint32_t value) { + TheStructure.Common.Address = value >> ADDRESS_BIT_SHIFT; + } + inline uint32_t getAddress(void) const { + return (TheStructure.Common.Address << ADDRESS_BIT_SHIFT); + } + inline void setAddressHigh(const uint32_t value) { + TheStructure.Common.AddressHigh = value; + } + inline uint32_t getAddressHigh(void) const { + return (TheStructure.Common.AddressHigh); + } + inline void setImmediateData(const uint64_t value) { + TheStructure.Common.ImmediateData = value; + } + inline uint64_t getImmediateData(void) const { + return (TheStructure.Common.ImmediateData); + } +} PIPE_CONTROL; +STATIC_ASSERT(24 == sizeof(PIPE_CONTROL)); +typedef struct tagMI_SEMAPHORE_WAIT { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 11); + uint32_t CompareOperation : BITFIELD_RANGE(12, 14); + uint32_t WaitMode : BITFIELD_RANGE(15, 15); + uint32_t RegisterPollMode : BITFIELD_RANGE(16, 16); + uint32_t Reserved_17 : BITFIELD_RANGE(17, 21); + uint32_t MemoryType : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint32_t SemaphoreDataDword; + uint64_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint64_t SemaphoreAddress : BITFIELD_RANGE(2, 63); + uint32_t Reserved_192 : BITFIELD_RANGE(0, 4); + uint32_t WaitTokenNumber : BITFIELD_RANGE(5, 9); + uint32_t Reserved_202 : BITFIELD_RANGE(10, 31); + } Common; + uint32_t RawData[5]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x3, + } DWORD_LENGTH; + typedef enum tagCOMPARE_OPERATION { + COMPARE_OPERATION_SAD_GREATER_THAN_SDD = 0x0, + COMPARE_OPERATION_SAD_GREATER_THAN_OR_EQUAL_SDD = 0x1, + COMPARE_OPERATION_SAD_LESS_THAN_SDD = 0x2, + COMPARE_OPERATION_SAD_LESS_THAN_OR_EQUAL_SDD = 0x3, + COMPARE_OPERATION_SAD_EQUAL_SDD = 0x4, + COMPARE_OPERATION_SAD_NOT_EQUAL_SDD = 0x5, + } COMPARE_OPERATION; + typedef enum tagWAIT_MODE { + WAIT_MODE_SIGNAL_MODE = 0x0, + WAIT_MODE_POLLING_MODE = 0x1, + } WAIT_MODE; + typedef enum tagREGISTER_POLL_MODE { + REGISTER_POLL_MODE_MEMORY_POLL = 0x0, + REGISTER_POLL_MODE_REGISTER_POLL = 0x1, + } REGISTER_POLL_MODE; + typedef enum tagMEMORY_TYPE { + MEMORY_TYPE_PER_PROCESS_GRAPHICS_ADDRESS = 0x0, + MEMORY_TYPE_GLOBAL_GRAPHICS_ADDRESS = 0x1, + } MEMORY_TYPE; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_SEMAPHORE_WAIT = 0x1c, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.CompareOperation = + COMPARE_OPERATION_SAD_GREATER_THAN_SDD; + TheStructure.Common.WaitMode = WAIT_MODE_SIGNAL_MODE; + TheStructure.Common.RegisterPollMode = REGISTER_POLL_MODE_MEMORY_POLL; + TheStructure.Common.MemoryType = MEMORY_TYPE_PER_PROCESS_GRAPHICS_ADDRESS; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_SEMAPHORE_WAIT; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_SEMAPHORE_WAIT sInit(void) { + MI_SEMAPHORE_WAIT state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 6); + return TheStructure.RawData[index]; + } + inline void setCompareOperation(const COMPARE_OPERATION value) { + TheStructure.Common.CompareOperation = value; + } + inline COMPARE_OPERATION getCompareOperation(void) const { + return static_cast(TheStructure.Common.CompareOperation); + } + inline void setWaitMode(const WAIT_MODE value) { + TheStructure.Common.WaitMode = value; + } + inline WAIT_MODE getWaitMode(void) const { + return static_cast(TheStructure.Common.WaitMode); + } + inline void setRegisterPollMode(const REGISTER_POLL_MODE value) { + TheStructure.Common.RegisterPollMode = value; + } + inline REGISTER_POLL_MODE getRegisterPollMode(void) const { + return static_cast( + TheStructure.Common.RegisterPollMode); + } + inline void setMemoryType(const MEMORY_TYPE value) { + TheStructure.Common.MemoryType = value; + } + inline MEMORY_TYPE getMemoryType(void) const { + return static_cast(TheStructure.Common.MemoryType); + } + inline void setSemaphoreDataDword(const uint32_t value) { + TheStructure.Common.SemaphoreDataDword = value; + } + inline uint32_t getSemaphoreDataDword(void) const { + return TheStructure.Common.SemaphoreDataDword; + } + typedef enum tagSEMAPHOREADDRESS { + SEMAPHOREADDRESS_BIT_SHIFT = 0x2, + SEMAPHOREADDRESS_ALIGN_SIZE = 0x4, + } SEMAPHOREADDRESS; + inline void setSemaphoreGraphicsAddress(const uint64_t value) { + TheStructure.Common.SemaphoreAddress = value >> SEMAPHOREADDRESS_BIT_SHIFT; + } + inline uint64_t getSemaphoreGraphicsAddress(void) const { + return TheStructure.Common.SemaphoreAddress << SEMAPHOREADDRESS_BIT_SHIFT; + } + inline void setWaitTokenNumber(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x3e0); + TheStructure.Common.WaitTokenNumber = value; + } + inline uint32_t getWaitTokenNumber(void) const { + return TheStructure.Common.WaitTokenNumber; + } +} MI_SEMAPHORE_WAIT; +STATIC_ASSERT(20 == sizeof(MI_SEMAPHORE_WAIT)); + +typedef struct tagMI_STORE_DATA_IMM { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 9); + uint32_t Reserved_10 : BITFIELD_RANGE(10, 20); + uint32_t StoreQword : BITFIELD_RANGE(21, 21); + uint32_t UseGlobalGtt : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint64_t CoreModeEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_33 : BITFIELD_RANGE(1, 1); + uint64_t Address : BITFIELD_RANGE(2, 47); + uint64_t AddressReserved_80 : BITFIELD_RANGE(48, 63); + uint32_t DataDword0; + uint32_t DataDword1; + } Common; + uint32_t RawData[5]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_STORE_DWORD = 0x2, + DWORD_LENGTH_STORE_QWORD = 0x3, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_STORE_DATA_IMM = 0x20, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_STORE_DWORD; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_STORE_DATA_IMM; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_STORE_DATA_IMM sInit(void) { + MI_STORE_DATA_IMM state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 5); + return TheStructure.RawData[index]; + } + inline void setDwordLength(const DWORD_LENGTH value) { + TheStructure.Common.DwordLength = value; + } + inline DWORD_LENGTH getDwordLength(void) const { + return static_cast(TheStructure.Common.DwordLength); + } + inline void setStoreQword(const bool value) { + TheStructure.Common.StoreQword = value; + } + inline bool getStoreQword(void) const { + return TheStructure.Common.StoreQword; + } + inline void setUseGlobalGtt(const bool value) { + TheStructure.Common.UseGlobalGtt = value; + } + inline bool getUseGlobalGtt(void) const { + return TheStructure.Common.UseGlobalGtt; + } + inline void setCoreModeEnable(const uint64_t value) { + TheStructure.Common.CoreModeEnable = value; + } + inline uint64_t getCoreModeEnable(void) const { + return TheStructure.Common.CoreModeEnable; + } + typedef enum tagADDRESS { + ADDRESS_BIT_SHIFT = 0x2, + ADDRESS_ALIGN_SIZE = 0x4, + } ADDRESS; + inline void setAddress(const uint64_t value) { + DEBUG_BREAK_IF(value > 0xfffffffffffcL); + TheStructure.Common.Address = value >> ADDRESS_BIT_SHIFT; + } + inline uint64_t getAddress(void) const { + return TheStructure.Common.Address << ADDRESS_BIT_SHIFT; + } + inline void setDataDword0(const uint32_t value) { + TheStructure.Common.DataDword0 = value; + } + inline uint32_t getDataDword0(void) const { + return TheStructure.Common.DataDword0; + } + inline void setDataDword1(const uint32_t value) { + TheStructure.Common.DataDword1 = value; + } + inline uint32_t getDataDword1(void) const { + return TheStructure.Common.DataDword1; + } +} MI_STORE_DATA_IMM; +STATIC_ASSERT(20 == sizeof(MI_STORE_DATA_IMM)); + +typedef struct tagSTATE_SIP { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint64_t Reserved_32 : BITFIELD_RANGE(0, 3); + uint64_t SystemInstructionPointer : BITFIELD_RANGE(4, 63); + } Common; + uint32_t RawData[3]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x1, + } DWORD_LENGTH; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_STATE_SIP = 0x2, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED = 0x1, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_COMMON = 0x0, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagPATCH_CONSTANTS { + SYSTEMINSTRUCTIONPOINTER_BYTEOFFSET = 0x4, + SYSTEMINSTRUCTIONPOINTER_INDEX = 0x1, + } PATCH_CONSTANTS; + void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_STATE_SIP; + TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_COMMON; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + } + static tagSTATE_SIP sInit() { + STATE_SIP state; + state.init(); + return state; + } + inline uint32_t &getRawData(uint32_t const index) { + DEBUG_BREAK_IF(index >= 3); + return TheStructure.RawData[index]; + } + typedef enum tagSYSTEMINSTRUCTIONPOINTER { + SYSTEMINSTRUCTIONPOINTER_BIT_SHIFT = 0x4, + SYSTEMINSTRUCTIONPOINTER_ALIGN_SIZE = 0x10, + } SYSTEMINSTRUCTIONPOINTER; + inline uint64_t getSystemInstructionPointer() const { + return (uint64_t)TheStructure.Common.SystemInstructionPointer << SYSTEMINSTRUCTIONPOINTER_BIT_SHIFT; + } + inline void setSystemInstructionPointer(uint64_t value) { + TheStructure.Common.SystemInstructionPointer = value >> SYSTEMINSTRUCTIONPOINTER_BIT_SHIFT; + } +} STATE_SIP; +STATIC_ASSERT(12 == sizeof(STATE_SIP)); +typedef struct tagGPGPU_CSR_BASE_ADDRESS { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint64_t Reserved_32 : BITFIELD_RANGE(0, 11); + uint64_t GpgpuCsrBaseAddress : BITFIELD_RANGE(12, 63); + } Common; + uint32_t RawData[3]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_UNNAMED_1 = 0x1, + } DWORD_LENGTH; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_GPGPU_CSR_BASE_ADDRESS = 0x4, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED = 0x1, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_COMMON = 0x0, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagPATCH_CONSTANTS { + GPGPUCSRBASEADDRESS_BYTEOFFSET = 0x4, + GPGPUCSRBASEADDRESS_INDEX = 0x1, + } PATCH_CONSTANTS; + inline void init(void) { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_UNNAMED_1; + TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_GPGPU_CSR_BASE_ADDRESS; + TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_COMMON; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + } + static tagGPGPU_CSR_BASE_ADDRESS sInit(void) { + GPGPU_CSR_BASE_ADDRESS state; + state.init(); + return state; + } + inline uint32_t &getRawData(uint32_t const index) { + DEBUG_BREAK_IF(index >= 3); + return TheStructure.RawData[index]; + } + typedef enum tagGPGPUCSRBASEADDRESS { + GPGPUCSRBASEADDRESS_BIT_SHIFT = 0xC, + GPGPUCSRBASEADDRESS_ALIGN_SIZE = 0x1000, + } GPGPUCSRBASEADDRESS; + inline uint64_t getGpgpuCsrBaseAddress() const { + return (uint64_t)TheStructure.Common.GpgpuCsrBaseAddress << GPGPUCSRBASEADDRESS_BIT_SHIFT; + } + inline void setGpgpuCsrBaseAddress(uint64_t value) { + TheStructure.Common.GpgpuCsrBaseAddress = value >> GPGPUCSRBASEADDRESS_BIT_SHIFT; + } +} GPGPU_CSR_BASE_ADDRESS; +STATIC_ASSERT(12 == sizeof(GPGPU_CSR_BASE_ADDRESS)); + +#pragma pack() diff --git a/core/memory_manager/definitions/engine_limits.h b/core/memory_manager/definitions/engine_limits.h index 4baf155ad8..802e83214f 100644 --- a/core/memory_manager/definitions/engine_limits.h +++ b/core/memory_manager/definitions/engine_limits.h @@ -10,7 +10,7 @@ namespace NEO { -constexpr uint32_t numGpgpuEngineInstances = 2u; +constexpr uint32_t numGpgpuEngineInstances = 3u; constexpr uint32_t maxOsContextCount = numGpgpuEngineInstances; constexpr uint32_t maxHandleCount = 1u; diff --git a/manifests/manifest.yml b/manifests/manifest.yml index 935b4519bb..67cd0c67f5 100644 --- a/manifests/manifest.yml +++ b/manifests/manifest.yml @@ -17,7 +17,7 @@ components: branch: infra clean_on_sync: true dest_dir: infra - revision: 7ca96d07b2704967f061e6b531bd4678c5e79f8a + revision: a87011cda63d3d1eb3049c533dfcb916a843b903 type: git internal: branch: master diff --git a/platforms.cmake b/platforms.cmake index 90c01d39b0..af7482673e 100644 --- a/platforms.cmake +++ b/platforms.cmake @@ -11,6 +11,7 @@ set(ALL_GEN_TYPES "") list(APPEND ALL_GEN_TYPES "GEN8") list(APPEND ALL_GEN_TYPES "GEN9") list(APPEND ALL_GEN_TYPES "GEN11") +list(APPEND ALL_GEN_TYPES "GEN12LP") set(ALL_GEN_TYPES_REVERSED ${ALL_GEN_TYPES}) list(REVERSE ALL_GEN_TYPES_REVERSED) @@ -176,6 +177,7 @@ endmacro() SET_FLAGS_FOR("GEN8" "BDW") SET_FLAGS_FOR("GEN9" "SKL" "KBL" "BXT" "GLK" "CFL") SET_FLAGS_FOR("GEN11" "ICLLP" "LKF" "EHL") +SET_FLAGS_FOR("GEN12LP" "TGLLP") # Init lists INIT_LIST("FAMILY_NAME" "TESTED") @@ -300,6 +302,23 @@ if(SUPPORT_GEN11) endif() endif() +if(SUPPORT_GEN12LP) + if(TESTS_GEN12LP) + ADD_ITEM_FOR_GEN("FAMILY_NAME" "TESTED" "GEN12LP" "TGLLPFamily") + endif() + if(SUPPORT_TGLLP) + ADD_PLATFORM_FOR_GEN("SUPPORTED" "GEN12LP" "TGLLP" "LP") + ADD_PLATFORM_FOR_GEN("SUPPORTED_2_0" "GEN12LP" "TGLLP" "LP") + if(TESTS_TGLLP) + ADD_ITEM_FOR_GEN("PLATFORMS" "TESTED" "GEN12LP" "TGLLP") + ADD_ITEM_FOR_GEN("PLATFORMS" "TESTED_APPVERIFIER" "GEN12LP" "TGLLP") + ADD_ITEM_FOR_GEN("CONFIGURATIONS" "AUB_TESTS" "GEN12LP" "tgllp/1/6/16") + ADD_ITEM_FOR_GEN("CONFIGURATIONS" "MT_TESTS" "GEN12LP" "tgllp/1/6/16") + ADD_ITEM_FOR_GEN("CONFIGURATIONS" "UNIT_TESTS" "GEN12LP" "tgllp/1/6/16") + endif() + endif() +endif() + # Get platform lists, flag definition and set default platforms GET_AVAILABLE_PLATFORMS("SUPPORTED" "SUPPORT" ALL_AVAILABLE_SUPPORTED_PLATFORMS) diff --git a/runtime/aub_mem_dump/aub_mem_dump.h b/runtime/aub_mem_dump/aub_mem_dump.h index 43d70e9083..5ed2537ff1 100644 --- a/runtime/aub_mem_dump/aub_mem_dump.h +++ b/runtime/aub_mem_dump/aub_mem_dump.h @@ -392,6 +392,13 @@ struct LrcaHelperVecs : public LrcaHelper { } }; +struct LrcaHelperCcs : public LrcaHelper { + LrcaHelperCcs(uint32_t base) : LrcaHelper(base) { + aubHintLRCA = DataTypeHintValues::TraceLogicalRingContextCcs; + name = "CCS"; + } +}; + extern const uint64_t g_pageMask; extern const size_t g_dwordCountMax; } // namespace AubMemDump diff --git a/runtime/aub_mem_dump/aub_services.h b/runtime/aub_mem_dump/aub_services.h index 4e781ddf7f..d930e7a8da 100644 --- a/runtime/aub_mem_dump/aub_services.h +++ b/runtime/aub_mem_dump/aub_services.h @@ -99,7 +99,8 @@ struct CmdServicesMemTraceVersion { Icllp = 19, Cfl = 24, Lkf = 25, - Ehl = 28 + Ehl = 28, + Tgllp = 22 }; }; struct RecordingMethodValues { @@ -745,6 +746,7 @@ struct CmdServicesMemTraceMemoryWrite { TraceCommandBufferBlt = 40, TraceRingContextBcs = 56, TraceCcViewport = 24, + TraceLogicalRingContextCcs = 64, TraceIndexBuffer = 13, TraceScratchSpace = 27, TraceGucContextDescriptor = 61, diff --git a/runtime/builtin_kernels_simulation/gen12lp/scheduler_simulation.cpp b/runtime/builtin_kernels_simulation/gen12lp/scheduler_simulation.cpp new file mode 100644 index 0000000000..bf62702339 --- /dev/null +++ b/runtime/builtin_kernels_simulation/gen12lp/scheduler_simulation.cpp @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/builtin_kernels_simulation/scheduler_simulation.h" + +#include "core/memory_manager/graphics_allocation.h" +#include "runtime/builtin_kernels_simulation/opencl_c.h" +#include "runtime/builtin_kernels_simulation/scheduler_simulation.inl" +#include "runtime/execution_model/device_enqueue.h" +#include "runtime/gen12lp/hw_cmds.h" + +#include "CL/cl.h" + +#include + +using namespace NEO; +using namespace BuiltinKernelsSimulation; + +namespace Gen12LPSchedulerSimulation { + +#define SCHEDULER_EMULATION + +uint GetNextPowerof2(uint number); + +float __intel__getProfilingTimerResolution() { + return static_cast(DEFAULT_GEN12LP_PLATFORM::hwInfo.capabilityTable.defaultProfilingTimerResolution); +} + +#include "runtime/gen12lp/device_enqueue.h" +#include "runtime/gen12lp/scheduler_definitions.h" +#include "runtime/gen12lp/scheduler_igdrcl_built_in.inl" +#include "runtime/scheduler/scheduler.cl" +} // namespace Gen12LPSchedulerSimulation + +namespace BuiltinKernelsSimulation { + +template <> +void SchedulerSimulation::startScheduler(uint32_t index, + GraphicsAllocation *queue, + GraphicsAllocation *commandsStack, + GraphicsAllocation *eventsPool, + GraphicsAllocation *secondaryBatchBuffer, + GraphicsAllocation *dsh, + GraphicsAllocation *reflectionSurface, + GraphicsAllocation *queueStorageBuffer, + GraphicsAllocation *ssh, + GraphicsAllocation *debugQueue) { + + threadIDToLocalIDmap.insert(std::make_pair(std::this_thread::get_id(), index)); + + while (!conditionReady) { + } + + Gen12LPSchedulerSimulation::SchedulerParallel20((IGIL_CommandQueue *)queue->getUnderlyingBuffer(), + (uint *)commandsStack->getUnderlyingBuffer(), + (IGIL_EventPool *)eventsPool->getUnderlyingBuffer(), + (uint *)secondaryBatchBuffer->getUnderlyingBuffer(), + (char *)dsh->getUnderlyingBuffer(), + (IGIL_KernelDataHeader *)reflectionSurface->getUnderlyingBuffer(), + (uint *)queueStorageBuffer->getUnderlyingBuffer(), + (char *)ssh->getUnderlyingBuffer(), + debugQueue != nullptr ? (DebugDataBuffer *)debugQueue->getUnderlyingBuffer() : nullptr); +} + +template <> +void SchedulerSimulation::patchGpGpuWalker(uint secondLevelBatchOffset, + __global uint *secondaryBatchBuffer, + uint interfaceDescriptorOffset, + uint simdSize, + uint totalLocalWorkSize, + uint3 dimSize, + uint3 startPoint, + uint numberOfHwThreadsPerWg, + uint indirectPayloadSize, + uint ioHoffset) { + Gen12LPSchedulerSimulation::patchGpGpuWalker(secondLevelBatchOffset, + secondaryBatchBuffer, + interfaceDescriptorOffset, + simdSize, + totalLocalWorkSize, + dimSize, + startPoint, + numberOfHwThreadsPerWg, + indirectPayloadSize, + ioHoffset); +} + +template class SchedulerSimulation; + +} // namespace BuiltinKernelsSimulation diff --git a/runtime/dll/linux/devices/devices_base.inl b/runtime/dll/linux/devices/devices_base.inl index ae50864fc8..113186c544 100644 --- a/runtime/dll/linux/devices/devices_base.inl +++ b/runtime/dll/linux/devices/devices_base.inl @@ -6,6 +6,13 @@ */ // clang-format off +#ifdef SUPPORT_GEN12LP +#ifdef SUPPORT_TGLLP +DEVICE( IGEN12LP_GT1_MOB_DEVICE_F0_ID, TGLLP_1x6x16, GTTYPE_GT2 ) +DEVICE( ITGL_LP_1x6x16_ULT_15W_DEVICE_F0_ID, TGLLP_1x6x16, GTTYPE_GT2 ) +#endif +#endif + #ifdef SUPPORT_GEN11 #ifdef SUPPORT_ICLLP // GT1 diff --git a/runtime/gen12lp/additional_files_gen12lp.cmake b/runtime/gen12lp/additional_files_gen12lp.cmake new file mode 100644 index 0000000000..7c1d93d4d2 --- /dev/null +++ b/runtime/gen12lp/additional_files_gen12lp.cmake @@ -0,0 +1,17 @@ +# +# Copyright (C) 2019 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +set(RUNTIME_SRCS_ADDITIONAL_FILES_GEN12LP + ${CMAKE_CURRENT_SOURCE_DIR}/gen12lp/helpers_gen12lp.h + ${CMAKE_CURRENT_SOURCE_DIR}/gen12lp/definitions${BRANCH_DIR_SUFFIX}/command_queue_helpers_gen12lp.inl + ${CMAKE_CURRENT_SOURCE_DIR}/gen12lp/definitions${BRANCH_DIR_SUFFIX}/hardware_commands_helper_gen12lp.inl + ${CMAKE_CURRENT_SOURCE_DIR}/gen12lp${BRANCH_DIR_SUFFIX}/helpers_gen12lp.cpp +) + +include_directories(${IGDRCL_SOURCE_DIR}/runtime/gen12lp/definitions${BRANCH_DIR_SUFFIX}/) + +target_sources(${NEO_STATIC_LIB_NAME} PRIVATE ${RUNTIME_SRCS_ADDITIONAL_FILES_GEN12LP}) +set_property(GLOBAL PROPERTY RUNTIME_SRCS_ADDITIONAL_FILES_GEN12LP ${RUNTIME_SRCS_ADDITIONAL_FILES_GEN12LP}) \ No newline at end of file diff --git a/runtime/gen12lp/aub_command_stream_receiver_gen12lp.cpp b/runtime/gen12lp/aub_command_stream_receiver_gen12lp.cpp new file mode 100644 index 0000000000..071ac5e82b --- /dev/null +++ b/runtime/gen12lp/aub_command_stream_receiver_gen12lp.cpp @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "core/memory_manager/memory_pool.h" +#include "runtime/aub_mem_dump/aub_alloc_dump.h" +#include "runtime/command_stream/aub_command_stream_receiver_hw.h" +#include "runtime/command_stream/aub_command_stream_receiver_hw_bdw_plus.inl" +#include "runtime/helpers/array_count.h" +#include "runtime/helpers/base_object.h" + +namespace NEO { +typedef TGLLPFamily Family; +static auto gfxCore = IGFX_GEN12LP_CORE; + +template <> +constexpr uint32_t AUBCommandStreamReceiverHw::getMaskAndValueForPollForCompletion() { + return 0x00008000; +} + +template <> +void AUBCommandStreamReceiverHw::addContextToken(uint32_t dumpHandle) { + AUB::createContext(*stream, dumpHandle); +} + +template <> +void populateFactoryTable>() { + extern AubCommandStreamReceiverCreateFunc aubCommandStreamReceiverFactory[IGFX_MAX_CORE]; + UNRECOVERABLE_IF(!isInRange(gfxCore, aubCommandStreamReceiverFactory)); + aubCommandStreamReceiverFactory[gfxCore] = AUBCommandStreamReceiverHw::create; +} + +template <> +uint32_t AUBCommandStreamReceiverHw::getGUCWorkQueueItemHeader() { + if (aub_stream::ENGINE_CCS == osContext->getEngineType()) { + return 0x00030401; + } + return 0x00030001; +} + +template class AUBCommandStreamReceiverHw; +} // namespace NEO diff --git a/runtime/gen12lp/aub_mapper.h b/runtime/gen12lp/aub_mapper.h new file mode 100644 index 0000000000..b0ba84d0e9 --- /dev/null +++ b/runtime/gen12lp/aub_mapper.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "core/memory_manager/memory_constants.h" +#include "runtime/gen_common/aub_mapper_base.h" + +#include "engine_node.h" + +namespace NEO { +struct TGLLPFamily; + +template <> +struct AUBFamilyMapper { + enum { device = AubMemDump::DeviceValues::Tgllp }; + + using AubTraits = AubMemDump::Traits; + + static const AubMemDump::LrcaHelper *const csTraits[aub_stream::NUM_ENGINES]; + + static const MMIOList globalMMIO; + static const MMIOList *perEngineMMIO[aub_stream::NUM_ENGINES]; + + typedef AubMemDump::AubDump AUB; +}; +} // namespace NEO diff --git a/runtime/gen12lp/aub_mem_dump_gen12lp.cpp b/runtime/gen12lp/aub_mem_dump_gen12lp.cpp new file mode 100644 index 0000000000..bc18c9aaca --- /dev/null +++ b/runtime/gen12lp/aub_mem_dump_gen12lp.cpp @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/aub_mem_dump/aub_alloc_dump.inl" +#include "runtime/aub_mem_dump/aub_mem_dump.inl" +#include "runtime/helpers/completion_stamp.h" +#include "runtime/helpers/hw_helper.h" + +#include "aub_mapper.h" +#include "config.h" +#include "reg_configs_common.h" + +namespace AubMemDump { + +enum { + device = DeviceValues::Tgllp +}; + +// Instantiate these common template implementations. +template struct AubDump>; +template struct AubDump>; + +template struct AubPageTableHelper32>; +template struct AubPageTableHelper64>; +} // namespace AubMemDump + +namespace NEO { +using Family = TGLLPFamily; + +static const AubMemDump::LrcaHelperRcs rcs(0x002000); +static const AubMemDump::LrcaHelperBcs bcs(0x022000); +static const AubMemDump::LrcaHelperVcs vcs(0x1c0000); +static const AubMemDump::LrcaHelperVecs vecs(0x1c8000); +static const AubMemDump::LrcaHelperCcs ccs(0x1a000); + +const AubMemDump::LrcaHelper *const AUBFamilyMapper::csTraits[aub_stream::NUM_ENGINES] = { + &rcs, + &bcs, + &vcs, + &vecs, + &ccs}; + +const MMIOList AUBFamilyMapper::globalMMIO = { + // GLOBAL_MOCS + MMIOPair(0x00004000, 0x00000008), + MMIOPair(0x00004004, 0x00000038), + MMIOPair(0x00004008, 0x00000038), + MMIOPair(0x0000400C, 0x00000008), + MMIOPair(0x00004010, 0x00000018), + MMIOPair(0x00004014, 0x00060038), + MMIOPair(0x00004018, 0x00000000), + MMIOPair(0x0000401C, 0x00000033), + MMIOPair(0x00004020, 0x00060037), + MMIOPair(0x00004024, 0x0000003B), + MMIOPair(0x00004028, 0x00000032), + MMIOPair(0x0000402C, 0x00000036), + MMIOPair(0x00004030, 0x0000003A), + MMIOPair(0x00004034, 0x00000033), + MMIOPair(0x00004038, 0x00000037), + MMIOPair(0x0000403C, 0x0000003B), + MMIOPair(0x00004040, 0x00000030), + MMIOPair(0x00004044, 0x00000034), + MMIOPair(0x00004048, 0x00000038), + MMIOPair(0x0000404C, 0x00000031), + MMIOPair(0x00004050, 0x00000032), + MMIOPair(0x00004054, 0x00000036), + MMIOPair(0x00004058, 0x0000003A), + MMIOPair(0x0000405C, 0x00000033), + MMIOPair(0x00004060, 0x00000037), + MMIOPair(0x00004064, 0x0000003B), + MMIOPair(0x00004068, 0x00000032), + MMIOPair(0x0000406C, 0x00000036), + MMIOPair(0x00004070, 0x0000003A), + MMIOPair(0x00004074, 0x00000033), + MMIOPair(0x00004078, 0x00000037), + MMIOPair(0x0000407C, 0x0000003B), + MMIOPair(0x00004080, 0x00000030), + MMIOPair(0x00004084, 0x00000034), + MMIOPair(0x00004088, 0x00000038), + MMIOPair(0x0000408C, 0x00000031), + MMIOPair(0x00004090, 0x00000032), + MMIOPair(0x00004094, 0x00000036), + MMIOPair(0x00004098, 0x0000003A), + MMIOPair(0x0000409C, 0x00000033), + MMIOPair(0x000040A0, 0x00000037), + MMIOPair(0x000040A4, 0x0000003B), + MMIOPair(0x000040A8, 0x00000032), + MMIOPair(0x000040AC, 0x00000036), + MMIOPair(0x000040B0, 0x0000003A), + MMIOPair(0x000040B4, 0x00000033), + MMIOPair(0x000040B8, 0x00000037), + MMIOPair(0x000040BC, 0x0000003B), + MMIOPair(0x000040C0, 0x00000038), + MMIOPair(0x000040C4, 0x00000034), + MMIOPair(0x000040C8, 0x00000038), + MMIOPair(0x000040CC, 0x00000031), + MMIOPair(0x000040D0, 0x00000032), + MMIOPair(0x000040D4, 0x00000036), + MMIOPair(0x000040D8, 0x0000003A), + MMIOPair(0x000040DC, 0x00000033), + MMIOPair(0x000040E0, 0x00000037), + MMIOPair(0x000040E4, 0x0000003B), + MMIOPair(0x000040E8, 0x00000032), + MMIOPair(0x000040EC, 0x00000036), + MMIOPair(0x000040F0, 0x00000038), + MMIOPair(0x000040F4, 0x00000038), + MMIOPair(0x000040F8, 0x00000038), + MMIOPair(0x000040FC, 0x00000038), + + // LNCF_MOCS + MMIOPair(0x0000B020, 0x00300010), + MMIOPair(0x0000B024, 0x00300010), + MMIOPair(0x0000B028, 0x00300030), + MMIOPair(0x0000B02C, 0x00000000), + MMIOPair(0x0000B030, 0x0030001F), + MMIOPair(0x0000B034, 0x00170013), + MMIOPair(0x0000B038, 0x0000001F), + MMIOPair(0x0000B03C, 0x00000000), + MMIOPair(0x0000B040, 0x00100000), + MMIOPair(0x0000B044, 0x00170013), + MMIOPair(0x0000B048, 0x0010001F), + MMIOPair(0x0000B04C, 0x00170013), + MMIOPair(0x0000B050, 0x0030001F), + MMIOPair(0x0000B054, 0x00170013), + MMIOPair(0x0000B058, 0x0000001F), + MMIOPair(0x0000B05C, 0x00000000), + MMIOPair(0x0000B060, 0x00100000), + MMIOPair(0x0000B064, 0x00170013), + MMIOPair(0x0000B068, 0x0010001F), + MMIOPair(0x0000B06C, 0x00170013), + MMIOPair(0x0000B070, 0x0030001F), + MMIOPair(0x0000B074, 0x00170013), + MMIOPair(0x0000B078, 0x0000001F), + MMIOPair(0x0000B07C, 0x00000000), + MMIOPair(0x0000B080, 0x00000030), + MMIOPair(0x0000B084, 0x00170013), + MMIOPair(0x0000B088, 0x0010001F), + MMIOPair(0x0000B08C, 0x00170013), + MMIOPair(0x0000B090, 0x0030001F), + MMIOPair(0x0000B094, 0x00170013), + MMIOPair(0x0000B098, 0x00300010), + MMIOPair(0x0000B09C, 0x00300010), + + //PAT_INDEX + MMIOPair(0x00004100, 0x0000000), + MMIOPair(0x00004104, 0x0000000), + MMIOPair(0x00004108, 0x0000000), + MMIOPair(0x0000410c, 0x0000000), + MMIOPair(0x00004110, 0x0000000), + MMIOPair(0x00004114, 0x0000000), + MMIOPair(0x00004118, 0x0000000), + MMIOPair(0x0000411c, 0x0000000), + + MMIOPair(0x00004b80, 0xffff1001), //GACB_PERF_CTRL_REG + MMIOPair(0x00007000, 0xffff0000), //CACHE_MODE_0 + MMIOPair(0x00007004, 0xffff0000), //CACHE_MODE_1 + MMIOPair(0x00009008, 0x00000200), //IDICR + MMIOPair(0x0000900c, 0x00001b40), //SNPCR + MMIOPair(0x0000b120, 0x14000002), //LTCDREG + MMIOPair(0x00042080, 0x00000000), //CHICKEN_MISC_1 +}; + +static const MMIOList mmioListRCS = { + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x00002058), 0x00000000), //CTX_WA_PTR_RCSUNIT + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000020a8), 0x00000000), //IMR + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE + + MMIOPair(0x00002090, 0xffff0000), //CHICKEN_PWR_CTX_RASTER_1 + MMIOPair(0x000020e0, 0xffff4000), //FF_SLICE_CS_CHICKEN1_RCSUNIT + MMIOPair(0x000020e4, 0xffff0000), //FF_SLICE_CS_CHICKEN2_RCSUNIT + MMIOPair(0x000020ec, 0xffff0051), //CS_DEBUG_MODE1 + + // FORCE_TO_NONPRIV + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024d0), 0x00007014), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024d4), 0x0000e48c), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024d8), 0x0000e18c), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024dc), 0x00004de0), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024e0), 0x00004de4), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024e4), 0x0000f180), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024e8), 0x0000e194), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024ec), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024f0), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024f4), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024f8), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024fc), 0x0000e000), + + MMIOPair(0x00002580, 0xffff0005), //CS_CHICKEN1 + MMIOPair(0x0000e194, 0xffff0002), //CHICKEN_SAMPLER_2 + + MMIOPair(0x0000B134, 0xD0000020) //L3ALLOCREG +}; + +static const MMIOList mmioListBCS = { + MMIOPair(AubMemDump::computeRegisterOffset(bcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE +}; + +static const MMIOList mmioListVCS = { + MMIOPair(AubMemDump::computeRegisterOffset(vcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE +}; + +static const MMIOList mmioListVECS = { + MMIOPair(AubMemDump::computeRegisterOffset(vecs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE +}; + +static const MMIOList mmioListCCS = { + MMIOPair(0x0000ce90, 0x00010001), //GFX_MULT_CTXT_CTL + MMIOPair(0x00014800, 0x00010001), //RCU_MODE + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE + + // FORCE_TO_NONPRIV + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024d0), 0x00007014), + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024d4), 0x0000e48c), + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024d8), 0x0000e18c), + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024dc), 0x00004de0), + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024e0), 0x00004de4), + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024e4), 0x0000f180), + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024e8), 0x0000e194), + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024ec), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024f0), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024f4), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024f8), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(ccs.mmioBase, 0x000024fc), 0x0000e000), + + MMIOPair(0x0000B234, 0xD0000020) //L3ALLOCREG_CCS0 +}; + +const MMIOList *AUBFamilyMapper::perEngineMMIO[aub_stream::NUM_ENGINES] = { + &mmioListRCS, + &mmioListBCS, + &mmioListVCS, + &mmioListVECS, + &mmioListCCS}; +} // namespace NEO + +namespace AubAllocDump { +using namespace NEO; + +template SurfaceInfo *getDumpSurfaceInfo(GraphicsAllocation &gfxAllocation, DumpFormat dumpFormat); + +template uint32_t getImageSurfaceTypeFromGmmResourceType(GMM_RESOURCE_TYPE gmmResourceType); + +template void dumpBufferInBinFormat(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context); + +template void dumpImageInBmpFormat(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context); + +template void dumpBufferInTreFormat(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context); + +template void dumpImageInTreFormat(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context); + +template void dumpAllocation(DumpFormat dumpFormat, GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context); +} // namespace AubAllocDump diff --git a/runtime/gen12lp/buffer_gen12lp.cpp b/runtime/gen12lp/buffer_gen12lp.cpp new file mode 100644 index 0000000000..26b786467a --- /dev/null +++ b/runtime/gen12lp/buffer_gen12lp.cpp @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/gen12lp/hw_cmds.h" +#include "runtime/mem_obj/buffer_bdw_plus.inl" + +namespace NEO { + +typedef TGLLPFamily Family; +static auto gfxCore = IGFX_GEN12LP_CORE; + +#include "runtime/mem_obj/buffer_factory_init.inl" +} // namespace NEO diff --git a/runtime/gen12lp/command_queue_gen12lp.cpp b/runtime/gen12lp/command_queue_gen12lp.cpp new file mode 100644 index 0000000000..6ceea3f93e --- /dev/null +++ b/runtime/gen12lp/command_queue_gen12lp.cpp @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_queue/command_queue_hw.h" +#include "runtime/command_queue/command_queue_hw_bdw_plus.inl" + +#include "command_queue_helpers_gen12lp.inl" + +namespace NEO { + +typedef TGLLPFamily Family; +static auto gfxCore = IGFX_GEN12LP_CORE; + +template <> +void populateFactoryTable>() { + extern CommandQueueCreateFunc commandQueueFactory[IGFX_MAX_CORE]; + commandQueueFactory[gfxCore] = CommandQueueHw::create; +} + +template class CommandQueueHw; + +} // namespace NEO diff --git a/runtime/gen12lp/command_stream_receiver_hw_gen12lp.cpp b/runtime/gen12lp/command_stream_receiver_hw_gen12lp.cpp new file mode 100644 index 0000000000..210efeccce --- /dev/null +++ b/runtime/gen12lp/command_stream_receiver_hw_gen12lp.cpp @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_stream/command_stream_receiver_hw_bdw_plus.inl" +#include "runtime/command_stream/device_command_stream.h" +#include "runtime/gen12lp/helpers_gen12lp.h" +#include "runtime/gen12lp/hw_cmds.h" +#include "runtime/helpers/blit_commands_helper_bdw_plus.inl" + +#include "hw_info.h" + +namespace NEO { +typedef TGLLPFamily Family; +static auto gfxCore = IGFX_GEN12LP_CORE; + +template <> +void CommandStreamReceiverHw::programL3(LinearStream &csr, DispatchFlags &dispatchFlags, uint32_t &newL3Config) { +} + +template <> +size_t CommandStreamReceiverHw::getCmdSizeForL3Config() const { + return 0; +} + +template <> +size_t CommandStreamReceiverHw::getCmdSizeForComputeMode() { + if (!csrSizeRequestFlags.hasSharedHandles) { + for (const auto &allocation : this->getResidencyAllocations()) { + if (allocation->peekSharedHandle()) { + csrSizeRequestFlags.hasSharedHandles = true; + break; + } + } + } + + size_t size = 0; + if (csrSizeRequestFlags.coherencyRequestChanged || csrSizeRequestFlags.hasSharedHandles) { + size += sizeof(typename Family::STATE_COMPUTE_MODE); + if (csrSizeRequestFlags.hasSharedHandles) { + size += sizeof(typename Family::PIPE_CONTROL); + } + } + return size; +} + +template <> +void CommandStreamReceiverHw::programComputeMode(LinearStream &stream, DispatchFlags &dispatchFlags) { + typedef typename Family::STATE_COMPUTE_MODE STATE_COMPUTE_MODE; + typedef typename Family::PIPE_CONTROL PIPE_CONTROL; + + if (csrSizeRequestFlags.coherencyRequestChanged || csrSizeRequestFlags.hasSharedHandles) { + auto stateComputeMode = stream.getSpaceForCmd(); + *stateComputeMode = Family::cmdInitStateComputeMode; + STATE_COMPUTE_MODE::FORCE_NON_COHERENT coherencyValue = !dispatchFlags.requiresCoherency ? STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT : STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_DISABLED; + stateComputeMode->setForceNonCoherent(coherencyValue); + stateComputeMode->setMaskBits(Family::stateComputeModeForceNonCoherentMask); + + this->lastSentCoherencyRequest = static_cast(dispatchFlags.requiresCoherency); + + if (csrSizeRequestFlags.hasSharedHandles) { + auto pc = stream.getSpaceForCmd(); + *pc = Family::cmdInitPipeControl; + } + } +} + +template <> +void populateFactoryTable>() { + extern CommandStreamReceiverCreateFunc commandStreamReceiverFactory[IGFX_MAX_CORE]; + commandStreamReceiverFactory[gfxCore] = DeviceCommandStreamReceiver::create; +} + +template <> +inline typename Family::PIPE_CONTROL *CommandStreamReceiverHw::addPipeControlBeforeStateBaseAddress(LinearStream &commandStream) { + auto pCmd = addPipeControlCmd(commandStream); + pCmd->setTextureCacheInvalidationEnable(true); + pCmd->setDcFlushEnable(true); + + if (Gen12LPHelpers::hdcFlushForPipeControlBeforeStateBaseAddressRequired(executionEnvironment.getHardwareInfo()->platform.eProductFamily)) { + pCmd->setHdcFlushEnable(true); + } + return pCmd; +} + +template class CommandStreamReceiverHw; +template struct BlitCommandsHelper; + +const Family::GPGPU_WALKER Family::cmdInitGpgpuWalker = Family::GPGPU_WALKER::sInit(); +const Family::INTERFACE_DESCRIPTOR_DATA Family::cmdInitInterfaceDescriptorData = Family::INTERFACE_DESCRIPTOR_DATA::sInit(); +const Family::MEDIA_INTERFACE_DESCRIPTOR_LOAD Family::cmdInitMediaInterfaceDescriptorLoad = Family::MEDIA_INTERFACE_DESCRIPTOR_LOAD::sInit(); +const Family::MEDIA_STATE_FLUSH Family::cmdInitMediaStateFlush = Family::MEDIA_STATE_FLUSH::sInit(); +const Family::MI_BATCH_BUFFER_START Family::cmdInitBatchBufferStart = Family::MI_BATCH_BUFFER_START::sInit(); +const Family::MI_BATCH_BUFFER_END Family::cmdInitBatchBufferEnd = Family::MI_BATCH_BUFFER_END::sInit(); +const Family::PIPE_CONTROL Family::cmdInitPipeControl = Family::PIPE_CONTROL::sInit(); +const Family::STATE_COMPUTE_MODE Family::cmdInitStateComputeMode = Family::STATE_COMPUTE_MODE::sInit(); +const Family::MI_SEMAPHORE_WAIT Family::cmdInitMiSemaphoreWait = Family::MI_SEMAPHORE_WAIT::sInit(); +const Family::RENDER_SURFACE_STATE Family::cmdInitRenderSurfaceState = Family::RENDER_SURFACE_STATE::sInit(); +const Family::MI_LOAD_REGISTER_IMM Family::cmdInitLoadRegisterImm = Family::MI_LOAD_REGISTER_IMM::sInit(); +const Family::MI_LOAD_REGISTER_REG Family::cmdInitLoadRegisterReg = Family::MI_LOAD_REGISTER_REG::sInit(); +const Family::MI_LOAD_REGISTER_MEM Family::cmdInitLoadRegisterMem = Family::MI_LOAD_REGISTER_MEM::sInit(); +const Family::MI_STORE_DATA_IMM Family::cmdInitStoreDataImm = Family::MI_STORE_DATA_IMM::sInit(); +const Family::MI_STORE_REGISTER_MEM Family::cmdInitStoreRegisterMem = Family::MI_STORE_REGISTER_MEM::sInit(); +const Family::MI_NOOP Family::cmdInitNoop = Family::MI_NOOP::sInit(); +const Family::MI_REPORT_PERF_COUNT Family::cmdInitReportPerfCount = Family::MI_REPORT_PERF_COUNT::sInit(); +const Family::MI_ATOMIC Family::cmdInitAtomic = Family::MI_ATOMIC::sInit(); +const Family::PIPELINE_SELECT Family::cmdInitPipelineSelect = Family::PIPELINE_SELECT::sInit(); +const Family::MI_ARB_CHECK Family::cmdInitArbCheck = Family::MI_ARB_CHECK::sInit(); +const Family::MEDIA_VFE_STATE Family::cmdInitMediaVfeState = Family::MEDIA_VFE_STATE::sInit(); +const Family::STATE_BASE_ADDRESS Family::cmdInitStateBaseAddress = Family::STATE_BASE_ADDRESS::sInit(); +const Family::MEDIA_SURFACE_STATE Family::cmdInitMediaSurfaceState = Family::MEDIA_SURFACE_STATE::sInit(); +const Family::SAMPLER_STATE Family::cmdInitSamplerState = Family::SAMPLER_STATE::sInit(); +const Family::GPGPU_CSR_BASE_ADDRESS Family::cmdInitGpgpuCsrBaseAddress = Family::GPGPU_CSR_BASE_ADDRESS::sInit(); +const Family::STATE_SIP Family::cmdInitStateSip = Family::STATE_SIP::sInit(); +const Family::BINDING_TABLE_STATE Family::cmdInitBindingTableState = Family::BINDING_TABLE_STATE::sInit(); +const Family::MI_USER_INTERRUPT Family::cmdInitUserInterrupt = Family::MI_USER_INTERRUPT::sInit(); +const Family::XY_SRC_COPY_BLT Family::cmdInitXyCopyBlt = Family::XY_SRC_COPY_BLT::sInit(); +const Family::MI_FLUSH_DW Family::cmdInitMiFlushDw = Family::MI_FLUSH_DW::sInit(); +} // namespace NEO diff --git a/runtime/gen12lp/command_stream_receiver_simulated_common_hw_gen12lp.cpp b/runtime/gen12lp/command_stream_receiver_simulated_common_hw_gen12lp.cpp new file mode 100644 index 0000000000..cc8c527631 --- /dev/null +++ b/runtime/gen12lp/command_stream_receiver_simulated_common_hw_gen12lp.cpp @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_stream/command_stream_receiver_simulated_common_hw_bdw_plus.inl" +#include "runtime/gen12lp/helpers_gen12lp.h" + +namespace NEO { +typedef TGLLPFamily Family; + +template <> +void CommandStreamReceiverSimulatedCommonHw::initGlobalMMIO() { + for (auto &mmioPair : AUBFamilyMapper::globalMMIO) { + stream->writeMMIO(mmioPair.first, mmioPair.second); + } + + Gen12LPHelpers::initAdditionalGlobalMMIO(*this, *stream); +} + +template <> +uint64_t CommandStreamReceiverSimulatedCommonHw::getPPGTTAdditionalBits(GraphicsAllocation *gfxAllocation) { + return BIT(PageTableEntry::presentBit) | BIT(PageTableEntry::writableBit) | Gen12LPHelpers::getPPGTTAdditionalBits(gfxAllocation); +} + +template <> +void CommandStreamReceiverSimulatedCommonHw::getGTTData(void *memory, AubGTTData &data) { + data = {}; + data.present = true; + + Gen12LPHelpers::adjustAubGTTData(*this, data); +} + +template <> +void CommandStreamReceiverSimulatedCommonHw::submitLRCA(const MiContextDescriptorReg &contextDescriptor) { + auto mmioBase = getCsTraits(osContext->getEngineType()).mmioBase; + stream->writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2510), contextDescriptor.ulData[0]); + stream->writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2514), contextDescriptor.ulData[1]); + + // Load our new exec list + stream->writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2550), 1); +} + +template class CommandStreamReceiverSimulatedCommonHw; +} // namespace NEO diff --git a/runtime/gen12lp/definitions/command_queue_helpers_gen12lp.inl b/runtime/gen12lp/definitions/command_queue_helpers_gen12lp.inl new file mode 100644 index 0000000000..b6f83fa883 --- /dev/null +++ b/runtime/gen12lp/definitions/command_queue_helpers_gen12lp.inl @@ -0,0 +1,8 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_queue/enqueue_resource_barrier.h" diff --git a/runtime/gen12lp/definitions/hardware_commands_helper_gen12lp.inl b/runtime/gen12lp/definitions/hardware_commands_helper_gen12lp.inl new file mode 100644 index 0000000000..2a73f8cdab --- /dev/null +++ b/runtime/gen12lp/definitions/hardware_commands_helper_gen12lp.inl @@ -0,0 +1,6 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ diff --git a/runtime/gen12lp/device_enqueue.h b/runtime/gen12lp/device_enqueue.h new file mode 100644 index 0000000000..6c0336e432 --- /dev/null +++ b/runtime/gen12lp/device_enqueue.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "../execution_model/device_enqueue.h" + +// Uncomment this macro to build "empty" schedulers +//#define WA_DISABLE_SCHEDULERS 1 + +#define OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G12LP (15 * sizeof(uint)) +#define OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G12LP (6 * sizeof(uint)) + +#define OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G12LP_DWORD_OFFSET (6) +#define OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G12LP_DWORD_OFFSET (15) + +#define SECOND_LEVEL_BUFFER_SPACE_FOR_EACH_ENQUEUE_GEN12LP (OCLRT_SIZEOF_MEDIA_STATE_FLUSH + OCLRT_SIZEOF_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DEVICE_CMD + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G12LP + OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G12LP + OCLRT_SIZEOF_MEDIA_STATE_FLUSH + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G12LP + CS_PREFETCH_SIZE) + +#define SECOND_LEVEL_BUFFER_NUMBER_OF_ENQUEUES_GEN12LP (128) diff --git a/runtime/gen12lp/device_queue_gen12lp.cpp b/runtime/gen12lp/device_queue_gen12lp.cpp new file mode 100644 index 0000000000..7b0921d900 --- /dev/null +++ b/runtime/gen12lp/device_queue_gen12lp.cpp @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/device_queue/device_queue_hw.h" +#include "runtime/device_queue/device_queue_hw_bdw_plus.inl" +#include "runtime/device_queue/device_queue_hw_profiling.inl" +#include "runtime/gen12lp/hw_cmds.h" + +namespace NEO { +typedef TGLLPFamily Family; +static auto gfxCore = IGFX_GEN12LP_CORE; + +template <> +void populateFactoryTable>() { + extern DeviceQueueCreateFunc deviceQueueFactory[IGFX_MAX_CORE]; + deviceQueueFactory[gfxCore] = DeviceQueueHw::create; +} + +template <> +size_t DeviceQueueHw::getWaCommandsSize() { return 0; } + +template <> +void DeviceQueueHw::addArbCheckCmdWa() {} + +template <> +void DeviceQueueHw::addMiAtomicCmdWa(uint64_t atomicOpPlaceholder) {} + +template <> +void DeviceQueueHw::addLriCmdWa(bool setArbCheck) {} + +template <> +void DeviceQueueHw::addPipeControlCmdWa(bool isNoopCmd) {} + +template class DeviceQueueHw; +} // namespace NEO diff --git a/runtime/gen12lp/enable_family_full_gen12lp.cpp b/runtime/gen12lp/enable_family_full_gen12lp.cpp new file mode 100644 index 0000000000..4a2c468610 --- /dev/null +++ b/runtime/gen12lp/enable_family_full_gen12lp.cpp @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_queue/command_queue_hw.h" +#include "runtime/command_stream/aub_command_stream_receiver_hw.h" +#include "runtime/command_stream/command_stream_receiver_hw.h" +#include "runtime/command_stream/tbx_command_stream_receiver_hw.h" +#include "runtime/device_queue/device_queue_hw.h" +#include "runtime/gen12lp/hw_cmds.h" +#include "runtime/helpers/hw_helper.h" +#include "runtime/mem_obj/buffer.h" +#include "runtime/mem_obj/image.h" +#include "runtime/sampler/sampler.h" + +namespace NEO { + +extern HwHelper *hwHelperFactory[IGFX_MAX_CORE]; + +typedef TGLLPFamily Family; +static auto gfxFamily = IGFX_GEN12LP_CORE; + +struct EnableGen12LP { + EnableGen12LP() { + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + hwHelperFactory[gfxFamily] = &HwHelperHw::get(); + } +}; + +static EnableGen12LP enable; +} // namespace NEO diff --git a/runtime/gen12lp/enable_gen12lp.cpp b/runtime/gen12lp/enable_gen12lp.cpp new file mode 100644 index 0000000000..b6af2d1e18 --- /dev/null +++ b/runtime/gen12lp/enable_gen12lp.cpp @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/gen12lp/hw_cmds.h" +#include "runtime/helpers/enable_product.inl" +#include "runtime/os_interface/hw_info_config.h" + +namespace NEO { + +#ifdef SUPPORT_TGLLP +static EnableGfxProductHw enableGfxProductHwTGLLP; +#endif + +} // namespace NEO diff --git a/runtime/gen12lp/enable_hw_info_config_gen12lp.cpp b/runtime/gen12lp/enable_hw_info_config_gen12lp.cpp new file mode 100644 index 0000000000..00205e6616 --- /dev/null +++ b/runtime/gen12lp/enable_hw_info_config_gen12lp.cpp @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/gen12lp/hw_cmds.h" +#include "runtime/os_interface/hw_info_config.h" + +namespace NEO { + +#ifdef SUPPORT_TGLLP +static EnableProductHwInfoConfig enableTGLLP; +#endif + +} // namespace NEO diff --git a/runtime/gen12lp/experimental_command_buffer_gen12lp.cpp b/runtime/gen12lp/experimental_command_buffer_gen12lp.cpp new file mode 100644 index 0000000000..5ee7b2a245 --- /dev/null +++ b/runtime/gen12lp/experimental_command_buffer_gen12lp.cpp @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_stream/experimental_command_buffer.h" +#include "runtime/command_stream/experimental_command_buffer.inl" +#include "runtime/helpers/hw_helper.h" + +namespace NEO { +typedef TGLLPFamily GfxFamily; + +template void ExperimentalCommandBuffer::injectBufferStart(LinearStream &parentStream, size_t cmdBufferOffset); +template size_t ExperimentalCommandBuffer::getRequiredInjectionSize() noexcept; + +template size_t ExperimentalCommandBuffer::programExperimentalCommandBuffer(); +template size_t ExperimentalCommandBuffer::getTotalExperimentalSize() noexcept; + +template void ExperimentalCommandBuffer::addTimeStampPipeControl(); +template size_t ExperimentalCommandBuffer::getTimeStampPipeControlSize() noexcept; + +template void ExperimentalCommandBuffer::addExperimentalCommands(); +template size_t ExperimentalCommandBuffer::getExperimentalCommandsSize() noexcept; +} // namespace NEO diff --git a/runtime/gen12lp/gpgpu_walker_gen12lp.cpp b/runtime/gen12lp/gpgpu_walker_gen12lp.cpp new file mode 100644 index 0000000000..11f6dd3567 --- /dev/null +++ b/runtime/gen12lp/gpgpu_walker_gen12lp.cpp @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_queue/gpgpu_walker_bdw_plus.inl" +#include "runtime/command_queue/hardware_interface_bdw_plus.inl" +#include "runtime/gen12lp/hw_info.h" + +namespace NEO { + +template class HardwareInterface; + +template <> +void GpgpuWalkerHelper::adjustMiStoreRegMemMode(MI_STORE_REG_MEM *storeCmd) { + storeCmd->setMmioRemapEnable(true); +} + +template class GpgpuWalkerHelper; + +template struct EnqueueOperation; + +} // namespace NEO diff --git a/runtime/gen12lp/gtpin_setup_gen12lp.cpp b/runtime/gen12lp/gtpin_setup_gen12lp.cpp new file mode 100644 index 0000000000..b5a260172d --- /dev/null +++ b/runtime/gen12lp/gtpin_setup_gen12lp.cpp @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/gtpin/gtpin_hw_helper.h" +#include "runtime/gtpin/gtpin_hw_helper.inl" + +#include "ocl_igc_shared/gtpin/gtpin_ocl_interface.h" + +namespace NEO { + +extern GTPinHwHelper *gtpinHwHelperFactory[IGFX_MAX_CORE]; + +typedef TGLLPFamily Family; +static const auto gfxFamily = IGFX_GEN12LP_CORE; + +template <> +uint32_t GTPinHwHelperHw::getGenVersion() { + return gtpin::GTPIN_GEN_INVALID; +} + +template class GTPinHwHelperHw; + +struct GTPinEnableGen12LP { + GTPinEnableGen12LP() { + gtpinHwHelperFactory[gfxFamily] = >PinHwHelperHw::get(); + } +}; + +static GTPinEnableGen12LP gtpinEnable; + +} // namespace NEO diff --git a/runtime/gen12lp/hardware_commands_helper_gen12lp.cpp b/runtime/gen12lp/hardware_commands_helper_gen12lp.cpp new file mode 100644 index 0000000000..c8e783cf48 --- /dev/null +++ b/runtime/gen12lp/hardware_commands_helper_gen12lp.cpp @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "hardware_commands_helper_gen12lp.inl" + +#include "runtime/command_queue/command_queue.h" +#include "runtime/gen12lp/helpers_gen12lp.h" +#include "runtime/gen12lp/hw_cmds.h" +#include "runtime/helpers/hardware_commands_helper.h" +#include "runtime/helpers/hardware_commands_helper.inl" +#include "runtime/helpers/hardware_commands_helper_base.inl" + +namespace NEO { + +template <> +size_t HardwareCommandsHelper::getSizeRequiredCS(const Kernel *kernel) { + size_t size = 2 * sizeof(typename TGLLPFamily::MEDIA_STATE_FLUSH) + + sizeof(typename TGLLPFamily::MEDIA_INTERFACE_DESCRIPTOR_LOAD); + return size; +} + +template <> +bool HardwareCommandsHelper::doBindingTablePrefetch() { + return false; +} + +template <> +bool HardwareCommandsHelper::isPipeControlWArequired(const HardwareInfo &hwInfo) { + return (Gen12LPHelpers::pipeControlWaRequired(hwInfo.platform.eProductFamily)) && (hwInfo.platform.usRevId == REVISION_A0); +} + +template <> +bool HardwareCommandsHelper::isPipeControlPriorToPipelineSelectWArequired(const HardwareInfo &hwInfo) { + return (Gen12LPHelpers::pipeControlWaRequired(hwInfo.platform.eProductFamily)) && (hwInfo.platform.usRevId == REVISION_A0); +} + +template struct HardwareCommandsHelper; +} // namespace NEO diff --git a/runtime/gen12lp/helpers_gen12lp.cpp b/runtime/gen12lp/helpers_gen12lp.cpp new file mode 100644 index 0000000000..a994bcb775 --- /dev/null +++ b/runtime/gen12lp/helpers_gen12lp.cpp @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/gen12lp/helpers_gen12lp.h" + +#include "runtime/command_stream/command_stream_receiver.h" +#include "runtime/command_stream/command_stream_receiver_simulated_common_hw.h" + +namespace NEO { +namespace Gen12LPHelpers { +bool hdcFlushForPipeControlBeforeStateBaseAddressRequired(PRODUCT_FAMILY productFamily) { + return (productFamily == PRODUCT_FAMILY::IGFX_TIGERLAKE_LP); +} + +bool pipeControlWaRequired(PRODUCT_FAMILY productFamily) { + return (productFamily == PRODUCT_FAMILY::IGFX_TIGERLAKE_LP); +} + +bool imagePitchAlignmentWaRequired(PRODUCT_FAMILY productFamily) { + return (productFamily == PRODUCT_FAMILY::IGFX_TIGERLAKE_LP); +} + +void adjustCoherencyFlag(PRODUCT_FAMILY productFamily, bool &coherencyFlag) {} + +bool isLocalMemoryEnabled(const HardwareInfo &hwInfo) { + return false; +} + +void initAdditionalGlobalMMIO(const CommandStreamReceiver &commandStreamReceiver, AubMemDump::AubStream &stream) {} + +uint64_t getPPGTTAdditionalBits(GraphicsAllocation *graphicsAllocation) { + return 0; +} + +void adjustAubGTTData(const CommandStreamReceiver &commandStreamReceiver, AubGTTData &data) {} + +void setAdditionalPipelineSelectFields(void *pipelineSelectCmd, + const PipelineSelectArgs &pipelineSelectArgs, + const HardwareInfo &hwInfo) {} + +} // namespace Gen12LPHelpers +} // namespace NEO diff --git a/runtime/gen12lp/helpers_gen12lp.h b/runtime/gen12lp/helpers_gen12lp.h new file mode 100644 index 0000000000..a98ba88aef --- /dev/null +++ b/runtime/gen12lp/helpers_gen12lp.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once + +#include "hw_info.h" + +namespace AubMemDump { +struct AubStream; +} +struct AubGTTData; + +namespace NEO { +class CommandStreamReceiver; +class GraphicsAllocation; +struct PipelineSelectArgs; + +namespace Gen12LPHelpers { +bool hdcFlushForPipeControlBeforeStateBaseAddressRequired(PRODUCT_FAMILY productFamily); +bool pipeControlWaRequired(PRODUCT_FAMILY productFamily); +bool imagePitchAlignmentWaRequired(PRODUCT_FAMILY productFamily); +void adjustCoherencyFlag(PRODUCT_FAMILY productFamily, bool &coherencyFlag); +bool isLocalMemoryEnabled(const HardwareInfo &hwInfo); +void initAdditionalGlobalMMIO(const CommandStreamReceiver &commandStreamReceiver, AubMemDump::AubStream &stream); +uint64_t getPPGTTAdditionalBits(GraphicsAllocation *graphicsAllocation); +void adjustAubGTTData(const CommandStreamReceiver &commandStreamReceiver, AubGTTData &data); +void setAdditionalPipelineSelectFields(void *pipelineSelectCmd, + const PipelineSelectArgs &pipelineSelectArgs, + const HardwareInfo &hwInfo); +} // namespace Gen12LPHelpers +} // namespace NEO diff --git a/runtime/gen12lp/hw_cmds.h b/runtime/gen12lp/hw_cmds.h new file mode 100644 index 0000000000..485221c136 --- /dev/null +++ b/runtime/gen12lp/hw_cmds.h @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#ifdef SUPPORT_TGLLP +#include "hw_cmds_tgllp.h" +#endif diff --git a/runtime/gen12lp/hw_cmds_base.h b/runtime/gen12lp/hw_cmds_base.h new file mode 100644 index 0000000000..918274572c --- /dev/null +++ b/runtime/gen12lp/hw_cmds_base.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "core/helpers/debug_helpers.h" +#include "runtime/commands/bxml_generator_glue.h" +#include "runtime/gen12lp/hw_info.h" + +#include "igfxfmid.h" + +#include +#include + +template +struct CmdParse; +namespace NEO { + +struct GEN12LP { +#include "core/gen12lp/hw_cmds_generated.inl" +#include "core/gen12lp/hw_cmds_generated_patched.inl" + static constexpr uint32_t stateComputeModeForceNonCoherentMask = (((1 << 0) | (1 << 1)) << 3); +}; +struct TGLLPFamily : public GEN12LP { + using PARSE = CmdParse; + using GfxFamily = TGLLPFamily; + using WALKER_TYPE = GPGPU_WALKER; + using XY_COPY_BLT = typename GfxFamily::XY_SRC_COPY_BLT; + using MI_STORE_REGISTER_MEM_CMD = typename GfxFamily::MI_STORE_REGISTER_MEM; + static const GPGPU_WALKER cmdInitGpgpuWalker; + static const INTERFACE_DESCRIPTOR_DATA cmdInitInterfaceDescriptorData; + static const MEDIA_INTERFACE_DESCRIPTOR_LOAD cmdInitMediaInterfaceDescriptorLoad; + static const MEDIA_STATE_FLUSH cmdInitMediaStateFlush; + static const MI_BATCH_BUFFER_END cmdInitBatchBufferEnd; + static const MI_BATCH_BUFFER_START cmdInitBatchBufferStart; + static const PIPE_CONTROL cmdInitPipeControl; + static const STATE_COMPUTE_MODE cmdInitStateComputeMode; + static const MI_SEMAPHORE_WAIT cmdInitMiSemaphoreWait; + static const RENDER_SURFACE_STATE cmdInitRenderSurfaceState; + static const MI_LOAD_REGISTER_IMM cmdInitLoadRegisterImm; + static const MI_LOAD_REGISTER_REG cmdInitLoadRegisterReg; + static const MI_LOAD_REGISTER_MEM cmdInitLoadRegisterMem; + static const MI_STORE_DATA_IMM cmdInitStoreDataImm; + static const MI_STORE_REGISTER_MEM cmdInitStoreRegisterMem; + static const MI_NOOP cmdInitNoop; + static const MI_REPORT_PERF_COUNT cmdInitReportPerfCount; + static const MI_ATOMIC cmdInitAtomic; + static const PIPELINE_SELECT cmdInitPipelineSelect; + static const MI_ARB_CHECK cmdInitArbCheck; + static const MEDIA_VFE_STATE cmdInitMediaVfeState; + static const STATE_BASE_ADDRESS cmdInitStateBaseAddress; + static const MEDIA_SURFACE_STATE cmdInitMediaSurfaceState; + static const SAMPLER_STATE cmdInitSamplerState; + static const GPGPU_CSR_BASE_ADDRESS cmdInitGpgpuCsrBaseAddress; + static const STATE_SIP cmdInitStateSip; + static const BINDING_TABLE_STATE cmdInitBindingTableState; + static const MI_USER_INTERRUPT cmdInitUserInterrupt; + static const XY_SRC_COPY_BLT cmdInitXyCopyBlt; + static const MI_FLUSH_DW cmdInitMiFlushDw; + + static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) { + return cmdSetBaseFamily == IGFX_GEN8_CORE; + } +}; + +} // namespace NEO diff --git a/runtime/gen12lp/hw_cmds_tgllp.h b/runtime/gen12lp/hw_cmds_tgllp.h new file mode 100644 index 0000000000..1595a6c5f3 --- /dev/null +++ b/runtime/gen12lp/hw_cmds_tgllp.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "runtime/gen12lp/hw_cmds_base.h" +namespace NEO { + +struct TGLLP : public TGLLPFamily { + static const PLATFORM platform; + static const HardwareInfo hwInfo; + static FeatureTable featureTable; + static WorkaroundTable workaroundTable; + static const uint32_t threadsPerEu = 7; + static const uint32_t maxEuPerSubslice = 16; + static const uint32_t maxSlicesSupported = 1; + static const uint32_t maxSubslicesSupported = 6; + static const uint32_t maxDualSubslicesSupported = 12; + static const RuntimeCapabilityTable capabilityTable; + static void (*setupHardwareInfo)(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, const std::string &hwInfoConfig); + static void setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo); +}; +class TGLLP_1x6x16 : public TGLLP { + public: + static void setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable); + static const HardwareInfo hwInfo; + + private: + static GT_SYSTEM_INFO gtSystemInfo; +}; +} // namespace NEO diff --git a/runtime/gen12lp/hw_helper_gen12lp.cpp b/runtime/gen12lp/hw_helper_gen12lp.cpp new file mode 100644 index 0000000000..b2354d4472 --- /dev/null +++ b/runtime/gen12lp/hw_helper_gen12lp.cpp @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/aub/aub_helper_bdw_plus.inl" +#include "runtime/gen12lp/helpers_gen12lp.h" +#include "runtime/helpers/flat_batch_buffer_helper_hw.inl" +#include "runtime/helpers/hw_helper_bdw_plus.inl" + +#include "engine_node.h" + +namespace NEO { +typedef TGLLPFamily Family; + +template <> +void HwHelperHw::adjustDefaultEngineType(HardwareInfo *pHwInfo) { + if (!pHwInfo->featureTable.ftrCCSNode) { + pHwInfo->capabilityTable.defaultEngineType = aub_stream::ENGINE_RCS; + } +} + +template <> +uint32_t HwHelperHw::getComputeUnitsUsedForScratch(const HardwareInfo *pHwInfo) const { + /* For ICL+ maxThreadCount equals (EUCount * 8). + ThreadCount/EUCount=7 is no longer valid, so we have to force 8 in below formula. + This is required to allocate enough scratch space. */ + return pHwInfo->gtSystemInfo.MaxSubSlicesSupported * pHwInfo->gtSystemInfo.MaxEuPerSubSlice * 8; +} + +template <> +uint32_t HwHelperHw::getConfigureAddressSpaceMode() { + return 1u; +} + +template <> +bool HwHelperHw::isLocalMemoryEnabled(const HardwareInfo &hwInfo) const { + return Gen12LPHelpers::isLocalMemoryEnabled(hwInfo); +} + +template <> +bool HwHelperHw::isPageTableManagerSupported(const HardwareInfo &hwInfo) const { + return hwInfo.capabilityTable.ftrRenderCompressedBuffers || hwInfo.capabilityTable.ftrRenderCompressedImages; +} + +template <> +bool HwHelperHw::obtainRenderBufferCompressionPreference(const size_t size) const { + return false; +} + +template <> +void HwHelperHw::checkResourceCompatibility(Buffer *buffer, cl_int &errorCode) { + if (buffer->getGraphicsAllocation()->getAllocationType() == GraphicsAllocation::AllocationType::BUFFER_COMPRESSED) { + errorCode = CL_INVALID_MEM_OBJECT; + } +} + +template <> +void HwHelperHw::setCapabilityCoherencyFlag(const HardwareInfo *pHwInfo, bool &coherencyFlag) { + coherencyFlag = true; + if (pHwInfo->platform.eProductFamily == IGFX_TIGERLAKE_LP && pHwInfo->platform.usRevId == 0x0) { + //stepping A0 devices - turn off coherency + coherencyFlag = false; + } + + Gen12LPHelpers::adjustCoherencyFlag(pHwInfo->platform.eProductFamily, coherencyFlag); +} + +template <> +uint32_t HwHelperHw::getPitchAlignmentForImage(const HardwareInfo *hwInfo) { + if (Gen12LPHelpers::imagePitchAlignmentWaRequired(hwInfo->platform.eProductFamily)) { + auto stepping = hwInfo->platform.usRevId; + if (stepping == 0) { + return 64u; + } + return 4u; + } + return 4u; +} + +template <> +const std::vector HwHelperHw::getGpgpuEngineInstances() const { + constexpr std::array gpgpuEngineInstances = {{aub_stream::ENGINE_RCS, + aub_stream::ENGINE_RCS, // low priority + aub_stream::ENGINE_CCS}}; + return std::vector(gpgpuEngineInstances.begin(), gpgpuEngineInstances.end()); +}; + +template <> +void PipeControlHelper::addPipeControlWA(LinearStream &commandStream, const HardwareInfo &hwInfo) { + if (Gen12LPHelpers::pipeControlWaRequired(hwInfo.platform.eProductFamily)) { + auto stepping = hwInfo.platform.usRevId; + if (stepping == 0) { + auto pCmd = static_cast(commandStream.getSpace(sizeof(Family::PIPE_CONTROL))); + *pCmd = Family::cmdInitPipeControl; + pCmd->setCommandStreamerStallEnable(true); + } + } +} + +template class AubHelperHw; +template class HwHelperHw; +template class FlatBatchBufferHelperHw; +template struct PipeControlHelper; +} // namespace NEO diff --git a/runtime/gen12lp/hw_info.h b/runtime/gen12lp/hw_info.h new file mode 100644 index 0000000000..177b92e00e --- /dev/null +++ b/runtime/gen12lp/hw_info.h @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#ifdef SUPPORT_TGLLP +#include "hw_info_tgllp.h" +#endif diff --git a/runtime/gen12lp/hw_info_gen12lp.cpp b/runtime/gen12lp/hw_info_gen12lp.cpp new file mode 100644 index 0000000000..102d9b5ab3 --- /dev/null +++ b/runtime/gen12lp/hw_info_gen12lp.cpp @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#ifdef SUPPORT_TGLLP +#include "hw_info_tgllp.inl" +#endif + +namespace NEO { +const char *GfxFamilyMapper::name = "Gen12LP"; +} // namespace NEO diff --git a/runtime/gen12lp/hw_info_gen12lp.h b/runtime/gen12lp/hw_info_gen12lp.h new file mode 100644 index 0000000000..dcebd1662b --- /dev/null +++ b/runtime/gen12lp/hw_info_gen12lp.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "runtime/helpers/hw_info.h" + +namespace NEO { + +struct TGLLPFamily; + +template <> +struct GfxFamilyMapper { + typedef TGLLPFamily GfxFamily; + static const char *name; +}; +} // namespace NEO diff --git a/runtime/gen12lp/hw_info_tgllp.h b/runtime/gen12lp/hw_info_tgllp.h new file mode 100644 index 0000000000..ad56ecc35f --- /dev/null +++ b/runtime/gen12lp/hw_info_tgllp.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "hw_info_gen12lp.h" + +namespace NEO { + +struct TGLLP; + +template <> +struct HwMapper { + enum { gfxFamily = IGFX_GEN12LP_CORE }; + + static const char *abbreviation; + typedef GfxFamilyMapper(gfxFamily)>::GfxFamily GfxFamily; + typedef TGLLP GfxProduct; +}; +} // namespace NEO diff --git a/runtime/gen12lp/hw_info_tgllp.inl b/runtime/gen12lp/hw_info_tgllp.inl new file mode 100644 index 0000000000..f7ae8dd92f --- /dev/null +++ b/runtime/gen12lp/hw_info_tgllp.inl @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "core/memory_manager/memory_constants.h" +#include "runtime/aub_mem_dump/aub_services.h" +#include "runtime/gen12lp/hw_cmds.h" + +#include "engine_node.h" +#include "hw_info_tgllp.h" + +namespace NEO { + +const char *HwMapper::abbreviation = "tgllp"; + +bool isSimulationTGLLP(unsigned short deviceId) { + switch (deviceId) { + case IGEN12LP_GT1_MOB_DEVICE_F0_ID: + return true; + } + return false; +}; + +const PLATFORM TGLLP::platform = { + IGFX_TIGERLAKE_LP, + PCH_UNKNOWN, + IGFX_GEN12LP_CORE, + IGFX_GEN12LP_CORE, + PLATFORM_NONE, // default init + 0, // usDeviceID + 0, // usRevId. 0 sets the stepping to A0 + 0, // usDeviceID_PCH + 0, // usRevId_PCH + GTTYPE_UNDEFINED}; + +const RuntimeCapabilityTable TGLLP::capabilityTable{ + {0, 0, 0, false, false, false}, // kmdNotifyProperties + MemoryConstants::max64BitAppAddress, // gpuAddressSpace + 83.333, // defaultProfilingTimerResolution + MemoryConstants::pageSize, // requiredPreemptionSurfaceSize + &isSimulationTGLLP, // isSimulation + PreemptionMode::ThreadGroup, // defaultPreemptionMode + aub_stream::ENGINE_CCS, // defaultEngineType + 0, // maxRenderFrequency + 21, // clVersionSupport + CmdServicesMemTraceVersion::DeviceValues::Tgllp, // aubDeviceId + 1, // extraQuantityThreadsPerEU + 64, // slmSize + false, // blitterOperationsSupported + false, // ftrSupportsInteger64BitAtomics + false, // ftrSupportsFP64 + false, // ftrSupports64BitMath + true, // ftrSvm + true, // ftrSupportsCoherency + false, // ftrSupportsVmeAvcTextureSampler + false, // ftrSupportsVmeAvcPreemption + false, // ftrRenderCompressedBuffers + false, // ftrRenderCompressedImages + true, // instrumentationEnabled + true, // forceStatelessCompilationFor32Bit + true, // ftr64KBpages + "lp", // platformType + true, // sourceLevelDebuggerSupported + false, // supportsVme + false, // supportCacheFlushAfterWalker + true, // supportsImages + true // supportsDeviceEnqueue +}; + +WorkaroundTable TGLLP::workaroundTable = {}; +FeatureTable TGLLP::featureTable = {}; + +void TGLLP::setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo) { + FeatureTable *featureTable = &hwInfo->featureTable; + WorkaroundTable *workaroundTable = &hwInfo->workaroundTable; + + featureTable->ftrL3IACoherency = true; + featureTable->ftrPPGTT = true; + featureTable->ftrSVM = true; + featureTable->ftrIA32eGfxPTEs = true; + featureTable->ftrStandardMipTailFormat = true; + + featureTable->ftrTranslationTable = true; + featureTable->ftrUserModeTranslationTable = true; + featureTable->ftrTileMappedResource = true; + featureTable->ftrEnableGuC = true; + + featureTable->ftrFbc = true; + featureTable->ftrFbc2AddressTranslation = true; + featureTable->ftrFbcBlitterTracking = true; + featureTable->ftrFbcCpuTracking = true; + featureTable->ftrTileY = true; + + featureTable->ftrAstcHdr2D = true; + featureTable->ftrAstcLdr2D = true; + + workaroundTable->wa4kAlignUVOffsetNV12LinearSurface = true; + workaroundTable->waEnablePreemptionGranularityControlByUMD = true; + workaroundTable->waUntypedBufferCompression = true; +}; + +const HardwareInfo TGLLP_1x6x16::hwInfo = { + &TGLLP::platform, + &TGLLP::featureTable, + &TGLLP::workaroundTable, + &TGLLP_1x6x16::gtSystemInfo, + TGLLP::capabilityTable, +}; + +GT_SYSTEM_INFO TGLLP_1x6x16::gtSystemInfo = {0}; +void TGLLP_1x6x16::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) { + GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo; + gtSysInfo->EUCount = 96; + gtSysInfo->ThreadCount = 96 * TGLLP::threadsPerEu; + gtSysInfo->SliceCount = 1; + gtSysInfo->SubSliceCount = 6; + gtSysInfo->DualSubSliceCount = 6; + gtSysInfo->L3CacheSizeInKb = 2048; + gtSysInfo->L3BankCount = 8; + gtSysInfo->MaxFillRate = 16; + gtSysInfo->TotalVsThreads = 336; + gtSysInfo->TotalHsThreads = 336; + gtSysInfo->TotalDsThreads = 336; + gtSysInfo->TotalGsThreads = 336; + gtSysInfo->TotalPsThreadsWindowerRange = 64; + gtSysInfo->CsrSizeInMb = 8; + gtSysInfo->MaxEuPerSubSlice = TGLLP::maxEuPerSubslice; + gtSysInfo->MaxSlicesSupported = TGLLP::maxSlicesSupported; + gtSysInfo->MaxSubSlicesSupported = TGLLP::maxSubslicesSupported; + gtSysInfo->MaxDualSubSlicesSupported = TGLLP::maxDualSubslicesSupported; + gtSysInfo->IsL3HashModeEnabled = false; + gtSysInfo->IsDynamicallyPopulated = false; + + gtSysInfo->CCSInfo.IsValid = true; + gtSysInfo->CCSInfo.NumberOfCCSEnabled = 1; + gtSysInfo->CCSInfo.Instances.CCSEnableMask = 0b1; + + if (setupFeatureTableAndWorkaroundTable) { + setupFeatureAndWorkaroundTable(hwInfo); + } +}; + +const HardwareInfo TGLLP::hwInfo = TGLLP_1x6x16::hwInfo; + +void setupTGLLPHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, const std::string &hwInfoConfig) { + if (hwInfoConfig == "1x6x16") { + TGLLP_1x6x16::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable); + } else if (hwInfoConfig == "default") { + // Default config + TGLLP_1x6x16::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable); + } else { + UNRECOVERABLE_IF(true); + } +} + +void (*TGLLP::setupHardwareInfo)(HardwareInfo *, bool, const std::string &) = setupTGLLPHardwareInfoImpl; +} // namespace NEO diff --git a/runtime/gen12lp/image_gen12lp.cpp b/runtime/gen12lp/image_gen12lp.cpp new file mode 100644 index 0000000000..848029c407 --- /dev/null +++ b/runtime/gen12lp/image_gen12lp.cpp @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/gen12lp/hw_cmds.h" +#include "runtime/mem_obj/image.h" +#include "runtime/mem_obj/image.inl" + +namespace NEO { + +typedef TGLLPFamily Family; +static auto gfxCore = IGFX_GEN12LP_CORE; + +template +void ImageHw::setMediaSurfaceRotation(void *memory) { + using MEDIA_SURFACE_STATE = typename GfxFamily::MEDIA_SURFACE_STATE; + using SURFACE_FORMAT = typename MEDIA_SURFACE_STATE::SURFACE_FORMAT; + + auto surfaceState = reinterpret_cast(memory); + + surfaceState->setRotation(MEDIA_SURFACE_STATE::ROTATION_NO_ROTATION_OR_0_DEGREE); + surfaceState->setXOffset(0); + surfaceState->setYOffset(0); +} + +template +void ImageHw::setSurfaceMemoryObjectControlStateIndexToMocsTable(void *memory, uint32_t value) { + using MEDIA_SURFACE_STATE = typename GfxFamily::MEDIA_SURFACE_STATE; + using SURFACE_FORMAT = typename MEDIA_SURFACE_STATE::SURFACE_FORMAT; + + auto surfaceState = reinterpret_cast(memory); + + surfaceState->setSurfaceMemoryObjectControlStateIndexToMocsTables(value); +} +// clang-format off +#include "runtime/mem_obj/image_tgllp_plus.inl" +#include "runtime/mem_obj/image_factory_init.inl" +// clang-format on +} // namespace NEO diff --git a/runtime/gen12lp/linux/command_stream_receiver_gen12lp.cpp b/runtime/gen12lp/linux/command_stream_receiver_gen12lp.cpp new file mode 100644 index 0000000000..267406700a --- /dev/null +++ b/runtime/gen12lp/linux/command_stream_receiver_gen12lp.cpp @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_stream/command_stream_receiver_with_aub_dump.inl" +#include "runtime/os_interface/linux/device_command_stream.inl" +#include "runtime/os_interface/linux/drm_command_stream.inl" +#include "runtime/os_interface/linux/drm_command_stream_bdw_plus.inl" + +namespace NEO { + +template class DeviceCommandStreamReceiver; +template class DrmCommandStreamReceiver; +template class CommandStreamReceiverWithAUBDump>; +} // namespace NEO diff --git a/runtime/gen12lp/linux/hw_info_config_gen12lp.cpp b/runtime/gen12lp/linux/hw_info_config_gen12lp.cpp new file mode 100644 index 0000000000..c4258f497f --- /dev/null +++ b/runtime/gen12lp/linux/hw_info_config_gen12lp.cpp @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/os_interface/hw_info_config.inl" +#include "runtime/os_interface/hw_info_config_bdw_plus.inl" + +#ifdef SUPPORT_TGLLP +#include "hw_info_config_tgllp.inl" +#endif diff --git a/runtime/gen12lp/linux/hw_info_config_tgllp.inl b/runtime/gen12lp/linux/hw_info_config_tgllp.inl new file mode 100644 index 0000000000..c0599c2b13 --- /dev/null +++ b/runtime/gen12lp/linux/hw_info_config_tgllp.inl @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/helpers/hw_info.h" +#include "runtime/os_interface/hw_info_config.h" + +namespace NEO { + +template <> +int HwInfoConfigHw::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) { + if (nullptr == osIface) { + return 0; + } + + GT_SYSTEM_INFO *gtSystemInfo = &hwInfo->gtSystemInfo; + gtSystemInfo->SliceCount = 1; + return 0; +} + +template class HwInfoConfigHw; +} // namespace NEO diff --git a/runtime/gen12lp/preamble_gen12lp.cpp b/runtime/gen12lp/preamble_gen12lp.cpp new file mode 100644 index 0000000000..7b4bfab7b5 --- /dev/null +++ b/runtime/gen12lp/preamble_gen12lp.cpp @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_stream/csr_definitions.h" +#include "runtime/gen12lp/helpers_gen12lp.h" +#include "runtime/helpers/hardware_commands_helper.h" +#include "runtime/helpers/preamble_bdw_plus.inl" + +#include "reg_configs_common.h" + +namespace NEO { + +template <> +uint32_t PreambleHelper::getL3Config(const HardwareInfo &hwInfo, bool useSLM) { + uint32_t l3Config = 0; + + switch (hwInfo.platform.eProductFamily) { + case IGFX_TIGERLAKE_LP: + l3Config = getL3ConfigHelper(useSLM); + break; + default: + l3Config = getL3ConfigHelper(true); + } + return l3Config; +} + +template <> +void PreambleHelper::programPipelineSelect(LinearStream *pCommandStream, + const PipelineSelectArgs &pipelineSelectArgs, + const HardwareInfo &hwInfo) { + + using PIPELINE_SELECT = typename TGLLPFamily::PIPELINE_SELECT; + + if (HardwareCommandsHelper::isPipeControlPriorToPipelineSelectWArequired(hwInfo)) { + auto pipeControl = PipeControlHelper::addPipeControl(*pCommandStream, false); + pipeControl->setRenderTargetCacheFlushEnable(true); + } + + auto pCmd = (PIPELINE_SELECT *)pCommandStream->getSpace(sizeof(PIPELINE_SELECT)); + *pCmd = TGLLPFamily::cmdInitPipelineSelect; + + auto mask = pipelineSelectEnablePipelineSelectMaskBits | pipelineSelectMediaSamplerDopClockGateMaskBits; + + pCmd->setMaskBits(mask); + pCmd->setPipelineSelection(PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU); + pCmd->setMediaSamplerDopClockGateEnable(!pipelineSelectArgs.mediaSamplerRequired); + + Gen12LPHelpers::setAdditionalPipelineSelectFields(pCmd, pipelineSelectArgs, hwInfo); +} + +template <> +void PreambleHelper::addPipeControlBeforeVfeCmd(LinearStream *pCommandStream, const HardwareInfo *hwInfo) { + auto pipeControl = pCommandStream->getSpaceForCmd(); + *pipeControl = TGLLPFamily::cmdInitPipeControl; + pipeControl->setCommandStreamerStallEnable(true); + if (hwInfo->workaroundTable.waSendMIFLUSHBeforeVFE) { + if (hwInfo->capabilityTable.defaultEngineType != aub_stream::ENGINE_CCS) { + pipeControl->setRenderTargetCacheFlushEnable(true); + pipeControl->setDepthCacheFlushEnable(true); + } + pipeControl->setDcFlushEnable(true); + } +} + +template <> +void PreambleHelper::programL3(LinearStream *pCommandStream, uint32_t l3Config) { +} + +template <> +uint32_t PreambleHelper::getUrbEntryAllocationSize() { + return 1024u; +} + +// Explicitly instantiate PreambleHelper for TGLLP device family + +template struct PreambleHelper; +} // namespace NEO diff --git a/runtime/gen12lp/preemption_gen12lp.cpp b/runtime/gen12lp/preemption_gen12lp.cpp new file mode 100644 index 0000000000..dec7e50ad5 --- /dev/null +++ b/runtime/gen12lp/preemption_gen12lp.cpp @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_stream/preemption.h" +#include "runtime/gen12lp/hw_cmds.h" + +namespace NEO { + +typedef TGLLPFamily GfxFamily; + +template <> +size_t PreemptionHelper::getRequiredCmdStreamSize(PreemptionMode newPreemptionMode, PreemptionMode oldPreemptionMode) { + return 0; +} + +template <> +void PreemptionHelper::programCmdStream(LinearStream &cmdStream, PreemptionMode newPreemptionMode, + PreemptionMode oldPreemptionMode, GraphicsAllocation *preemptionCsr) { +} + +template <> +size_t PreemptionHelper::getRequiredPreambleSize(const Device &device) { + return 0; +} + +template <> +size_t PreemptionHelper::getRequiredStateSipCmdSize(const Device &device) { + return 0; +} + +template <> +void PreemptionHelper::programCsrBaseAddress(LinearStream &preambleCmdStream, Device &device, + const GraphicsAllocation *preemptionCsr) { +} + +template <> +void PreemptionHelper::programStateSip(LinearStream &preambleCmdStream, Device &device) { +} + +template <> +size_t PreemptionHelper::getPreemptionWaCsSize(const Device &device) { + return 0; +} + +template <> +void PreemptionHelper::applyPreemptionWaCmdsBegin(LinearStream *pCommandStream, const Device &device) { +} + +template <> +void PreemptionHelper::applyPreemptionWaCmdsEnd(LinearStream *pCommandStream, const Device &device) { +} + +template <> +void PreemptionHelper::programInterfaceDescriptorDataPreemption(INTERFACE_DESCRIPTOR_DATA *idd, PreemptionMode preemptionMode) { + using INTERFACE_DESCRIPTOR_DATA = typename GfxFamily::INTERFACE_DESCRIPTOR_DATA; + if (preemptionMode == PreemptionMode::MidThread) { + idd->setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_DISABLE); + } else { + idd->setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_ENABLE); + } +} +} // namespace NEO diff --git a/runtime/gen12lp/reg_configs.h b/runtime/gen12lp/reg_configs.h new file mode 100644 index 0000000000..d0e765c03a --- /dev/null +++ b/runtime/gen12lp/reg_configs.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "runtime/helpers/preamble.h" + +namespace NEO { + +struct TGLLPFamily; +template <> +struct L3CNTLREGConfig { + static const uint32_t valueForSLM = 0xD0000020u; + static const uint32_t valueForNoSLM = 0xD0000020u; +}; + +template <> +struct L3CNTLRegisterOffset { + static const uint32_t registerOffset = 0xB134; + static const uint32_t registerOffsetCCS = 0xB234; +}; +} // namespace NEO diff --git a/runtime/gen12lp/sampler_gen12lp.cpp b/runtime/gen12lp/sampler_gen12lp.cpp new file mode 100644 index 0000000000..847db5e00c --- /dev/null +++ b/runtime/gen12lp/sampler_gen12lp.cpp @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/gen12lp/hw_cmds_base.h" +using Family = NEO::TGLLPFamily; +constexpr static auto gfxCore = IGFX_GEN12LP_CORE; +#include "runtime/sampler/sampler_tgllp_plus.inl" diff --git a/runtime/gen12lp/scheduler_definitions.h b/runtime/gen12lp/scheduler_definitions.h new file mode 100644 index 0000000000..6542014017 --- /dev/null +++ b/runtime/gen12lp/scheduler_definitions.h @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#ifdef _DUMMY_WA +#endif +//POPULATE DEFINES WITH CORRECT VALUES FOR GEN12LP +#define SCHEDULER_COMPILATION_SIZE 8 + +#define SIZEOF_INTERFACE_DESCRIPTOR_DATA_G12LP 32 + +#define NUMBER_OF_INERFACE_DESCRIPTORS 64 +#define IDT_BREAKDOWN (NUMBER_OF_INERFACE_DESCRIPTORS - 2) + +#define MAX_WKG_SIZE 448 + +#define INTERFACE_DESCRIPTOR_TABLE_SIZE_G12LP (NUMBER_OF_INERFACE_DESCRIPTORS * SIZEOF_INTERFACE_DESCRIPTOR_DATA_G12LP) +#define SIZEOF_COLOR_CALCULATOR_STATE_G12LP 0xC0 +#define INTERFACE_DESCRIPTOR_TABLE_START_ADDRESS_G12LP SIZEOF_COLOR_CALCULATOR_STATE_G12LP +#define OCLRT_SIZEOF_SAMPLER_STATE_G12LP (16) + +#define SIZEOF_COLOR_CALCULATOR_STATE SIZEOF_COLOR_CALCULATOR_STATE_G12LP +#define SIZEOF_INTERFACE_DESCRIPTOR_DATA SIZEOF_INTERFACE_DESCRIPTOR_DATA_G12LP +#define INTERFACE_DESCRIPTOR_TABLE_SIZE INTERFACE_DESCRIPTOR_TABLE_SIZE_G12LP +#define INTERFACE_DESCRIPTOR_TABLE_START_ADDRESS INTERFACE_DESCRIPTOR_TABLE_START_ADDRESS_G12LP +#define OCLRT_SIZEOF_SAMPLER_STATE OCLRT_SIZEOF_SAMPLER_STATE_G12LP + +#define SECOND_LEVEL_BUFFER_SPACE_FOR_EACH_ENQUEUE (SECOND_LEVEL_BUFFER_SPACE_FOR_EACH_ENQUEUE_GEN12LP) +#define SECOND_LEVEL_BUFFER_NUMBER_OF_ENQUEUES (SECOND_LEVEL_BUFFER_NUMBER_OF_ENQUEUES_GEN12LP) + +//#define OCLRT_MEDIA_VFE_STATE_OFFSET ( MEDIA_STATE_FLUSH_INITIAL_OFFSET + OCLRT_SIZEOF_MSFLUSH_DWORD ) +#define OCLRT_MEDIA_VFE_STATE_OFFSET (0) +//address is QWORD in size and starts on DWORD 1 +#define MEDIA_VFE_STATE_ADDRESS_OFFSET (OCLRT_MEDIA_VFE_STATE_OFFSET + 1) + +// DWORD OFFSET +#define MEDIA_STATE_FLUSH_INITIAL_OFFSET 0 +//bits 0-5 of 1st DWORD +#define MEDIA_STATE_FLUSH_INITIAL_INTERFACE_DESCRIPTOR_OFFSET (MEDIA_STATE_FLUSH_INITIAL_OFFSET + 1) + +#define MI_ARB_CHECK_AFTER_MEDIA_STATE_FLUSH_INITIAL_OFFSET 0 + +#define MI_ATOMIC_CMD_OFFSET 0 + +#define MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET (MEDIA_STATE_FLUSH_INITIAL_OFFSET + OCLRT_SIZEOF_MSFLUSH_DWORD) +// DWORD OFFSET of InterfaceDescriptor Length +// bits 0 - 16 +#define MEDIA_INTERFACE_DESCRIPTOR_LOAD_INTERFACEDESCRIPTORLENGTH_OFFSET (MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET + 2) +// DWORD OFFSET of Interface Descriptor Start Address +#define MEDIA_INTERFACE_DESCRIPTOR_LOAD_INTERFACEDESCRIPTORSTARTADDRESS_OFFSET (MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET + 3) + +#define PIPE_CONTROL_FOR_TIMESTAMP_START_OFFSET (MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET + OCLRT_SIZEOF_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DEVICE_CMD_DWORD_OFFSET) + +#define INTERFACE_DESCRIPTOR_SAMPLER_STATE_TABLE_DWORD 3 +#define INTERFACE_DESCRIPTOR_BINDING_TABLE_POINTER_DWORD 4 +#define INTERFACE_DESCRIPTOR_CONSTANT_URB_ENTRY_READ_OFFSET 5 +#define INTERFACE_DESCRIPTOR_HWTHREADS_NUMBER_DWORD 6 +#define INTERFACE_DESCRIPTOR_SLMSIZE_DWORD 6 +#define INTERFACE_DESCRIPTOR_HWTHREADS_UPPER_BIT 9 + +#define SAMPLER_STATE_INDIRECT_STATE_MASK (0x7FFFFC0) +#define SAMPLER_STATE_BORDER_COLOR_MASK (0xFFFFFFE0) +#define SAMPLER_STATE_DESCRIPTOR_BORDER_COLOR_POINTER_DWORD 2 + +#define GPGPU_WALKER_OFFSET (PIPE_CONTROL_FOR_TIMESTAMP_START_OFFSET + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G12LP_DWORD_OFFSET) + +// DWORD OFFSET of the Interface Descriptor Offset for GPGPU_WALKER +// bits 0 - 5 +#define GPGPU_WALKER_INTERFACE_DESCRIPTOR_ID_OFFSET (GPGPU_WALKER_OFFSET + 1) +// DWORD OFFSET of the Indirect data length Offset for GPGPU_WALKER +// bits 0 - 16 +#define GPGPU_WALKER_INDIRECT_DATA_LENGTH_OFFSET (GPGPU_WALKER_OFFSET + 2) +// DWORD OFFSET of the Indirect Start Address for GPGPU_WALKER +#define GPGPU_WALKER_INDIRECT_START_ADDRESS_OFFSET (GPGPU_WALKER_OFFSET + 3) +// DWORD OFFSET of the Thread Width Counter Maximum for GPGPU_WALKER +// bits 0 - 5 +#define GPGPU_WALKER_THREAD_WIDTH_DWORD (GPGPU_WALKER_OFFSET + 4) +// DWORD OFFSET of the Thread Height Counter Maximum for GPGPU_WALKER +// bits 8 - 13 +#define GPGPU_WALKER_THREAD_HEIGHT_DWORD (GPGPU_WALKER_OFFSET + 4) +// DWORD OFFSET of the Thread Depth Counter Maximum for GPGPU_WALKER +// bits 16 - 21 +#define GPGPU_WALKER_THREAD_DEPTH_DWORD (GPGPU_WALKER_OFFSET + 4) +// DWORD OFFSET of the SIMD Size for GPGPU_WALKER +// bits 30 - 31 +#define GPGPU_WALKER_SIMDSIZE_DWORD (GPGPU_WALKER_OFFSET + 4) +// DWORD OFFSET of the Starting in X pos for GPGPU_WALKER +//bits 0 - 31 +#define GPGPU_WALKER_GROUP_ID_START_X (GPGPU_WALKER_OFFSET + 5) +// DWORD OFFSET of the X Dimension for GPGPU_WALKER +#define GPGPU_WALKER_XDIM_DWORD (GPGPU_WALKER_OFFSET + 7) +// DWORD OFFSET of the Starting in Y pos for GPGPU_WALKER +//bits 0 - 31 +#define GPGPU_WALKER_GROUP_ID_START_Y (GPGPU_WALKER_OFFSET + 8) +// DWORD OFFSET of the Y Dimension for GPGPU_WALKER +#define GPGPU_WALKER_YDIM_DWORD (GPGPU_WALKER_OFFSET + 10) +// DWORD OFFSET of the Starting in Z pos for GPGPU_WALKER +//bits 0 - 31 +#define GPGPU_WALKER_GROUP_ID_START_Z (GPGPU_WALKER_OFFSET + 11) +// DWORD OFFSET of the X Dimension for GPGPU_WALKER +#define GPGPU_WALKER_ZDIM_DWORD (GPGPU_WALKER_OFFSET + 12) +// DWORD OFFSET of the Right or X Mask for GPGPU_WALKER +#define GPGPU_WALKER_XMASK_DWORD (GPGPU_WALKER_OFFSET + 13) +// DWORD OFFSET of the Bottom or Y Mask for GPGPU_WALKER +#define GPGPU_WALKER_YMASK_DWORD (GPGPU_WALKER_OFFSET + 14) + +#define MEDIA_STATE_FLUSH_OFFSET (GPGPU_WALKER_OFFSET + OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G12LP_DWORD_OFFSET) +//bits 0-5 of 1st DWORD of M_S_F command +#define MEDIA_STATE_FLUSH_INTERFACE_DESCRIPTOR_OFFSET (MEDIA_STATE_FLUSH_OFFSET + 1) + +#define PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET (MEDIA_STATE_FLUSH_OFFSET + OCLRT_SIZEOF_MSFLUSH_DWORD) +#define PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET_TO_PATCH (PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET) +#define PIPE_CONTROL_POST_SYNC_DWORD 1 +#define PIPE_CONTROL_POST_SYNC_START_BIT 14 +#define PIPE_CONTROL_POST_SYNC_END_BIT 15 +#define PIPE_CONTROL_GENERATE_TIME_STAMP 3 +#define PIPE_CONTROL_NO_POSTSYNC_OPERATION 0 +#define PIPE_CONTROL_ADDRESS_FIELD_DWORD 2 +#define PIPE_CONTROL_PROFILING_START_TIMESTAMP_ADDRESS_OFFSET (PIPE_CONTROL_FOR_TIMESTAMP_START_OFFSET + PIPE_CONTROL_ADDRESS_FIELD_DWORD) //DWORD 2 +#define PIPE_CONTROL_GRAPHICS_ADDRESS_START_BIT 2 +#define PIPE_CONTROL_GRAPHICS_ADDRESS_END_BIT 31 +#define PIPE_CONTROL_GRAPHICS_ADDRESS_HIGH_START_BIT 0 +#define PIPE_CONTROL_GRAPHICS_ADDRESS_HIGH_END_BIT 15 + +#define PIPE_CONTROL_TIME_STAMP_DWORD0 0x7A000004 +#define PIPE_CONTROL_TIME_STAMP_DWORD1 0x0010C4A4 + +#define PIPE_CONTROL_CSTALL_DWORD0 0x7A000004 +#define PIPE_CONTROL_CSTALL_DWORD1 0x001004A4 + +#define PIPE_CONTROL_TAG_WRITE_DWORD0 0x7A000004 +#define PIPE_CONTROL_TAG_WRITE_DWORD1 0x001044A4 + +// the value of g_cInitMiBatchBufferStartCmdG12 DWORD0 +#define OCLRT_BATCH_BUFFER_BEGIN_CMD_DWORD0 (0x18800101) + +#if defined WA_LRI_COMMANDS_EXIST +#define IMM_LOAD_REGISTER_FOR_ENABLE_PREEMPTION_OFFSET (PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G12LP_DWORD_OFFSET + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G12LP_DWORD_OFFSET) +#endif + +#define OCLRT_LOAD_REGISTER_IMM_CMD 0x11000001 +#define CTXT_PREMP_DBG_ADDRESS_VALUE 0x2248 +#define CTXT_PREMP_ON_MI_ARB_CHECK_ONLY 0x00000100 +#define CTXT_PREMP_DEFAULT_VALUE 0x0 + +#define IMM_LOAD_REGISTER_ADDRESS_DWORD_OFFSET 1 +#define IMM_LOAD_REGISTER_VALUE_DWORD_OFFSET 2 diff --git a/runtime/gen12lp/scheduler_igdrcl_built_in.inl b/runtime/gen12lp/scheduler_igdrcl_built_in.inl new file mode 100644 index 0000000000..b72b059e86 --- /dev/null +++ b/runtime/gen12lp/scheduler_igdrcl_built_in.inl @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#ifdef _DUMMY_WA +#endif + +uint GetPatchValueForSLMSize(uint slMsize) { + //todo: veryfy this optimization : + //return ( SLMSize == 0 ) ? 0 : max( 33 - clz( ( SLMSize - 1 ) >> 10 ), 7 ); + + uint PatchValue = 0; + if (slMsize == 0) { + PatchValue = 0; + } else if (slMsize <= (1 * 1024)) { + PatchValue = 1; + } else if (slMsize <= (2 * 1024)) { + PatchValue = 2; + } else if (slMsize <= (4 * 1024)) { + PatchValue = 3; + } else if (slMsize <= (8 * 1024)) { + PatchValue = 4; + } else if (slMsize <= (16 * 1024)) { + PatchValue = 5; + } else if (slMsize <= (32 * 1024)) { + PatchValue = 6; + } else if (slMsize <= (64 * 1024)) { + PatchValue = 7; + } + return PatchValue; +} + +//on SKL we have pipe control in pairs, therefore when we NOOP we need to do this for both pipe controls +void NOOPCSStallPipeControl(__global uint *secondaryBatchBuffer, uint dwordOffset, uint pipeControlOffset) { + dwordOffset += pipeControlOffset; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; +} + +//on SKL+ with mid thread preemption we need to have 2 pipe controls instead of 1 any time we do post sync operation +void PutCSStallPipeControl(__global uint *secondaryBatchBuffer, uint dwordOffset, uint pipeControlOffset) { + dwordOffset += pipeControlOffset; + //first pipe control doing CS stall + secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD1; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + //second pipe control , doing actual timestamp write + secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD1; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; + secondaryBatchBuffer[dwordOffset] = 0; + dwordOffset++; +} diff --git a/runtime/gen12lp/state_base_address_gen12lp.cpp b/runtime/gen12lp/state_base_address_gen12lp.cpp new file mode 100644 index 0000000000..04e9579c71 --- /dev/null +++ b/runtime/gen12lp/state_base_address_gen12lp.cpp @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/helpers/state_base_address.h" +#include "runtime/helpers/state_base_address_bdw_plus.inl" + +namespace NEO { +template struct StateBaseAddressHelper; +} diff --git a/runtime/gen12lp/tbx_command_stream_receiver_gen12lp.cpp b/runtime/gen12lp/tbx_command_stream_receiver_gen12lp.cpp new file mode 100644 index 0000000000..6423489b3f --- /dev/null +++ b/runtime/gen12lp/tbx_command_stream_receiver_gen12lp.cpp @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "core/memory_manager/memory_pool.h" +#include "runtime/aub_mem_dump/aub_mem_dump.h" +#include "runtime/command_stream/command_stream_receiver_with_aub_dump.inl" +#include "runtime/command_stream/tbx_command_stream_receiver_hw.h" +#include "runtime/command_stream/tbx_command_stream_receiver_hw.inl" +#include "runtime/gen12lp/hw_cmds.h" +#include "runtime/helpers/array_count.h" +#include "runtime/helpers/base_object.h" + +namespace NEO { +typedef TGLLPFamily Family; +static auto gfxCore = IGFX_GEN12LP_CORE; + +template <> +uint32_t TbxCommandStreamReceiverHw::getMaskAndValueForPollForCompletion() const { + return 0x80; +} + +template <> +bool TbxCommandStreamReceiverHw::getpollNotEqualValueForPollForCompletion() const { + return true; +} + +template <> +void populateFactoryTable>() { + extern TbxCommandStreamReceiverCreateFunc tbxCommandStreamReceiverFactory[IGFX_MAX_CORE]; + UNRECOVERABLE_IF(!isInRange(gfxCore, tbxCommandStreamReceiverFactory)); + tbxCommandStreamReceiverFactory[gfxCore] = TbxCommandStreamReceiverHw::create; +} + +template class TbxCommandStreamReceiverHw; +template class CommandStreamReceiverWithAUBDump>; +} // namespace NEO diff --git a/runtime/gen12lp/windows/command_stream_receiver_gen12lp.cpp b/runtime/gen12lp/windows/command_stream_receiver_gen12lp.cpp new file mode 100644 index 0000000000..d46eb3a579 --- /dev/null +++ b/runtime/gen12lp/windows/command_stream_receiver_gen12lp.cpp @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_stream/command_stream_receiver_with_aub_dump.inl" +#include "runtime/os_interface/windows/device_command_stream.inl" +#include "runtime/os_interface/windows/wddm_device_command_stream.inl" + +namespace NEO { + +template class DeviceCommandStreamReceiver; +template class WddmCommandStreamReceiver; +template class CommandStreamReceiverWithAUBDump>; +} // namespace NEO diff --git a/runtime/gen12lp/windows/gmm_callbacks_gen12lp.cpp b/runtime/gen12lp/windows/gmm_callbacks_gen12lp.cpp new file mode 100644 index 0000000000..16dd49f0e5 --- /dev/null +++ b/runtime/gen12lp/windows/gmm_callbacks_gen12lp.cpp @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/gen12lp/hw_cmds.h" +#include "runtime/helpers/gmm_callbacks_tgllp_plus.inl" + +using namespace NEO; + +template struct DeviceCallbacks; +template struct TTCallbacks; diff --git a/runtime/gen12lp/windows/hw_info_config_gen12lp.cpp b/runtime/gen12lp/windows/hw_info_config_gen12lp.cpp new file mode 100644 index 0000000000..bc3c25daed --- /dev/null +++ b/runtime/gen12lp/windows/hw_info_config_gen12lp.cpp @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/helpers/hw_info.h" +#include "runtime/os_interface/debug_settings_manager.h" +#include "runtime/os_interface/hw_info_config.h" +#include "runtime/os_interface/hw_info_config.inl" +#include "runtime/os_interface/hw_info_config_bdw_plus.inl" + +namespace NEO { + +#ifdef SUPPORT_TGLLP +template <> +int HwInfoConfigHw::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) { + hwInfo->capabilityTable.ftrRenderCompressedImages = hwInfo->featureTable.ftrE2ECompression; + hwInfo->capabilityTable.ftrRenderCompressedBuffers = hwInfo->featureTable.ftrE2ECompression; + + return 0; +} + +template <> +void HwInfoConfigHw::adjustPlatformForProductFamily(HardwareInfo *hwInfo) { + PLATFORM *platform = &hwInfo->platform; + platform->eRenderCoreFamily = IGFX_GEN12LP_CORE; + platform->eDisplayCoreFamily = IGFX_GEN12LP_CORE; +} + +template class HwInfoConfigHw; +#endif + +} // namespace NEO diff --git a/runtime/gen_common/aub_mapper.h b/runtime/gen_common/aub_mapper.h index 6ae5c453c3..612828aab9 100644 --- a/runtime/gen_common/aub_mapper.h +++ b/runtime/gen_common/aub_mapper.h @@ -15,3 +15,6 @@ #ifdef SUPPORT_GEN11 #include "runtime/gen11/aub_mapper.h" #endif +#ifdef SUPPORT_GEN12LP +#include "runtime/gen12lp/aub_mapper.h" +#endif diff --git a/runtime/gen_common/hw_cmds.h b/runtime/gen_common/hw_cmds.h index 1e1e46d0ea..a4812eb862 100644 --- a/runtime/gen_common/hw_cmds.h +++ b/runtime/gen_common/hw_cmds.h @@ -15,3 +15,6 @@ #ifdef SUPPORT_GEN11 #include "runtime/gen11/hw_cmds.h" #endif +#ifdef SUPPORT_GEN12LP +#include "runtime/gen12lp/hw_cmds.h" +#endif diff --git a/runtime/gen_common/reg_configs/reg_configs_common.h b/runtime/gen_common/reg_configs/reg_configs_common.h index f0fffcf5df..a25680dfa9 100644 --- a/runtime/gen_common/reg_configs/reg_configs_common.h +++ b/runtime/gen_common/reg_configs/reg_configs_common.h @@ -15,6 +15,9 @@ #ifdef SUPPORT_GEN11 #include "runtime/gen11/reg_configs.h" #endif +#ifdef SUPPORT_GEN12LP +#include "runtime/gen12lp/reg_configs.h" +#endif #include namespace NEO { diff --git a/runtime/helpers/CMakeLists.txt b/runtime/helpers/CMakeLists.txt index 78cd5380c9..ed879f4e70 100644 --- a/runtime/helpers/CMakeLists.txt +++ b/runtime/helpers/CMakeLists.txt @@ -101,6 +101,7 @@ list(APPEND RUNTIME_SRCS_HELPERS_BASE ${NEO_CORE_HELPERS}) set(RUNTIME_SRCS_HELPERS_WINDOWS ${CMAKE_CURRENT_SOURCE_DIR}/gmm_callbacks.h ${CMAKE_CURRENT_SOURCE_DIR}/gmm_callbacks.inl + ${CMAKE_CURRENT_SOURCE_DIR}/gmm_callbacks_tgllp_plus.inl ${CMAKE_CURRENT_SOURCE_DIR}/windows/kmd_notify_properties_windows.cpp ${CMAKE_CURRENT_SOURCE_DIR}/windows/gl_helper.h ) diff --git a/runtime/helpers/gmm_callbacks_tgllp_plus.inl b/runtime/helpers/gmm_callbacks_tgllp_plus.inl new file mode 100644 index 0000000000..3a85d3b951 --- /dev/null +++ b/runtime/helpers/gmm_callbacks_tgllp_plus.inl @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_stream/aub_command_stream_receiver_hw.h" +#include "runtime/command_stream/command_stream_receiver_hw.h" +#include "runtime/command_stream/command_stream_receiver_with_aub_dump.h" +#include "runtime/helpers/gmm_callbacks.h" +#include "runtime/helpers/hw_helper.h" +#include "runtime/os_interface/windows/wddm_device_command_stream.h" + +namespace NEO { + +template +long __stdcall DeviceCallbacks::notifyAubCapture(void *csrHandle, uint64_t gfxAddress, size_t gfxSize, bool allocate) { + auto csr = reinterpret_cast *>(csrHandle); + + if (DebugManager.flags.SetCommandStreamReceiver.get() == CSR_HW_WITH_AUB) { + auto csrWithAub = static_cast> *>(csr); + auto aubCsr = static_cast *>(csrWithAub->aubCSR.get()); + if (allocate) { + AllocationView externalAllocation(gfxAddress, gfxSize); + aubCsr->makeResidentExternal(externalAllocation); + } else { + aubCsr->makeNonResidentExternal(gfxAddress); + } + } + + return 1; +} + +template +int __stdcall TTCallbacks::writeL3Address(void *queueHandle, uint64_t l3GfxAddress, uint64_t regOffset) { + auto csr = reinterpret_cast *>(queueHandle); + + auto lri1 = LriHelper::program(&csr->getCS(0), + static_cast(regOffset & 0xFFFFFFFF), + static_cast(l3GfxAddress & 0xFFFFFFFF)); + lri1->setMmioRemapEnable(true); + + auto lri2 = LriHelper::program(&csr->getCS(0), + static_cast(regOffset >> 32), + static_cast(l3GfxAddress >> 32)); + lri2->setMmioRemapEnable(true); + + return 1; +} + +} // namespace NEO diff --git a/runtime/mem_obj/CMakeLists.txt b/runtime/mem_obj/CMakeLists.txt index 6a7c901e3e..388a869805 100644 --- a/runtime/mem_obj/CMakeLists.txt +++ b/runtime/mem_obj/CMakeLists.txt @@ -14,6 +14,7 @@ set(RUNTIME_SRCS_MEM_OBJ ${CMAKE_CURRENT_SOURCE_DIR}/image.cpp ${CMAKE_CURRENT_SOURCE_DIR}/image.h ${CMAKE_CURRENT_SOURCE_DIR}/image.inl + ${CMAKE_CURRENT_SOURCE_DIR}/image_tgllp_plus.inl ${CMAKE_CURRENT_SOURCE_DIR}/image_factory_init.inl ${CMAKE_CURRENT_SOURCE_DIR}/map_operations_handler.cpp ${CMAKE_CURRENT_SOURCE_DIR}/map_operations_handler.h diff --git a/runtime/mem_obj/image_tgllp_plus.inl b/runtime/mem_obj/image_tgllp_plus.inl new file mode 100644 index 0000000000..89a9d5082d --- /dev/null +++ b/runtime/mem_obj/image_tgllp_plus.inl @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +template <> +void ImageHw::setClearColorParams(Family::RENDER_SURFACE_STATE *surfaceState, const Gmm *gmm) { + if (gmm->gmmResourceInfo->getResourceFlags()->Gpu.IndirectClearColor) { + surfaceState->setClearValueAddressEnable(true); + + uint64_t clearColorAddress = GmmHelper::decanonize(surfaceState->getSurfaceBaseAddress() + + gmm->gmmResourceInfo->getUnifiedAuxSurfaceOffset(GMM_UNIFIED_AUX_TYPE::GMM_AUX_CC)); + surfaceState->setClearColorAddress(static_cast(clearColorAddress & 0xFFFFFFFFULL)); + surfaceState->setClearColorAddressHigh(static_cast(clearColorAddress >> 32)); + } +} + +template <> +void ImageHw::setAuxParamsForMCSCCS(RENDER_SURFACE_STATE *surfaceState, Gmm *gmm) { + surfaceState->setAuxiliarySurfaceMode(AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_MCS_LCE); +} + +template <> +void ImageHw::setFlagsForMediaCompression(RENDER_SURFACE_STATE *surfaceState, Gmm *gmm) { + if (gmm->gmmResourceInfo->getResourceFlags()->Info.MediaCompressed) { + surfaceState->setAuxiliarySurfaceMode(AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_NONE); + surfaceState->setMemoryCompressionEnable(true); + } else { + surfaceState->setMemoryCompressionEnable(false); + } +} diff --git a/runtime/mem_obj/mem_obj_helper.cpp b/runtime/mem_obj/mem_obj_helper.cpp index 54e685234c..b81f5a344b 100644 --- a/runtime/mem_obj/mem_obj_helper.cpp +++ b/runtime/mem_obj/mem_obj_helper.cpp @@ -12,7 +12,7 @@ namespace NEO { bool MemObjHelper::isSuitableForRenderCompression(bool renderCompressed, const MemoryPropertiesFlags &properties, ContextType contextType, bool preferCompression) { - return renderCompressed; + return renderCompressed && preferCompression; } bool MemObjHelper::validateExtraMemoryProperties(const MemoryProperties &properties) { diff --git a/runtime/os_interface/debug_variables_base.inl b/runtime/os_interface/debug_variables_base.inl index 5bceb6b36e..db074b735e 100644 --- a/runtime/os_interface/debug_variables_base.inl +++ b/runtime/os_interface/debug_variables_base.inl @@ -102,6 +102,7 @@ DECLARE_DEBUG_VARIABLE(bool, EnablePassInlineData, false, "Enable passing of inl DECLARE_DEBUG_VARIABLE(bool, EnableFormatQuery, false, "Enable sharing format querying") DECLARE_DEBUG_VARIABLE(bool, AllowOpenFdOperations, false, "When enabled driver is allowed to call DRM_IOCTL_PRIME_HANDLE_TO_FD.") DECLARE_DEBUG_VARIABLE(bool, EnableFreeMemory, false, "Enable freeMemory in memory manager") +DECLARE_DEBUG_VARIABLE(bool, ForceSamplerLowFilteringPrecision, false, "Force Low Filtering Precision Sampler mode") DECLARE_DEBUG_VARIABLE(int32_t, EnableIntelVme, -1, "-1: default, 0: disabled, 1: Enables cl_intel_motion_estimation extension") DECLARE_DEBUG_VARIABLE(int32_t, EnableIntelAdvancedVme, -1, "-1: default, 0: disabled, 1: Enables cl_intel_advanced_motion_estimation extension") DECLARE_DEBUG_VARIABLE(int32_t, EnableBlitterOperationsForReadWriteBuffers, -1, "Use Blitter engine for Read/Write Buffers operations. -1: default, 0: disabled, 1: enabled") diff --git a/runtime/os_interface/linux/drm_engine_mapper.cpp b/runtime/os_interface/linux/drm_engine_mapper.cpp index cedd3e6972..37eeb08933 100644 --- a/runtime/os_interface/linux/drm_engine_mapper.cpp +++ b/runtime/os_interface/linux/drm_engine_mapper.cpp @@ -17,6 +17,8 @@ unsigned int DrmEngineMapper::engineNodeMap(aub_stream::EngineType engineType) { return I915_EXEC_RENDER; } else if (aub_stream::ENGINE_BCS == engineType) { return I915_EXEC_BLT; + } else if (aub_stream::ENGINE_CCS == engineType) { + return I915_EXEC_COMPUTE; } UNRECOVERABLE_IF(true); } diff --git a/runtime/os_interface/windows/wddm_engine_mapper.cpp b/runtime/os_interface/windows/wddm_engine_mapper.cpp index d69432ef49..c23296c4ab 100644 --- a/runtime/os_interface/windows/wddm_engine_mapper.cpp +++ b/runtime/os_interface/windows/wddm_engine_mapper.cpp @@ -16,6 +16,8 @@ GPUNODE_ORDINAL WddmEngineMapper::engineNodeMap(aub_stream::EngineType engineTyp return GPUNODE_3D; } else if (aub_stream::ENGINE_BCS == engineType) { return GPUNODE_BLT; + } else if (aub_stream::ENGINE_CCS == engineType) { + return GPUNODE_CCS0; } UNRECOVERABLE_IF(true); } diff --git a/runtime/sampler/CMakeLists.txt b/runtime/sampler/CMakeLists.txt index e7128cb1df..142a4577f5 100644 --- a/runtime/sampler/CMakeLists.txt +++ b/runtime/sampler/CMakeLists.txt @@ -10,6 +10,7 @@ set(RUNTIME_SRCS_SAMPLER ${CMAKE_CURRENT_SOURCE_DIR}/sampler.h ${CMAKE_CURRENT_SOURCE_DIR}/sampler.inl ${CMAKE_CURRENT_SOURCE_DIR}/sampler_factory_init.inl + ${CMAKE_CURRENT_SOURCE_DIR}/sampler_tgllp_plus.inl ) add_subdirectories() target_sources(${NEO_STATIC_LIB_NAME} PRIVATE ${RUNTIME_SRCS_SAMPLER}) diff --git a/runtime/sampler/sampler_tgllp_plus.inl b/runtime/sampler/sampler_tgllp_plus.inl new file mode 100644 index 0000000000..e23d72fb7e --- /dev/null +++ b/runtime/sampler/sampler_tgllp_plus.inl @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/os_interface/debug_settings_manager.h" +#include "runtime/sampler/sampler.h" +#include "runtime/sampler/sampler.inl" + +namespace NEO { + +using SAMPLER_STATE = typename Family::SAMPLER_STATE; + +template <> +void SamplerHw::appendSamplerStateParams(SAMPLER_STATE *state) { + if (DebugManager.flags.ForceSamplerLowFilteringPrecision.get()) { + state->setLowQualityFilter(SAMPLER_STATE::LOW_QUALITY_FILTER_ENABLE); + } +} + +#include "runtime/sampler/sampler_factory_init.inl" +} // namespace NEO diff --git a/third_party/aub_stream/headers/engine_node.h b/third_party/aub_stream/headers/engine_node.h index c1859e4fb3..453b88fa84 100644 --- a/third_party/aub_stream/headers/engine_node.h +++ b/third_party/aub_stream/headers/engine_node.h @@ -15,6 +15,7 @@ enum EngineType : uint32_t { ENGINE_BCS, ENGINE_VCS, ENGINE_VECS, + ENGINE_CCS, NUM_ENGINES }; diff --git a/third_party/uapi/drm/i915_drm.h b/third_party/uapi/drm/i915_drm.h index 31526bbacd..f8da59fd00 100644 --- a/third_party/uapi/drm/i915_drm.h +++ b/third_party/uapi/drm/i915_drm.h @@ -1034,6 +1034,7 @@ struct drm_i915_gem_execbuffer2 { #define I915_EXEC_BSD (2<<0) #define I915_EXEC_BLT (3<<0) #define I915_EXEC_VEBOX (4<<0) +#define I915_EXEC_COMPUTE (5<<0) /* Used for switching the constants addressing mode on gen4+ RENDER ring. * Gen6+ only supports relative addressing to dynamic state (default) and diff --git a/unit_tests/aub_tests/gen12lp/CMakeLists.txt b/unit_tests/aub_tests/gen12lp/CMakeLists.txt new file mode 100644 index 0000000000..5c53ef2482 --- /dev/null +++ b/unit_tests/aub_tests/gen12lp/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (C) 2019 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +if(TESTS_GEN12LP) + target_sources(igdrcl_aub_tests PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/aub_mem_dump_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/aub_tests_configuration_gen12lp.cpp + ${IGDRCL_SOURCE_DIR}/unit_tests/gen12lp/unit_test_helper_gen12lp.cpp + ) + add_subdirectories() +endif() diff --git a/unit_tests/aub_tests/gen12lp/aub_mem_dump_tests_gen12lp.cpp b/unit_tests/aub_tests/gen12lp/aub_mem_dump_tests_gen12lp.cpp new file mode 100644 index 0000000000..f0de75ac42 --- /dev/null +++ b/unit_tests/aub_tests/gen12lp/aub_mem_dump_tests_gen12lp.cpp @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "unit_tests/aub_tests/command_stream/aub_mem_dump_tests.h" +#include "unit_tests/fixtures/device_fixture.h" + +namespace NEO { + +using Gen12LPAubMemDumpTests = Test; + +GEN12LPTEST_F(Gen12LPAubMemDumpTests, simpleCCS) { + setupAUB(pDevice, aub_stream::ENGINE_CCS); +} + +} // namespace NEO diff --git a/unit_tests/aub_tests/gen12lp/aub_tests_configuration_gen12lp.cpp b/unit_tests/aub_tests/gen12lp/aub_tests_configuration_gen12lp.cpp new file mode 100644 index 0000000000..041bdcee3d --- /dev/null +++ b/unit_tests/aub_tests/gen12lp/aub_tests_configuration_gen12lp.cpp @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/gen_common/hw_cmds.h" +#include "unit_tests/aub_tests/aub_tests_configuration.h" + +using namespace NEO; + +template <> +AubTestsConfig GetAubTestsConfig() { + AubTestsConfig aubTestsConfig; + aubTestsConfig.testCanonicalAddress = false; + return aubTestsConfig; +} \ No newline at end of file diff --git a/unit_tests/aub_tests/gen12lp/batch_buffer/CMakeLists.txt b/unit_tests/aub_tests/gen12lp/batch_buffer/CMakeLists.txt new file mode 100644 index 0000000000..88c2884246 --- /dev/null +++ b/unit_tests/aub_tests/gen12lp/batch_buffer/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (C) 2019 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +target_sources(igdrcl_aub_tests PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/aub_batch_buffer_tests_gen12lp.h + ${CMAKE_CURRENT_SOURCE_DIR}/aub_batch_buffer_tests_gen12lp.cpp +) diff --git a/unit_tests/aub_tests/gen12lp/batch_buffer/aub_batch_buffer_tests_gen12lp.cpp b/unit_tests/aub_tests/gen12lp/batch_buffer/aub_batch_buffer_tests_gen12lp.cpp new file mode 100644 index 0000000000..5ba4b6ea55 --- /dev/null +++ b/unit_tests/aub_tests/gen12lp/batch_buffer/aub_batch_buffer_tests_gen12lp.cpp @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "aub_batch_buffer_tests_gen12lp.h" + +#include "core/memory_manager/graphics_allocation.h" +#include "core/unit_tests/helpers/debug_manager_state_restore.h" +#include "runtime/command_queue/command_queue_hw.h" +#include "runtime/event/event.h" +#include "runtime/helpers/hardware_commands_helper.h" +#include "runtime/mem_obj/buffer.h" +#include "runtime/utilities/tag_allocator.h" +#include "test.h" +#include "unit_tests/aub_tests/command_stream/aub_command_stream_fixture.h" +#include "unit_tests/aub_tests/fixtures/hello_world_fixture.h" +#include "unit_tests/fixtures/device_fixture.h" +#include "unit_tests/mocks/mock_context.h" +#include "unit_tests/mocks/mock_device.h" + +using Gen12LPAubBatchBufferTests = Test; +using Gen12LPTimestampTests = Test>; + +static constexpr auto gpuBatchBufferAddr = 0x400400001000; // 47-bit GPU address + +GEN12LPTEST_F(Gen12LPAubBatchBufferTests, givenSimpleRCSWithBatchBufferWhenItHasMSBSetInGpuAddressThenAUBShouldBeSetupSuccessfully) { + setupAUBWithBatchBuffer(pDevice, aub_stream::ENGINE_RCS, gpuBatchBufferAddr); +} + +GEN12LPTEST_F(Gen12LPAubBatchBufferTests, givenSimpleCCSWithBatchBufferWhenItHasMSBSetInGpuAddressThenAUBShouldBeSetupSuccessfully) { + setupAUBWithBatchBuffer(pDevice, aub_stream::ENGINE_CCS, gpuBatchBufferAddr); +} + +GEN12LPTEST_F(Gen12LPTimestampTests, DISABLED_GivenCommandQueueWithProfilingEnabledWhenKernelIsEnqueuedThenProfilingTimestampsAreNotZero) { + cl_queue_properties properties[3] = {CL_QUEUE_PROPERTIES, CL_QUEUE_PROFILING_ENABLE, 0}; + CommandQueueHw cmdQ(pContext, pDevice, &properties[0]); + EXPECT_EQ(aub_stream::ENGINE_CCS, pDevice->getDefaultEngine().osContext->getEngineType()); + + const uint32_t bufferSize = 4; + std::unique_ptr buffer(Buffer::create(pContext, CL_MEM_READ_WRITE, bufferSize, nullptr, retVal)); + memset(buffer->getGraphicsAllocation()->getUnderlyingBuffer(), 0, buffer->getGraphicsAllocation()->getUnderlyingBufferSize()); + buffer->forceDisallowCPUCopy = true; + + uint8_t writeData[bufferSize] = {0x11, 0x22, 0x33, 0x44}; + cl_event event; + cmdQ.enqueueWriteBuffer(buffer.get(), CL_TRUE, 0, bufferSize, writeData, nullptr, 0, nullptr, &event); + ASSERT_NE(event, nullptr); + auto eventObject = castToObject(event); + ASSERT_NE(eventObject, nullptr); + expectMemory(buffer->getGraphicsAllocation()->getUnderlyingBuffer(), writeData, bufferSize); + + uint64_t expectedTimestampValues[2] = {0, 0}; + TagNode &hwTimeStamps = *(eventObject->getHwTimeStampNode()); + uint64_t timeStampStartAddress = hwTimeStamps.getGpuAddress() + offsetof(HwTimeStamps, ContextStartTS); + uint64_t timeStampEndAddress = hwTimeStamps.getGpuAddress() + offsetof(HwTimeStamps, ContextEndTS); + expectMemoryNotEqual(reinterpret_cast(timeStampStartAddress), &expectedTimestampValues[0], sizeof(uint64_t)); + expectMemoryNotEqual(reinterpret_cast(timeStampEndAddress), &expectedTimestampValues[1], sizeof(uint64_t)); + + eventObject->release(); +} diff --git a/unit_tests/aub_tests/gen12lp/batch_buffer/aub_batch_buffer_tests_gen12lp.h b/unit_tests/aub_tests/gen12lp/batch_buffer/aub_batch_buffer_tests_gen12lp.h new file mode 100644 index 0000000000..e5f67d8aed --- /dev/null +++ b/unit_tests/aub_tests/gen12lp/batch_buffer/aub_batch_buffer_tests_gen12lp.h @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "runtime/aub/aub_helper.h" +#include "unit_tests/aub_tests/command_stream/aub_mem_dump_tests.h" + +template +void setupAUBWithBatchBuffer(const NEO::Device *pDevice, aub_stream::EngineType engineType, uint64_t gpuBatchBufferAddr) { + typedef typename NEO::AUBFamilyMapper::AUB AUB; + const auto &csTraits = NEO::CommandStreamReceiverSimulatedCommonHw::getCsTraits(engineType); + auto mmioBase = csTraits.mmioBase; + uint64_t physAddress = 0x10000; + + NEO::AUBCommandStreamReceiver::AubFileStream aubFile; + std::string filePath(NEO::folderAUB); + filePath.append(Os::fileSeparator); + std::string baseName("simple"); + baseName.append(csTraits.name); + baseName.append("WithBatchBuffer"); + baseName.append(".aub"); + filePath.append(getAubFileName(pDevice, baseName)); + + aubFile.fileHandle.open(filePath.c_str(), std::ofstream::binary); + + // Header + aubFile.init(AubMemDump::SteppingValues::A, AUB::Traits::device); + + aubFile.writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x229c), 0xffff8280); + + // enable CCS + if (engineType == aub_stream::ENGINE_CCS) { + aubFile.writeMMIO(0x0000ce90, 0x00010001); + aubFile.writeMMIO(0x00014800, 0x00010001); + } + + const size_t sizeHWSP = 0x1000; + const size_t alignHWSP = 0x1000; + auto pGlobalHWStatusPage = alignedMalloc(sizeHWSP, alignHWSP); + + uint32_t ggttGlobalHardwareStatusPage = (uint32_t)((uintptr_t)pGlobalHWStatusPage); + AubGTTData data = {true, false}; + AUB::reserveAddressGGTT(aubFile, ggttGlobalHardwareStatusPage, sizeHWSP, physAddress, data); + physAddress += sizeHWSP; + + aubFile.writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2080), ggttGlobalHardwareStatusPage); + + using MI_NOOP = typename FamilyType::MI_NOOP; + using MI_BATCH_BUFFER_START = typename FamilyType::MI_BATCH_BUFFER_START; + using MI_BATCH_BUFFER_END = typename FamilyType::MI_BATCH_BUFFER_END; + + // create a user mode batch buffer + auto physBatchBuffer = physAddress; + const auto sizeBatchBuffer = 0x1000; + auto gpuBatchBuffer = static_cast(gpuBatchBufferAddr); + physAddress += sizeBatchBuffer; + + NEO::AubHelperHw aubHelperHw(false); + AUB::reserveAddressPPGTT(aubFile, gpuBatchBuffer, sizeBatchBuffer, physBatchBuffer, 3, aubHelperHw); + uint8_t batchBuffer[sizeBatchBuffer]; + + auto noop = FamilyType::cmdInitNoop; + uint32_t noopId = 0xbaadd; + + { + auto pBatchBuffer = (void *)batchBuffer; + *(MI_NOOP *)pBatchBuffer = noop; + pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP)); + *(MI_NOOP *)pBatchBuffer = noop; + pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP)); + *(MI_NOOP *)pBatchBuffer = noop; + pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP)); + noop.TheStructure.Common.IdentificationNumberRegisterWriteEnable = true; + noop.TheStructure.Common.IdentificationNumber = noopId++; + *(MI_NOOP *)pBatchBuffer = noop; + pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_NOOP)); + *(MI_BATCH_BUFFER_END *)pBatchBuffer = FamilyType::cmdInitBatchBufferEnd; + pBatchBuffer = ptrOffset(pBatchBuffer, sizeof(MI_BATCH_BUFFER_END)); + auto sizeBufferUsed = ptrDiff(pBatchBuffer, batchBuffer); + + AUB::addMemoryWrite(aubFile, physBatchBuffer, batchBuffer, sizeBufferUsed, AubMemDump::AddressSpaceValues::TraceNonlocal, AubMemDump::DataTypeHintValues::TraceBatchBuffer); + } + + const size_t sizeRing = 0x4 * 0x1000; + const size_t alignRing = 0x1000; + size_t sizeCommands = 0; + auto pRing = alignedMalloc(sizeRing, alignRing); + + auto ggttRing = (uint32_t)(uintptr_t)pRing; + auto physRing = physAddress; + physAddress += sizeRing; + auto rRing = AUB::reserveAddressGGTT(aubFile, ggttRing, sizeRing, physRing, data); + ASSERT_NE(static_cast(-1), rRing); + EXPECT_EQ(rRing, physRing); + + auto cur = (uint32_t *)pRing; + auto bbs = FamilyType::cmdInitBatchBufferStart; + bbs.setBatchBufferStartAddressGraphicsaddress472(gpuBatchBuffer); + bbs.setAddressSpaceIndicator(MI_BATCH_BUFFER_START::ADDRESS_SPACE_INDICATOR_PPGTT); + *(MI_BATCH_BUFFER_START *)cur = bbs; + cur = ptrOffset(cur, sizeof(MI_BATCH_BUFFER_START)); + noop.TheStructure.Common.IdentificationNumberRegisterWriteEnable = true; + noop.TheStructure.Common.IdentificationNumber = noopId; + *cur++ = noop.TheStructure.RawData[0]; + + sizeCommands = ptrDiff(cur, pRing); + + AUB::addMemoryWrite(aubFile, physRing, pRing, sizeCommands, AubMemDump::AddressSpaceValues::TraceNonlocal, csTraits.aubHintCommandBuffer); + + auto sizeLRCA = csTraits.sizeLRCA; + auto pLRCABase = alignedMalloc(csTraits.sizeLRCA, csTraits.alignLRCA); + + csTraits.initialize(pLRCABase); + csTraits.setRingHead(pLRCABase, 0x0000); + csTraits.setRingTail(pLRCABase, static_cast(sizeCommands)); + csTraits.setRingBase(pLRCABase, ggttRing); + auto ringCtrl = static_cast((sizeRing - 0x1000) | 1); + csTraits.setRingCtrl(pLRCABase, ringCtrl); + + auto ggttLRCA = static_cast(reinterpret_cast(pLRCABase)); + auto physLRCA = physAddress; + physAddress += sizeLRCA; + AUB::reserveAddressGGTT(aubFile, ggttLRCA, sizeLRCA, physLRCA, data); + AUB::addMemoryWrite(aubFile, physLRCA, pLRCABase, sizeLRCA, AubMemDump::AddressSpaceValues::TraceNonlocal, csTraits.aubHintLRCA); + + typename AUB::MiContextDescriptorReg contextDescriptor = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}; + + contextDescriptor.sData.Valid = true; + contextDescriptor.sData.ForcePageDirRestore = false; + contextDescriptor.sData.ForceRestore = false; + contextDescriptor.sData.Legacy = true; + contextDescriptor.sData.FaultSupport = 0; + contextDescriptor.sData.PrivilegeAccessOrPPGTT = true; + contextDescriptor.sData.ADor64bitSupport = AUB::Traits::addressingBits > 32; + + contextDescriptor.sData.LogicalRingCtxAddress = (uintptr_t)pLRCABase / 4096; + contextDescriptor.sData.ContextID = 0; + + aubFile.writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2510), contextDescriptor.ulData[0]); + aubFile.writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2514), contextDescriptor.ulData[1]); + + // Load our new exec list + aubFile.writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2550), 1); + + // Poll until HW complete + using AubMemDump::CmdServicesMemTraceRegisterPoll; + aubFile.registerPoll( + AubMemDump::computeRegisterOffset(mmioBase, 0x2234), //EXECLIST_STATUS + 0x00008000, + 0x00008000, + false, + CmdServicesMemTraceRegisterPoll::TimeoutActionValues::Abort); + + alignedFree(pRing); + alignedFree(pLRCABase); + alignedFree(pGlobalHWStatusPage); + + aubFile.fileHandle.close(); +} diff --git a/unit_tests/aub_tests/gen12lp/execution_model/CMakeLists.txt b/unit_tests/aub_tests/gen12lp/execution_model/CMakeLists.txt new file mode 100644 index 0000000000..7478925506 --- /dev/null +++ b/unit_tests/aub_tests/gen12lp/execution_model/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (C) 2019 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +target_sources(igdrcl_aub_tests PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/enqueue_parent_kernel_tests_gen12lp.cpp +) diff --git a/unit_tests/aub_tests/gen12lp/execution_model/enqueue_parent_kernel_tests_gen12lp.cpp b/unit_tests/aub_tests/gen12lp/execution_model/enqueue_parent_kernel_tests_gen12lp.cpp new file mode 100644 index 0000000000..ef866987f5 --- /dev/null +++ b/unit_tests/aub_tests/gen12lp/execution_model/enqueue_parent_kernel_tests_gen12lp.cpp @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/built_ins/built_ins.h" +#include "runtime/mem_obj/image.h" +#include "runtime/sampler/sampler.h" +#include "test.h" +#include "unit_tests/aub_tests/fixtures/aub_parent_kernel_fixture.h" +#include "unit_tests/fixtures/buffer_fixture.h" + +using namespace NEO; + +typedef AUBParentKernelFixture GEN12LPAUBParentKernelFixture; + +GEN12LPTEST_F(GEN12LPAUBParentKernelFixture, EnqueueParentKernel) { + if (pDevice->getSupportedClVersion() >= 20) { + ASSERT_NE(nullptr, pKernel); + ASSERT_TRUE(pKernel->isParentKernel); + + const cl_queue_properties properties[3] = {(CL_QUEUE_ON_DEVICE | CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE), + 0, 0}; + + DeviceQueue *devQueue = DeviceQueue::create( + &pCmdQ->getContext(), + pDevice, + properties[0], + retVal); + + BuiltIns &builtIns = *pDevice->getExecutionEnvironment()->getBuiltIns(); + SchedulerKernel &scheduler = builtIns.getSchedulerKernel(pCmdQ->getContext()); + // Aub execution takes huge time for bigger GWS + scheduler.setGws(24); + + size_t offset[3] = {0, 0, 0}; + size_t gws[3] = {1, 1, 1}; + size_t lws[3] = {1, 1, 1}; + + // clang-format off + cl_image_format imageFormat; + imageFormat.image_channel_data_type = CL_UNSIGNED_INT8; + imageFormat.image_channel_order = CL_R; + + cl_image_desc desc = { 0 }; + desc.image_array_size = 0; + desc.image_depth = 1; + desc.image_height = 4; + desc.image_width = 4; + desc.image_type = CL_MEM_OBJECT_IMAGE3D; + desc.image_row_pitch = 0; + desc.image_slice_pitch = 0; + // clang-format on + + auto surfaceFormat = Image::getSurfaceFormatFromTable(0, &imageFormat); + Image *image = Image::create( + pContext, + 0, + surfaceFormat, + &desc, + nullptr, + retVal); + + Buffer *buffer = BufferHelper>::create(pContext); + + cl_mem bufferMem = buffer; + cl_mem imageMem = image; + + auto sampler = Sampler::create( + pContext, + CL_TRUE, + CL_ADDRESS_NONE, + CL_FILTER_LINEAR, + retVal); + + uint64_t argScalar = 2; + pKernel->setArg( + 3, + sizeof(uint64_t), + &argScalar); + + pKernel->setArg( + 2, + sizeof(cl_mem), + &bufferMem); + + pKernel->setArg( + 1, + sizeof(cl_mem), + &imageMem); + + pKernel->setArg( + 0, + sizeof(cl_sampler), + &sampler); + + pCmdQ->enqueueKernel(pKernel, 1, offset, gws, lws, 0, 0, 0); + + pCmdQ->finish(); + + uint32_t expectedNumberOfEnqueues = 1; + uint64_t gpuAddress = devQueue->getQueueBuffer()->getGpuAddress() + offsetof(IGIL_CommandQueue, m_controls.m_TotalNumberOfQueues); + + AUBCommandStreamFixture::expectMemory((void *)(uintptr_t)gpuAddress, &expectedNumberOfEnqueues, sizeof(uint32_t)); + AUBCommandStreamFixture::expectMemory((void *)(uintptr_t)buffer->getGraphicsAllocation()->getGpuAddress(), &argScalar, sizeof(size_t)); + + delete devQueue; + delete image; + delete buffer; + delete sampler; + } +} diff --git a/unit_tests/context/driver_diagnostics_tests.cpp b/unit_tests/context/driver_diagnostics_tests.cpp index 273c977185..cd720ea109 100644 --- a/unit_tests/context/driver_diagnostics_tests.cpp +++ b/unit_tests/context/driver_diagnostics_tests.cpp @@ -473,7 +473,9 @@ TEST_F(PerformanceHintTest, given64bitCompressedBufferWhenItsCreatedThenProperPe context->isSharedContext = false; auto buffer = std::unique_ptr(Buffer::create(context.get(), properties, size, static_cast(NULL), retVal)); snprintf(expectedHint, DriverDiagnostics::maxHintStringSize, DriverDiagnostics::hintFormat[BUFFER_IS_COMPRESSED], buffer.get()); - if (!is32bit && HwHelper::renderCompressedBuffersSupported(hwInfo)) { + auto compressionSupported = HwHelper::get(hwInfo.platform.eRenderCoreFamily).obtainRenderBufferCompressionPreference(size) && + HwHelper::renderCompressedBuffersSupported(hwInfo); + if (!is32bit && compressionSupported) { EXPECT_TRUE(containsHint(expectedHint, userData)); } else { EXPECT_FALSE(containsHint(expectedHint, userData)); diff --git a/unit_tests/gen12lp/CMakeLists.txt b/unit_tests/gen12lp/CMakeLists.txt new file mode 100644 index 0000000000..2741b303e6 --- /dev/null +++ b/unit_tests/gen12lp/CMakeLists.txt @@ -0,0 +1,32 @@ +# +# Copyright (C) 2019 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +if(TESTS_GEN12LP) + set(IGDRCL_SRCS_tests_gen12lp + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/aub_command_stream_receiver_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/coherency_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/command_stream_receiver_hw_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/command_stream_receiver_simulated_common_hw_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/enqueue_media_kernel_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/hw_helper_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/image_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/profiling_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/sampler_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/scheduler_source_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/tbx_command_stream_receiver_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/test_device_caps_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/test_device_queue_hw_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/test_platform_caps_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/test_preamble_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/test_preemption_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/test_sample_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/unit_test_helper_gen12lp.cpp + ) + target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen12lp}) + add_subdirectories() +endif() diff --git a/unit_tests/gen12lp/aub_command_stream_receiver_tests_gen12lp.cpp b/unit_tests/gen12lp/aub_command_stream_receiver_tests_gen12lp.cpp new file mode 100644 index 0000000000..ecc5605cd5 --- /dev/null +++ b/unit_tests/gen12lp/aub_command_stream_receiver_tests_gen12lp.cpp @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "core/unit_tests/helpers/debug_manager_state_restore.h" +#include "runtime/aub_mem_dump/page_table_entry_bits.h" +#include "runtime/command_stream/aub_command_stream_receiver_hw.h" +#include "runtime/os_interface/os_context.h" +#include "test.h" +#include "unit_tests/fixtures/device_fixture.h" +#include "unit_tests/helpers/hw_helper_tests.h" +#include "unit_tests/mocks/mock_aub_csr.h" +#include "unit_tests/mocks/mock_graphics_allocation.h" +#include "unit_tests/mocks/mock_os_context.h" + +using namespace NEO; + +using Gen12LPAubCommandStreamReceiverTests = Test; + +GEN12LPTEST_F(Gen12LPAubCommandStreamReceiverTests, givenAubCommandStreamReceiverWhenGetGUCWorkQueueItemHeaderIsCalledThenAppropriateValueDependingOnEngineTypeIsReturned) { + std::unique_ptr> aubCsr(new AUBCommandStreamReceiverHw("", true, *pDevice->executionEnvironment)); + MockOsContext rcsOsContext(0, 1, aub_stream::ENGINE_RCS, PreemptionMode::Disabled, false); + MockOsContext ccsOsContext(0, 1, aub_stream::ENGINE_CCS, PreemptionMode::Disabled, false); + + aubCsr->setupContext(ccsOsContext); + uint32_t headerCCS = aubCsr->getGUCWorkQueueItemHeader(); + aubCsr->setupContext(rcsOsContext); + uint32_t headerRCS = aubCsr->getGUCWorkQueueItemHeader(); + + EXPECT_EQ(0x00030401u, headerCCS); + EXPECT_EQ(0x00030001u, headerRCS); +} + +GEN12LPTEST_F(Gen12LPAubCommandStreamReceiverTests, givenGraphicsAlloctionWhenGetPPGTTAdditionalBitsIsCalledThenAppropriateValueIsReturned) { + std::unique_ptr> aubCsr(new AUBCommandStreamReceiverHw("", true, *pDevice->executionEnvironment)); + MockGraphicsAllocation allocation(nullptr, 0); + auto bits = aubCsr->getPPGTTAdditionalBits(&allocation); + constexpr uint64_t expectedBits = BIT(PageTableEntry::presentBit) | BIT(PageTableEntry::writableBit); + + EXPECT_EQ(expectedBits, bits); +} + +GEN12LPTEST_F(Gen12LPAubCommandStreamReceiverTests, givenCCSEnabledWhenEngineMmiosAreInitializedThenExpectL3ConfigMmioIsWritten) { + MockOsContext osContext(0, 1, aub_stream::ENGINE_CCS, PreemptionMode::Disabled, false); + AUBCommandStreamReceiverHw aubCsr("", true, *pDevice->executionEnvironment); + aubCsr.setupContext(osContext); + + auto stream = std::make_unique(); + aubCsr.stream = stream.get(); + + aubCsr.initEngineMMIO(); + + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0xB234, 0xD0000020u))); +} + +GEN12LPTEST_F(Gen12LPAubCommandStreamReceiverTests, givenRCSEnabledWhenEngineMmiosAreInitializedThenExpectL3ConfigMmioIsWritten) { + MockOsContext osContext(0, 1, aub_stream::ENGINE_RCS, PreemptionMode::Disabled, false); + AUBCommandStreamReceiverHw aubCsr("", true, *pDevice->executionEnvironment); + aubCsr.setupContext(osContext); + + auto stream = std::make_unique(); + aubCsr.stream = stream.get(); + + aubCsr.initEngineMMIO(); + + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0xB134, 0xD0000020u))); +} diff --git a/unit_tests/gen12lp/cmd_parse/cmd_parse_gen12lp.inl b/unit_tests/gen12lp/cmd_parse/cmd_parse_gen12lp.inl new file mode 100644 index 0000000000..33a5af31f6 --- /dev/null +++ b/unit_tests/gen12lp/cmd_parse/cmd_parse_gen12lp.inl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +size_t getAdditionalCommandLengthHwSpecific(void *cmd) { + return 0; +} + +const char *getAdditionalCommandNameHwSpecific(void *cmd) { + return "UNKNOWN"; +} diff --git a/unit_tests/gen12lp/cmd_parse_gen12lp.cpp b/unit_tests/gen12lp/cmd_parse_gen12lp.cpp new file mode 100644 index 0000000000..2367be8112 --- /dev/null +++ b/unit_tests/gen12lp/cmd_parse_gen12lp.cpp @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "unit_tests/gen_common/gen_cmd_parse.h" + +#include "gtest/gtest.h" +using GenStruct = NEO::GEN12LP; +using GenGfxFamily = NEO::TGLLPFamily; +#include "unit_tests/gen_common/cmd_parse_base.inl" +#include "unit_tests/gen_common/cmd_parse_compute_mode.inl" +#include "unit_tests/gen_common/cmd_parse_gpgpu_walker.inl" +#include "unit_tests/gen_common/cmd_parse_mi_arb.inl" +#include "unit_tests/gen_common/cmd_parse_sip.inl" +#include "unit_tests/helpers/hw_parse.h" +#include "unit_tests/helpers/hw_parse.inl" + +#include "cmd_parse_gen12lp.inl" + +template <> +size_t CmdParse::getCommandLengthHwSpecific(void *cmd) { + { + auto pCmd = genCmdCast(cmd); + if (pCmd) + return pCmd->TheStructure.Common.DwordLength + 2; + } + { + auto pCmd = genCmdCast(cmd); + if (pCmd) + return pCmd->TheStructure.Common.DwordLength + 2; + } + { + auto pCmd = genCmdCast(cmd); + if (pCmd) + return pCmd->TheStructure.Common.DwordLength + 2; + } + { + auto pCmd = genCmdCast(cmd); + if (pCmd) + return pCmd->TheStructure.Common.DwordLength + 2; + } + { + auto pCmd = genCmdCast(cmd); + if (pCmd) + return pCmd->TheStructure.Common.DwordLength + 2; + } + { + auto pCmd = genCmdCast(cmd); + if (pCmd) + return pCmd->TheStructure.Common.DwordLength + 2; + } + { + auto pCmd = genCmdCast(cmd); + if (pCmd) + return pCmd->TheStructure.Common.DwordLength + 2; + } + + return getAdditionalCommandLengthHwSpecific(cmd); +} + +template <> +const char *CmdParse::getCommandNameHwSpecific(void *cmd) { + if (nullptr != genCmdCast(cmd)) { + return "GPGPU_WALKER"; + } + + if (nullptr != genCmdCast(cmd)) { + return "MEDIA_INTERFACE_DESCRIPTOR_LOAD"; + } + + if (nullptr != genCmdCast(cmd)) { + return "MEDIA_VFE_STATE"; + } + + if (nullptr != genCmdCast(cmd)) { + return "MEDIA_STATE_FLUSH"; + } + + if (nullptr != genCmdCast(cmd)) { + return "MEDIA_STATE_FLUSH"; + } + + if (nullptr != genCmdCast(cmd)) { + return "GPGPU_CSR_BASE_ADDRESS"; + } + + if (nullptr != genCmdCast(cmd)) { + return "STATE_SIP"; + } + + return getAdditionalCommandNameHwSpecific(cmd); +} + +template struct CmdParse; + +namespace NEO { +template void HardwareParse::findHardwareCommands(); +template void HardwareParse::findHardwareCommands(IndirectHeap *); +template const void *HardwareParse::getStatelessArgumentPointer(const Kernel &kernel, uint32_t indexArg, IndirectHeap &ioh); +} // namespace NEO diff --git a/unit_tests/gen12lp/coherency_tests_gen12lp.cpp b/unit_tests/gen12lp/coherency_tests_gen12lp.cpp new file mode 100644 index 0000000000..5515bc2831 --- /dev/null +++ b/unit_tests/gen12lp/coherency_tests_gen12lp.cpp @@ -0,0 +1,307 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "core/helpers/ptr_math.h" +#include "runtime/command_stream/command_stream_receiver_hw.h" +#include "runtime/helpers/hardware_commands_helper.h" +#include "runtime/helpers/hw_helper.h" +#include "test.h" +#include "unit_tests/helpers/hw_parse.h" +#include "unit_tests/mocks/mock_device.h" + +using namespace NEO; + +struct Gen12LpCoherencyRequirements : public ::testing::Test { + using STATE_COMPUTE_MODE = typename TGLLPFamily::STATE_COMPUTE_MODE; + using PIPE_CONTROL = typename TGLLPFamily::PIPE_CONTROL; + + struct myCsr : public CommandStreamReceiverHw { + using CommandStreamReceiver::commandStream; + myCsr(ExecutionEnvironment &executionEnvironment) : CommandStreamReceiverHw(executionEnvironment){}; + CsrSizeRequestFlags *getCsrRequestFlags() { return &csrSizeRequestFlags; } + }; + + void makeResidentSharedAlloc() { + csr->getResidencyAllocations().push_back(alloc); + } + + void overrideCoherencyRequest(bool reqestChanged, bool requireCoherency, bool hasSharedHandles) { + csr->getCsrRequestFlags()->coherencyRequestChanged = reqestChanged; + csr->getCsrRequestFlags()->hasSharedHandles = hasSharedHandles; + flags.requiresCoherency = requireCoherency; + if (hasSharedHandles) { + makeResidentSharedAlloc(); + } + } + + void SetUp() override { + device.reset(MockDevice::createWithNewExecutionEnvironment(platformDevices[0])); + csr = new myCsr(*device->executionEnvironment); + device->resetCommandStreamReceiver(csr); + AllocationProperties properties(false, MemoryConstants::pageSize, GraphicsAllocation::AllocationType::SHARED_BUFFER, false); + + alloc = device->getMemoryManager()->createGraphicsAllocationFromSharedHandle((osHandle)123, properties, false); + } + + void TearDown() override { + device->getMemoryManager()->freeGraphicsMemory(alloc); + } + + myCsr *csr = nullptr; + std::unique_ptr device; + DispatchFlags flags = DispatchFlagsHelper::createDefaultDispatchFlags(); + GraphicsAllocation *alloc = nullptr; +}; + +GEN12LPTEST_F(Gen12LpCoherencyRequirements, coherencyCmdSizeWithoutSharedHandles) { + auto cmdsSize = sizeof(STATE_COMPUTE_MODE); + + overrideCoherencyRequest(false, false, false); + auto retSize = csr->getCmdSizeForComputeMode(); + EXPECT_EQ(0u, retSize); + + overrideCoherencyRequest(false, true, false); + retSize = csr->getCmdSizeForComputeMode(); + EXPECT_EQ(0u, retSize); + + overrideCoherencyRequest(true, true, false); + retSize = csr->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); + + overrideCoherencyRequest(true, false, false); + retSize = csr->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); +} + +GEN12LPTEST_F(Gen12LpCoherencyRequirements, coherencyCmdSizeWithSharedHandles) { + auto cmdsSize = sizeof(STATE_COMPUTE_MODE) + sizeof(PIPE_CONTROL); + + overrideCoherencyRequest(false, false, true); + auto retSize = csr->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); + + overrideCoherencyRequest(false, true, true); + retSize = csr->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); + + overrideCoherencyRequest(true, true, true); + retSize = csr->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); + + overrideCoherencyRequest(true, false, true); + retSize = csr->getCmdSizeForComputeMode(); + EXPECT_EQ(cmdsSize, retSize); +} + +GEN12LPTEST_F(Gen12LpCoherencyRequirements, coherencyCmdValuesWithoutSharedHandles) { + auto cmdsSize = sizeof(STATE_COMPUTE_MODE); + char buff[1024]; + LinearStream stream(buff, 1024); + + auto expectedScmCmd = FamilyType::cmdInitStateComputeMode; + expectedScmCmd.setForceNonCoherent(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT); + expectedScmCmd.setMaskBits(FamilyType::stateComputeModeForceNonCoherentMask); + + overrideCoherencyRequest(true, false, false); + csr->programComputeMode(stream, flags); + EXPECT_EQ(cmdsSize, stream.getUsed()); + + auto scmCmd = reinterpret_cast(stream.getCpuBase()); + EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); + + auto startOffset = stream.getUsed(); + + overrideCoherencyRequest(true, true, false); + csr->programComputeMode(stream, flags); + EXPECT_EQ(cmdsSize * 2, stream.getUsed()); + + expectedScmCmd.setForceNonCoherent(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_DISABLED); + expectedScmCmd.setMaskBits(FamilyType::stateComputeModeForceNonCoherentMask); + scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), startOffset)); + EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); +} + +GEN12LPTEST_F(Gen12LpCoherencyRequirements, coherencyCmdValuesWithSharedHandles) { + auto cmdsSize = sizeof(STATE_COMPUTE_MODE) + sizeof(PIPE_CONTROL); + char buff[1024]; + LinearStream stream(buff, 1024); + + auto expectedScmCmd = FamilyType::cmdInitStateComputeMode; + expectedScmCmd.setForceNonCoherent(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT); + expectedScmCmd.setMaskBits(FamilyType::stateComputeModeForceNonCoherentMask); + + auto expectedPcCmd = FamilyType::cmdInitPipeControl; + + overrideCoherencyRequest(true, false, true); + csr->programComputeMode(stream, flags); + EXPECT_EQ(cmdsSize, stream.getUsed()); + + auto scmCmd = reinterpret_cast(stream.getCpuBase()); + EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); + + auto pcCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), sizeof(STATE_COMPUTE_MODE))); + EXPECT_TRUE(memcmp(&expectedPcCmd, pcCmd, sizeof(PIPE_CONTROL)) == 0); + + auto startOffset = stream.getUsed(); + + overrideCoherencyRequest(true, true, true); + csr->programComputeMode(stream, flags); + EXPECT_EQ(cmdsSize * 2, stream.getUsed()); + + expectedScmCmd.setForceNonCoherent(STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_DISABLED); + expectedScmCmd.setMaskBits(FamilyType::stateComputeModeForceNonCoherentMask); + scmCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), startOffset)); + EXPECT_TRUE(memcmp(&expectedScmCmd, scmCmd, sizeof(STATE_COMPUTE_MODE)) == 0); + + pcCmd = reinterpret_cast(ptrOffset(stream.getCpuBase(), startOffset + sizeof(STATE_COMPUTE_MODE))); + EXPECT_TRUE(memcmp(&expectedPcCmd, pcCmd, sizeof(PIPE_CONTROL)) == 0); +} + +GEN12LPTEST_F(Gen12LpCoherencyRequirements, givenCoherencyRequirementWithoutSharedHandlesWhenFlushTaskCalledThenProgramCmdOnlyIfChanged) { + auto startOffset = csr->commandStream.getUsed(); + + auto graphicAlloc = csr->getMemoryManager()->allocateGraphicsMemoryWithProperties(MockAllocationProperties{MemoryConstants::pageSize}); + IndirectHeap stream(graphicAlloc); + + auto flushTask = [&](bool coherencyRequired) { + flags.requiresCoherency = coherencyRequired; + startOffset = csr->commandStream.getUsed(); + csr->flushTask(stream, 0, stream, stream, stream, 0, flags, *device); + }; + + auto findCmd = [&](bool expectToBeProgrammed, bool expectCoherent, bool expectPipeControl) { + HardwareParse hwParser; + hwParser.parseCommands(csr->commandStream, startOffset); + bool foundOne = false; + + STATE_COMPUTE_MODE::FORCE_NON_COHERENT expectedCoherentValue = expectCoherent ? STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_DISABLED : STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT; + uint32_t expectedCoherentMask = FamilyType::stateComputeModeForceNonCoherentMask; + + for (auto it = hwParser.cmdList.begin(); it != hwParser.cmdList.end(); it++) { + auto cmd = genCmdCast(*it); + if (cmd) { + EXPECT_EQ(expectedCoherentValue, cmd->getForceNonCoherent()); + EXPECT_EQ(expectedCoherentMask, cmd->getMaskBits()); + EXPECT_FALSE(foundOne); + foundOne = true; + auto pc = genCmdCast(*(++it)); + if (!expectPipeControl) + EXPECT_EQ(nullptr, pc); + else { + EXPECT_NE(nullptr, pc); + } + } + } + EXPECT_EQ(expectToBeProgrammed, foundOne); + }; + + auto hwInfo = device->getHardwareInfo(); + + flushTask(false); + if (HardwareCommandsHelper::isPipeControlPriorToPipelineSelectWArequired(hwInfo)) { + findCmd(true, false, true); // first time + } else { + findCmd(true, false, false); // first time + } + + flushTask(false); + findCmd(false, false, false); // not changed + + flushTask(true); + findCmd(true, true, false); // changed + + flushTask(true); + findCmd(false, true, false); // not changed + + flushTask(false); + findCmd(true, false, false); // changed + + flushTask(false); + findCmd(false, false, false); // not changed + csr->getMemoryManager()->freeGraphicsMemory(graphicAlloc); +} + +GEN12LPTEST_F(Gen12LpCoherencyRequirements, givenCoherencyRequirementWithSharedHandlesWhenFlushTaskCalledThenAlwaysProgramCmds) { + auto startOffset = csr->commandStream.getUsed(); + auto graphicsAlloc = csr->getMemoryManager()->allocateGraphicsMemoryWithProperties(MockAllocationProperties{MemoryConstants::pageSize}); + IndirectHeap stream(graphicsAlloc); + + auto flushTask = [&](bool coherencyRequired) { + flags.requiresCoherency = coherencyRequired; + makeResidentSharedAlloc(); + + startOffset = csr->commandStream.getUsed(); + csr->flushTask(stream, 0, stream, stream, stream, 0, flags, *device); + }; + + auto flushTaskAndFindCmds = [&](bool expectCoherent) { + flushTask(expectCoherent); + HardwareParse hwParser; + hwParser.parseCommands(csr->commandStream, startOffset); + bool foundOne = false; + + STATE_COMPUTE_MODE::FORCE_NON_COHERENT expectedCoherentValue = expectCoherent ? STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_DISABLED : STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT; + uint32_t expectedCoherentMask = FamilyType::stateComputeModeForceNonCoherentMask; + + for (auto it = hwParser.cmdList.begin(); it != hwParser.cmdList.end(); it++) { + auto cmd = genCmdCast(*it); + if (cmd) { + EXPECT_EQ(expectedCoherentValue, cmd->getForceNonCoherent()); + EXPECT_EQ(expectedCoherentMask, cmd->getMaskBits()); + EXPECT_FALSE(foundOne); + foundOne = true; + auto pc = genCmdCast(*(++it)); + EXPECT_NE(nullptr, pc); + } + } + EXPECT_TRUE(foundOne); + }; + + flushTaskAndFindCmds(false); // first time + flushTaskAndFindCmds(false); // not changed + flushTaskAndFindCmds(true); // changed + flushTaskAndFindCmds(true); // not changed + flushTaskAndFindCmds(false); // changed + flushTaskAndFindCmds(false); // not changed + + csr->getMemoryManager()->freeGraphicsMemory(graphicsAlloc); +} + +GEN12LPTEST_F(Gen12LpCoherencyRequirements, givenFlushWithoutSharedHandlesWhenPreviouslyUsedThenProgramPcAndSCM) { + auto graphicAlloc = csr->getMemoryManager()->allocateGraphicsMemoryWithProperties(MockAllocationProperties{MemoryConstants::pageSize}); + IndirectHeap stream(graphicAlloc); + + makeResidentSharedAlloc(); + csr->flushTask(stream, 0, stream, stream, stream, 0, flags, *device); + EXPECT_TRUE(csr->getCsrRequestFlags()->hasSharedHandles); + auto startOffset = csr->commandStream.getUsed(); + + csr->flushTask(stream, 0, stream, stream, stream, 0, flags, *device); + EXPECT_TRUE(csr->getCsrRequestFlags()->hasSharedHandles); + + HardwareParse hwParser; + hwParser.parseCommands(csr->commandStream, startOffset); + + STATE_COMPUTE_MODE::FORCE_NON_COHERENT expectedCoherentValue = STATE_COMPUTE_MODE::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT; + uint32_t expectedCoherentMask = FamilyType::stateComputeModeForceNonCoherentMask; + + bool foundOne = false; + for (auto it = hwParser.cmdList.begin(); it != hwParser.cmdList.end(); it++) { + auto cmd = genCmdCast(*it); + if (cmd) { + EXPECT_EQ(expectedCoherentValue, cmd->getForceNonCoherent()); + EXPECT_EQ(expectedCoherentMask, cmd->getMaskBits()); + EXPECT_FALSE(foundOne); + foundOne = true; + auto pc = genCmdCast(*(++it)); + EXPECT_NE(nullptr, pc); + } + } + EXPECT_TRUE(foundOne); + + csr->getMemoryManager()->freeGraphicsMemory(graphicAlloc); +} diff --git a/unit_tests/gen12lp/command_stream_receiver_hw_tests_gen12lp.cpp b/unit_tests/gen12lp/command_stream_receiver_hw_tests_gen12lp.cpp new file mode 100644 index 0000000000..799bf66724 --- /dev/null +++ b/unit_tests/gen12lp/command_stream_receiver_hw_tests_gen12lp.cpp @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "core/command_stream/linear_stream.h" +#include "runtime/command_queue/command_queue_hw.h" +#include "runtime/command_stream/command_stream_receiver.h" +#include "test.h" +#include "unit_tests/fixtures/device_fixture.h" +#include "unit_tests/fixtures/ult_command_stream_receiver_fixture.h" +#include "unit_tests/helpers/hw_parse.h" +#include "unit_tests/mocks/mock_command_queue.h" +#include "unit_tests/mocks/mock_context.h" +#include "unit_tests/mocks/mock_csr.h" +#include "unit_tests/mocks/mock_event.h" +#include "unit_tests/mocks/mock_kernel.h" + +#include "gtest/gtest.h" +#include "reg_configs_common.h" + +using namespace NEO; + +#include "unit_tests/command_stream/command_stream_receiver_hw_tests.inl" + +using CommandStreamReceiverHwTestGen12lp = CommandStreamReceiverHwTest; + +GEN12LPTEST_F(CommandStreamReceiverHwTestGen12lp, givenPreambleSentWhenL3ConfigRequestChangedThenDontProgramL3Register) { + size_t GWS = 1; + MockContext ctx(pDevice); + MockKernelWithInternals kernel(*pDevice); + CommandQueueHw commandQueue(&ctx, pDevice, 0); + auto commandStreamReceiver = new MockCsrHw(*pDevice->executionEnvironment); + pDevice->resetCommandStreamReceiver(commandStreamReceiver); + auto &commandStreamCSR = commandStreamReceiver->getCS(); + + commandStreamReceiver->isPreambleSent = true; + commandStreamReceiver->lastSentL3Config = 0; + + commandQueue.enqueueKernel(kernel, 1, nullptr, &GWS, nullptr, 0, nullptr, nullptr); + + parseCommands(commandStreamCSR, 0); + auto itorCmd = findMmio(cmdList.begin(), cmdList.end(), L3CNTLRegisterOffset::registerOffset); + ASSERT_EQ(cmdList.end(), itorCmd); +} + +GEN12LPTEST_F(CommandStreamReceiverHwTestGen12lp, whenProgrammingMiSemaphoreWaitThenSetRegisterPollModeMemoryPoll) { + using MI_SEMAPHORE_WAIT = typename FamilyType::MI_SEMAPHORE_WAIT; + MI_SEMAPHORE_WAIT miSemaphoreWait = FamilyType::cmdInitMiSemaphoreWait; + EXPECT_EQ(MI_SEMAPHORE_WAIT::REGISTER_POLL_MODE::REGISTER_POLL_MODE_MEMORY_POLL, miSemaphoreWait.getRegisterPollMode()); +} + +using CommandStreamReceiverFlushTaskTests = UltCommandStreamReceiverTest; +GEN12LPTEST_F(UltCommandStreamReceiverTest, givenStateBaseAddressWhenItIsRequiredThenThereIsPipeControlPriorToItWithTextureCacheFlushAndHdc) { + using STATE_BASE_ADDRESS = typename FamilyType::STATE_BASE_ADDRESS; + auto &commandStreamReceiver = pDevice->getUltCommandStreamReceiver(); + configureCSRtoNonDirtyState(); + ioh.replaceBuffer(ptrOffset(ioh.getCpuBase(), +1u), ioh.getMaxAvailableSpace() + MemoryConstants::pageSize * 3); + + flushTask(commandStreamReceiver); + + parseCommands(commandStreamReceiver.commandStream, 0); + auto stateBaseAddressItor = find(cmdList.begin(), cmdList.end()); + auto pipeControlItor = find(cmdList.begin(), stateBaseAddressItor); + EXPECT_NE(stateBaseAddressItor, pipeControlItor); + auto pipeControlCmd = reinterpret_cast(*pipeControlItor); + EXPECT_TRUE(pipeControlCmd->getTextureCacheInvalidationEnable()); + EXPECT_TRUE(pipeControlCmd->getDcFlushEnable()); + + if (productFamily == PRODUCT_FAMILY::IGFX_TIGERLAKE_LP) { + EXPECT_TRUE(pipeControlCmd->getHdcFlushEnable()); + } else { + EXPECT_FALSE(pipeControlCmd->getHdcFlushEnable()); + } +} diff --git a/unit_tests/gen12lp/command_stream_receiver_simulated_common_hw_tests_gen12lp.cpp b/unit_tests/gen12lp/command_stream_receiver_simulated_common_hw_tests_gen12lp.cpp new file mode 100644 index 0000000000..c1e1b72c2a --- /dev/null +++ b/unit_tests/gen12lp/command_stream_receiver_simulated_common_hw_tests_gen12lp.cpp @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "core/unit_tests/helpers/debug_manager_state_restore.h" +#include "runtime/helpers/hardware_context_controller.h" +#include "test.h" +#include "unit_tests/fixtures/device_fixture.h" +#include "unit_tests/mocks/mock_aub_stream.h" + +#include "command_stream_receiver_simulated_hw.h" + +using namespace NEO; + +using Gen12LPCommandStreamReceiverSimulatedCommonHwTests = Test; + +template +class MockSimulatedCsrHw : public CommandStreamReceiverSimulatedHw { + public: + using CommandStreamReceiverSimulatedHw::CommandStreamReceiverSimulatedHw; + + void pollForCompletion() override {} + bool writeMemory(GraphicsAllocation &gfxAllocation) override { return true; } + void writeMemory(uint64_t gpuAddress, void *cpuAddress, size_t size, uint32_t memoryBank, uint64_t entryBits) override {} +}; + +GEN12LPTEST_F(Gen12LPCommandStreamReceiverSimulatedCommonHwTests, givenAubCommandStreamReceiverWhewGlobalMmiosAreInitializedThenMOCSRegistersAreConfigured) { + MockSimulatedCsrHw csrSimulatedCommonHw(*pDevice->executionEnvironment); + + auto stream = std::make_unique(); + csrSimulatedCommonHw.stream = stream.get(); + + csrSimulatedCommonHw.initGlobalMMIO(); + + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004000, 0x00000008))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004004, 0x00000038))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004008, 0x00000038))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000400C, 0x00000008))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004010, 0x00000018))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004014, 0x00060038))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004018, 0x00000000))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000401C, 0x00000033))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004020, 0x00060037))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004024, 0x0000003B))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004028, 0x00000032))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000402C, 0x00000036))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004030, 0x0000003A))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004034, 0x00000033))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004038, 0x00000037))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000403C, 0x0000003B))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004040, 0x00000030))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004044, 0x00000034))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004048, 0x00000038))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000404C, 0x00000031))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004050, 0x00000032))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004054, 0x00000036))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004058, 0x0000003A))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000405C, 0x00000033))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004060, 0x00000037))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004064, 0x0000003B))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004068, 0x00000032))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000406C, 0x00000036))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004070, 0x0000003A))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004074, 0x00000033))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004078, 0x00000037))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000407C, 0x0000003B))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004080, 0x00000030))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004084, 0x00000034))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004088, 0x00000038))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000408C, 0x00000031))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004090, 0x00000032))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004094, 0x00000036))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x00004098, 0x0000003A))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000409C, 0x00000033))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040A0, 0x00000037))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040A4, 0x0000003B))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040A8, 0x00000032))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040AC, 0x00000036))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040B0, 0x0000003A))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040B4, 0x00000033))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040B8, 0x00000037))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040BC, 0x0000003B))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040C0, 0x00000038))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040C4, 0x00000034))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040C8, 0x00000038))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040CC, 0x00000031))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040D0, 0x00000032))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040D4, 0x00000036))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040D8, 0x0000003A))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040DC, 0x00000033))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040E0, 0x00000037))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040E4, 0x0000003B))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040E8, 0x00000032))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040EC, 0x00000036))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040F0, 0x00000038))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040F4, 0x00000038))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040F8, 0x00000038))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x000040FC, 0x00000038))); +} + +GEN12LPTEST_F(Gen12LPCommandStreamReceiverSimulatedCommonHwTests, givenAubCommandStreamReceiverWhenGlobalMmiosAreInitializedThenLNCFRegistersAreConfigured) { + MockSimulatedCsrHw csrSimulatedCommonHw(*pDevice->executionEnvironment); + + auto stream = std::make_unique(); + csrSimulatedCommonHw.stream = stream.get(); + + csrSimulatedCommonHw.initGlobalMMIO(); + + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B020, 0x00300010))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B024, 0x00300010))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B028, 0x00300030))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B02C, 0x00000000))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B030, 0x0030001F))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B034, 0x00170013))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B038, 0x0000001F))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B03C, 0x00000000))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B040, 0x00100000))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B044, 0x00170013))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B048, 0x0010001F))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B04C, 0x00170013))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B050, 0x0030001F))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B054, 0x00170013))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B058, 0x0000001F))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B05C, 0x00000000))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B060, 0x00100000))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B064, 0x00170013))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B068, 0x0010001F))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B06C, 0x00170013))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B070, 0x0030001F))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B074, 0x00170013))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B078, 0x0000001F))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B07C, 0x00000000))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B080, 0x00000030))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B084, 0x00170013))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B088, 0x0010001F))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B08C, 0x00170013))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B090, 0x0030001F))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B094, 0x00170013))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B098, 0x00300010))); + EXPECT_TRUE(stream->isOnMmioList(MMIOPair(0x0000B09C, 0x00300010))); +} diff --git a/unit_tests/gen12lp/enqueue_media_kernel_gen12lp.cpp b/unit_tests/gen12lp/enqueue_media_kernel_gen12lp.cpp new file mode 100644 index 0000000000..763fd55bfb --- /dev/null +++ b/unit_tests/gen12lp/enqueue_media_kernel_gen12lp.cpp @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "test.h" +#include "unit_tests/fixtures/media_kernel_fixture.h" + +using namespace NEO; +typedef MediaKernelFixture MediaKernelTest; + +GEN12LPTEST_F(MediaKernelTest, givenGen12LpCsrWhenEnqueueBlockedVmeKernelFirstTimeThenProgramPipelineSelectionAndMediaSampler) { + typedef typename TGLLPFamily::PIPELINE_SELECT PIPELINE_SELECT; + + cl_uint workDim = 1; + size_t globalWorkOffset[3] = {0, 0, 0}; + size_t globalWorkSize[3] = {1, 1, 1}; + + UserEvent userEvent(context); + cl_event blockedEvent = &userEvent; + + auto retVal = pCmdQ->enqueueKernel( + pVmeKernel, + workDim, + globalWorkOffset, + globalWorkSize, + nullptr, + 1, + &blockedEvent, + nullptr); + ASSERT_EQ(CL_SUCCESS, retVal); + + userEvent.setStatus(CL_COMPLETE); + + parseCommands(*pCmdQ); + ASSERT_NE(cmdPipelineSelect, nullptr); + auto *pCmd = genCmdCast(cmdPipelineSelect); + + auto expectedMask = pipelineSelectEnablePipelineSelectMaskBits | pipelineSelectMediaSamplerDopClockGateMaskBits; + auto expectedPipelineSelection = PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU; + EXPECT_EQ(expectedMask, pCmd->getMaskBits()); + EXPECT_EQ(expectedPipelineSelection, pCmd->getPipelineSelection()); + EXPECT_FALSE(pCmd->getMediaSamplerDopClockGateEnable()); +} + +GEN12LPTEST_F(MediaKernelTest, givenGen12LpCsrWhenEnqueueBlockedNonVmeKernelFirstTimeThenProgramPipelineSelectionAndMediaSampler) { + typedef typename TGLLPFamily::PIPELINE_SELECT PIPELINE_SELECT; + + cl_uint workDim = 1; + size_t globalWorkOffset[3] = {0, 0, 0}; + size_t globalWorkSize[3] = {1, 1, 1}; + + UserEvent userEvent(context); + cl_event blockedEvent = &userEvent; + + auto retVal = pCmdQ->enqueueKernel( + pKernel, + workDim, + globalWorkOffset, + globalWorkSize, + nullptr, + 1, + &blockedEvent, + nullptr); + ASSERT_EQ(CL_SUCCESS, retVal); + + userEvent.setStatus(CL_COMPLETE); + + parseCommands(*pCmdQ); + ASSERT_NE(cmdPipelineSelect, nullptr); + auto *pCmd = genCmdCast(cmdPipelineSelect); + + auto expectedMask = pipelineSelectEnablePipelineSelectMaskBits | pipelineSelectMediaSamplerDopClockGateMaskBits; + auto expectedPipelineSelection = PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU; + EXPECT_EQ(expectedMask, pCmd->getMaskBits()); + EXPECT_EQ(expectedPipelineSelection, pCmd->getPipelineSelection()); + EXPECT_TRUE(pCmd->getMediaSamplerDopClockGateEnable()); +} + +GEN12LPTEST_F(MediaKernelTest, givenGen12LpCsrWhenEnqueueVmeKernelFirstTimeThenProgramPipelineSelectionAndMediaSampler) { + typedef typename TGLLPFamily::PIPELINE_SELECT PIPELINE_SELECT; + enqueueVmeKernel(); + + auto numCommands = getCommandsList().size(); + EXPECT_EQ(1u, numCommands); + + auto pCmd = getCommand(); + auto expectedMask = pipelineSelectEnablePipelineSelectMaskBits | pipelineSelectMediaSamplerDopClockGateMaskBits; + auto expectedPipelineSelection = PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU; + EXPECT_EQ(expectedMask, pCmd->getMaskBits()); + EXPECT_EQ(expectedPipelineSelection, pCmd->getPipelineSelection()); + EXPECT_FALSE(pCmd->getMediaSamplerDopClockGateEnable()); +} + +GEN12LPTEST_F(MediaKernelTest, givenGen12LpCsrWhenEnqueueNonVmeKernelFirstTimeThenProgramPipelineSelectionAndMediaSampler) { + typedef typename TGLLPFamily::PIPELINE_SELECT PIPELINE_SELECT; + enqueueRegularKernel(); + + auto numCommands = getCommandsList().size(); + EXPECT_EQ(1u, numCommands); + + auto pCmd = getCommand(); + auto expectedMask = pipelineSelectEnablePipelineSelectMaskBits | pipelineSelectMediaSamplerDopClockGateMaskBits; + auto expectedPipelineSelection = PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU; + EXPECT_EQ(expectedMask, pCmd->getMaskBits()); + EXPECT_EQ(expectedPipelineSelection, pCmd->getPipelineSelection()); + EXPECT_TRUE(pCmd->getMediaSamplerDopClockGateEnable()); +} + +GEN12LPTEST_F(MediaKernelTest, givenGen12LpCsrWhenEnqueueVmeKernelTwiceThenProgramPipelineSelectOnce) { + typedef typename TGLLPFamily::PIPELINE_SELECT PIPELINE_SELECT; + enqueueVmeKernel(); + auto numCommands = getCommandsList().size(); + EXPECT_EQ(1u, numCommands); +} + +GEN12LPTEST_F(MediaKernelTest, givenGen12LpCsrWhenEnqueueNonVmeKernelTwiceThenProgramPipelineSelectOnce) { + typedef typename TGLLPFamily::PIPELINE_SELECT PIPELINE_SELECT; + enqueueVmeKernel(); + auto numCommands = getCommandsList().size(); + EXPECT_EQ(1u, numCommands); +} + +GEN12LPTEST_F(MediaKernelTest, givenGen12LpCsrWhenEnqueueVmeKernelAfterNonVmeKernelThenProgramPipelineSelectionAndMediaSamplerTwice) { + typedef typename TGLLPFamily::PIPELINE_SELECT PIPELINE_SELECT; + enqueueRegularKernel(); + enqueueVmeKernel(); + + auto commands = getCommandsList(); + EXPECT_EQ(2u, commands.size()); + + auto pCmd = static_cast(commands.back()); + + auto expectedMask = pipelineSelectEnablePipelineSelectMaskBits | pipelineSelectMediaSamplerDopClockGateMaskBits; + EXPECT_EQ(expectedMask, pCmd->getMaskBits()); + EXPECT_FALSE(pCmd->getMediaSamplerDopClockGateEnable()); +} + +GEN12LPTEST_F(MediaKernelTest, givenGen12LpCsrWhenEnqueueNonVmeKernelAfterVmeKernelThenProgramProgramPipelineSelectionAndMediaSamplerTwice) { + typedef typename TGLLPFamily::PIPELINE_SELECT PIPELINE_SELECT; + enqueueVmeKernel(); + enqueueRegularKernel(); + + auto commands = getCommandsList(); + EXPECT_EQ(2u, commands.size()); + + auto pCmd = static_cast(commands.back()); + + auto expectedMask = pipelineSelectEnablePipelineSelectMaskBits | pipelineSelectMediaSamplerDopClockGateMaskBits; + EXPECT_EQ(expectedMask, pCmd->getMaskBits()); + EXPECT_TRUE(pCmd->getMediaSamplerDopClockGateEnable()); +} + +GEN12LPTEST_F(MediaKernelTest, givenGen12LpCsrWhenEnqueueVmeKernelThenVmeSubslicesConfigDoesntChangeToFalse) { + auto csr = static_cast *>(&pDevice->getGpgpuCommandStreamReceiver()); + csr->lastVmeSubslicesConfig = true; + enqueueVmeKernel(); + EXPECT_TRUE(csr->lastVmeSubslicesConfig); +} + +GEN12LPTEST_F(MediaKernelTest, givenGen12LpCsrWhenEnqueueVmeKernelThenVmeSubslicesConfigDoesntChangeToTrue) { + auto csr = static_cast *>(&pDevice->getGpgpuCommandStreamReceiver()); + csr->lastVmeSubslicesConfig = false; + enqueueVmeKernel(); + EXPECT_FALSE(csr->lastVmeSubslicesConfig); +} + +GEN12LPTEST_F(MediaKernelTest, givenGen12LpCmdSizeForVme) { + auto csr = static_cast *>(&pDevice->getGpgpuCommandStreamReceiver()); + + csr->lastVmeSubslicesConfig = false; + EXPECT_EQ(0u, csr->getCmdSizeForMediaSampler(false)); + EXPECT_EQ(0u, csr->getCmdSizeForMediaSampler(true)); + + csr->lastVmeSubslicesConfig = true; + EXPECT_EQ(0u, csr->getCmdSizeForMediaSampler(false)); + EXPECT_EQ(0u, csr->getCmdSizeForMediaSampler(true)); +} diff --git a/unit_tests/gen12lp/hw_helper_tests_gen12lp.cpp b/unit_tests/gen12lp/hw_helper_tests_gen12lp.cpp new file mode 100644 index 0000000000..a4e6b9809c --- /dev/null +++ b/unit_tests/gen12lp/hw_helper_tests_gen12lp.cpp @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "unit_tests/helpers/hw_helper_tests.h" +#include "unit_tests/mocks/mock_context.h" + +#include "engine_node.h" + +using HwHelperTestGen12Lp = HwHelperTest; + +GEN12LPTEST_F(HwHelperTestGen12Lp, givenTglLpThenAuxTranslationIsRequired) { + auto &helper = HwHelper::get(renderCoreFamily); + EXPECT_TRUE(helper.requiresAuxResolves()); +} + +GEN12LPTEST_F(HwHelperTestGen12Lp, getMaxBarriersPerSliceReturnsCorrectSize) { + auto &helper = HwHelper::get(renderCoreFamily); + EXPECT_EQ(32u, helper.getMaxBarrierRegisterPerSlice()); +} + +GEN12LPTEST_F(HwHelperTestGen12Lp, givenGen12LpSkuWhenGettingCapabilityCoherencyFlagThenExpectValidValue) { + auto &helper = HwHelper::get(renderCoreFamily); + bool coherency = false; + helper.setCapabilityCoherencyFlag(&hardwareInfo, coherency); + + if (hardwareInfo.platform.eProductFamily == IGFX_TIGERLAKE_LP) { + hardwareInfo.platform.usRevId = 0x1; + helper.setCapabilityCoherencyFlag(&hardwareInfo, coherency); + EXPECT_TRUE(coherency); + hardwareInfo.platform.usRevId = 0x0; + helper.setCapabilityCoherencyFlag(&hardwareInfo, coherency); + EXPECT_FALSE(coherency); + } else { + EXPECT_TRUE(coherency); + } +} + +GEN12LPTEST_F(HwHelperTestGen12Lp, getPitchAlignmentForImage) { + auto &helper = HwHelper::get(renderCoreFamily); + auto stepping = hardwareInfo.platform.usRevId; + + if ((hardwareInfo.platform.eProductFamily == IGFX_TIGERLAKE_LP) && + stepping == 0) { + EXPECT_EQ(64u, helper.getPitchAlignmentForImage(&hardwareInfo)); + } else { + EXPECT_EQ(4u, helper.getPitchAlignmentForImage(&hardwareInfo)); + } +} + +GEN12LPTEST_F(HwHelperTestGen12Lp, adjustDefaultEngineTypeNoCcs) { + hardwareInfo.featureTable.ftrCCSNode = false; + + auto &helper = HwHelper::get(renderCoreFamily); + helper.adjustDefaultEngineType(&hardwareInfo); + EXPECT_EQ(aub_stream::ENGINE_RCS, hardwareInfo.capabilityTable.defaultEngineType); +} + +GEN12LPTEST_F(HwHelperTestGen12Lp, adjustDefaultEngineTypeCcs) { + hardwareInfo.featureTable.ftrCCSNode = true; + + auto &helper = HwHelper::get(renderCoreFamily); + helper.adjustDefaultEngineType(&hardwareInfo); + EXPECT_EQ(aub_stream::ENGINE_CCS, hardwareInfo.capabilityTable.defaultEngineType); +} + +GEN12LPTEST_F(HwHelperTestGen12Lp, givenGen12LpPlatformWhenSetupHardwareCapabilitiesIsCalledThenDefaultImplementationIsUsed) { + auto &helper = HwHelper::get(renderCoreFamily); + + testDefaultImplementationOfSetupHardwareCapabilities(helper, hardwareInfo); +} + +GEN12LPTEST_F(HwHelperTestGen12Lp, whenGetConfigureAddressSpaceModeThenReturnOne) { + auto &helper = HwHelper::get(renderCoreFamily); + EXPECT_EQ(1u, helper.getConfigureAddressSpaceMode()); +} + +GEN12LPTEST_F(HwHelperTestGen12Lp, givenCompressionFtrEnabledWhenAskingForPageTableManagerThenReturnTrue) { + auto &helper = HwHelper::get(renderCoreFamily); + + hardwareInfo.capabilityTable.ftrRenderCompressedBuffers = false; + hardwareInfo.capabilityTable.ftrRenderCompressedImages = false; + EXPECT_FALSE(helper.isPageTableManagerSupported(hardwareInfo)); + + hardwareInfo.capabilityTable.ftrRenderCompressedBuffers = true; + hardwareInfo.capabilityTable.ftrRenderCompressedImages = false; + EXPECT_TRUE(helper.isPageTableManagerSupported(hardwareInfo)); + + hardwareInfo.capabilityTable.ftrRenderCompressedBuffers = false; + hardwareInfo.capabilityTable.ftrRenderCompressedImages = true; + EXPECT_TRUE(helper.isPageTableManagerSupported(hardwareInfo)); + + hardwareInfo.capabilityTable.ftrRenderCompressedBuffers = true; + hardwareInfo.capabilityTable.ftrRenderCompressedImages = true; + EXPECT_TRUE(helper.isPageTableManagerSupported(hardwareInfo)); +} + +GEN12LPTEST_F(HwHelperTestGen12Lp, whenGetGpgpuEnginesThenReturnTwoRcsEnginesAndOneCcsEngine) { + EXPECT_EQ(3u, pDevice->getExecutionEnvironment()->commandStreamReceivers[0].size()); + auto &engines = HwHelperHw::get().getGpgpuEngineInstances(); + EXPECT_EQ(3u, engines.size()); + EXPECT_EQ(aub_stream::ENGINE_RCS, engines[0]); + EXPECT_EQ(aub_stream::ENGINE_RCS, engines[1]); + EXPECT_EQ(aub_stream::ENGINE_CCS, engines[2]); +} + +class HwHelperTestsGen12LpBuffer : public ::testing::Test { + public: + void SetUp() override { + ExecutionEnvironment *executionEnvironment = platformImpl->peekExecutionEnvironment(); + device.reset(Device::create(executionEnvironment, 0u)); + context = std::make_unique(device.get(), true); + context->setContextType(ContextType::CONTEXT_TYPE_UNRESTRICTIVE); + } + + cl_int retVal = CL_SUCCESS; + std::unique_ptr device; + std::unique_ptr context; + std::unique_ptr buffer; +}; + +GEN12LPTEST_F(HwHelperTestsGen12LpBuffer, givenCompressedBufferThenCheckResourceCompatibilitySetCL_INVALID_MEM_OBJ) { + auto &helper = HwHelper::get(renderCoreFamily); + + buffer.reset(Buffer::create(context.get(), 0, MemoryConstants::cacheLineSize, nullptr, retVal)); + + buffer->getGraphicsAllocation()->setAllocationType(GraphicsAllocation::AllocationType::BUFFER_COMPRESSED); + + cl_int errCode = 0; + + helper.checkResourceCompatibility(buffer.get(), errCode); + + EXPECT_EQ(CL_INVALID_MEM_OBJECT, errCode); +} + +GEN12LPTEST_F(HwHelperTestsGen12LpBuffer, givenBufferThenCheckResourceCompatibilityDoesNotSetErrorCode) { + auto &helper = HwHelper::get(renderCoreFamily); + + buffer.reset(Buffer::create(context.get(), 0, MemoryConstants::cacheLineSize, nullptr, retVal)); + + buffer->getGraphicsAllocation()->setAllocationType(GraphicsAllocation::AllocationType::BUFFER); + + cl_int errCode = CL_SUCCESS; + + helper.checkResourceCompatibility(buffer.get(), errCode); + + EXPECT_EQ(CL_SUCCESS, errCode); +} diff --git a/unit_tests/gen12lp/image_tests_gen12lp.cpp b/unit_tests/gen12lp/image_tests_gen12lp.cpp new file mode 100644 index 0000000000..7518cf8c6e --- /dev/null +++ b/unit_tests/gen12lp/image_tests_gen12lp.cpp @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/gmm_helper/gmm_helper.h" +#include "runtime/memory_manager/memory_manager.h" +#include "test.h" +#include "unit_tests/fixtures/image_fixture.h" +#include "unit_tests/helpers/variable_backup.h" +#include "unit_tests/mocks/mock_allocation_properties.h" +#include "unit_tests/mocks/mock_context.h" +#include "unit_tests/mocks/mock_gmm.h" + +#include + +using namespace NEO; + +typedef ::testing::Test gen12LpImageTests; + +GEN12LPTEST_F(gen12LpImageTests, appendSurfaceStateParamsDoesNothing) { + typedef typename FamilyType::RENDER_SURFACE_STATE RENDER_SURFACE_STATE; + MockContext context; + auto image = std::unique_ptr(ImageHelper::create(&context)); + auto surfaceStateBefore = FamilyType::cmdInitRenderSurfaceState; + auto surfaceStateAfter = FamilyType::cmdInitRenderSurfaceState; + auto imageHw = static_cast *>(image.get()); + + EXPECT_EQ(0, memcmp(&surfaceStateBefore, &surfaceStateAfter, sizeof(RENDER_SURFACE_STATE))); + + imageHw->appendSurfaceStateParams(&surfaceStateAfter); + + EXPECT_EQ(0, memcmp(&surfaceStateBefore, &surfaceStateAfter, sizeof(RENDER_SURFACE_STATE))); +} + +GEN12LPTEST_F(ImageClearColorFixture, givenImageForGen12LpWhenClearColorParametersAreSetThenClearColorSurfaceInSurfaceStateIsSet) { + this->setUpImpl(); + auto surfaceState = this->getSurfaceState(); + + surfaceState.setSurfaceBaseAddress(0xABCDEF1000); + + EXPECT_EQ(false, surfaceState.getClearValueAddressEnable()); + EXPECT_EQ(0u, surfaceState.getClearColorAddress()); + EXPECT_EQ(0u, surfaceState.getClearColorAddressHigh()); + + std::unique_ptr> imageHw(static_cast *>(ImageHelper::create(&context))); + auto gmm = imageHw->getGraphicsAllocation()->getDefaultGmm(); + gmm->gmmResourceInfo->getResourceFlags()->Gpu.IndirectClearColor = 1; + imageHw->setClearColorParams(&surfaceState, gmm); + + EXPECT_EQ(true, surfaceState.getClearValueAddressEnable()); + EXPECT_NE(0u, surfaceState.getClearColorAddress()); + EXPECT_NE(0u, surfaceState.getClearColorAddressHigh()); +} + +GEN12LPTEST_F(ImageClearColorFixture, givenImageForGen12LpWhenCanonicalAddresForClearColorIsUsedThenItsConvertedToNonCanonicalForm) { + this->setUpImpl(); + auto surfaceState = this->getSurfaceState(); + + uint64_t canonicalAddress = 0xffffABCDABCDE000; + + EXPECT_THROW(surfaceState.setClearColorAddressHigh(static_cast(canonicalAddress >> 32)), std::exception); + surfaceState.setSurfaceBaseAddress(canonicalAddress); + + std::unique_ptr> imageHw(static_cast *>(ImageHelper::create(&context))); + auto gmm = imageHw->getGraphicsAllocation()->getDefaultGmm(); + gmm->gmmResourceInfo->getResourceFlags()->Gpu.IndirectClearColor = 1; + EXPECT_NO_THROW(imageHw->setClearColorParams(&surfaceState, gmm)); + + uint64_t nonCanonicalAddress = ((static_cast(surfaceState.getClearColorAddressHigh()) << 32) | surfaceState.getClearColorAddress()); + EXPECT_EQ(GmmHelper::decanonize(canonicalAddress), nonCanonicalAddress); +} + +GEN12LPTEST_F(ImageClearColorFixture, givenMcsAllocationWhenSetArgIsCalledWithUnifiedAuxCapabilityAndMCSThenProgramAuxFieldsForCcs) { + this->setUpImpl(); + + using RENDER_SURFACE_STATE = typename FamilyType::RENDER_SURFACE_STATE; + using AUXILIARY_SURFACE_MODE = typename RENDER_SURFACE_STATE::AUXILIARY_SURFACE_MODE; + using SURFACE_TYPE = typename RENDER_SURFACE_STATE::SURFACE_TYPE; + std::unique_ptr context(new MockContext()); + McsSurfaceInfo msi = {10, 20, 3}; + auto mcsAlloc = context->getMemoryManager()->allocateGraphicsMemoryWithProperties(MockAllocationProperties{MemoryConstants::pageSize}); + + cl_image_desc imgDesc = Image2dDefaults::imageDesc; + imgDesc.num_samples = 8; + std::unique_ptr image(Image2dHelper<>::create(context.get(), &imgDesc)); + + auto surfaceState = FamilyType::cmdInitRenderSurfaceState; + auto imageHw = static_cast *>(image.get()); + mcsAlloc->setDefaultGmm(new Gmm(nullptr, 1, false)); + surfaceState.setSurfaceBaseAddress(0xABCDEF1000); + imageHw->setMcsSurfaceInfo(msi); + imageHw->setMcsAllocation(mcsAlloc); + auto mockResource = static_cast(mcsAlloc->getDefaultGmm()->gmmResourceInfo.get()); + mockResource->setUnifiedAuxTranslationCapable(); + mockResource->setMultisampleControlSurface(); + + EXPECT_EQ(0u, surfaceState.getAuxiliarySurfaceBaseAddress()); + + imageHw->setAuxParamsForMultisamples(&surfaceState); + + EXPECT_NE(0u, surfaceState.getAuxiliarySurfaceBaseAddress()); + EXPECT_EQ(surfaceState.getAuxiliarySurfaceMode(), AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_MCS_LCE); +} + +GEN12LPTEST_F(gen12LpImageTests, givenRenderCompressionSurfaceStateParamsAreSetForRenderCompression) { + MockContext context; + using RENDER_SURFACE_STATE = typename FamilyType::RENDER_SURFACE_STATE; + cl_image_desc imgDesc = Image2dDefaults::imageDesc; + imgDesc.num_samples = 8; + std::unique_ptr image(Image2dHelper<>::create(&context, &imgDesc)); + auto surfaceState = FamilyType::cmdInitRenderSurfaceState; + auto imageHw = static_cast *>(image.get()); + imageHw->getGraphicsAllocation()->getDefaultGmm()->gmmResourceInfo->getResourceFlags()->Info.RenderCompressed = true; + imageHw->setAuxParamsForCCS(&surfaceState, imageHw->getGraphicsAllocation()->getDefaultGmm()); + + EXPECT_FALSE(surfaceState.getMemoryCompressionEnable()); + EXPECT_EQ(surfaceState.getAuxiliarySurfaceMode(), RENDER_SURFACE_STATE::AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_CCS_E); +} + +GEN12LPTEST_F(gen12LpImageTests, givenMediaCompressionSurfaceStateParamsAreSetForMediaCompression) { + MockContext context; + using RENDER_SURFACE_STATE = typename FamilyType::RENDER_SURFACE_STATE; + cl_image_desc imgDesc = Image2dDefaults::imageDesc; + imgDesc.num_samples = 8; + std::unique_ptr image(Image2dHelper<>::create(&context, &imgDesc)); + auto surfaceState = FamilyType::cmdInitRenderSurfaceState; + auto imageHw = static_cast *>(image.get()); + imageHw->getGraphicsAllocation()->getDefaultGmm()->gmmResourceInfo->getResourceFlags()->Info.MediaCompressed = true; + surfaceState.setAuxiliarySurfaceMode(RENDER_SURFACE_STATE::AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_CCS_E); + imageHw->setAuxParamsForCCS(&surfaceState, imageHw->getGraphicsAllocation()->getDefaultGmm()); + + EXPECT_TRUE(surfaceState.getMemoryCompressionEnable()); + EXPECT_EQ(surfaceState.getAuxiliarySurfaceMode(), RENDER_SURFACE_STATE::AUXILIARY_SURFACE_MODE::AUXILIARY_SURFACE_MODE_AUX_NONE); +} diff --git a/unit_tests/gen12lp/kernel_tests_gen12lp.cpp b/unit_tests/gen12lp/kernel_tests_gen12lp.cpp new file mode 100644 index 0000000000..89c4877597 --- /dev/null +++ b/unit_tests/gen12lp/kernel_tests_gen12lp.cpp @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/helpers/hardware_commands_helper.h" +#include "test.h" +#include "unit_tests/fixtures/device_fixture.h" +#include "unit_tests/mocks/mock_kernel.h" + +using namespace NEO; + +using Gen12LpKernelTest = Test; +GEN12LPTEST_F(Gen12LpKernelTest, givenKernelWhenCanTransformImagesIsCalledThenReturnsTrue) { + MockKernelWithInternals mockKernel(*pDevice); + auto retVal = mockKernel.mockKernel->Kernel::canTransformImages(); + EXPECT_TRUE(retVal); +} +using Gen12LpHardwareCommandsTest = testing::Test; +GEN12LPTEST_F(Gen12LpHardwareCommandsTest, givenGen12LpPlatformWhenDoBindingTablePrefetchIsCalledThenReturnsTrue) { + EXPECT_FALSE(HardwareCommandsHelper::doBindingTablePrefetch()); +} diff --git a/unit_tests/gen12lp/profiling_tests_gen12lp.cpp b/unit_tests/gen12lp/profiling_tests_gen12lp.cpp new file mode 100644 index 0000000000..46c2d2fa2f --- /dev/null +++ b/unit_tests/gen12lp/profiling_tests_gen12lp.cpp @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_queue/command_queue_hw.h" +#include "runtime/command_queue/enqueue_common.h" +#include "test.h" +#include "unit_tests/command_queue/command_enqueue_fixture.h" +#include "unit_tests/mocks/mock_kernel.h" + +using namespace NEO; + +struct ProfilingTestsGen12LP : public CommandEnqueueFixture, + public ::testing::Test { + void SetUp() override { + CommandEnqueueFixture::SetUp(CL_QUEUE_PROFILING_ENABLE); + mockKernelWithInternals = std::make_unique(*pDevice, nullptr); + } + + void TearDown() override { + CommandEnqueueFixture::TearDown(); + } + + std::unique_ptr mockKernelWithInternals; +}; + +GEN12LPTEST_F(ProfilingTestsGen12LP, GivenCommandQueueWithProflingWhenWalkerIsDispatchedThenTwoMiStoreRegisterMemWithMmioRemapEnableArePresentInCS) { + typedef typename FamilyType::MI_STORE_REGISTER_MEM MI_STORE_REGISTER_MEM; + typedef typename FamilyType::GPGPU_WALKER GPGPU_WALKER; + + size_t globalOffsets[3] = {0, 0, 0}; + size_t workItems[3] = {1, 1, 1}; + uint32_t dimensions = 1; + cl_event event; + + static_cast *>(pCmdQ)->enqueueKernel( + *mockKernelWithInternals, + dimensions, + globalOffsets, + workItems, + nullptr, + 0, + nullptr, + &event); + + parseCommands(*pCmdQ); + + // Find GPGPU_WALKER + auto itorGPGPUWalkerCmd = find(cmdList.begin(), cmdList.end()); + GenCmdList::reverse_iterator rItorGPGPUWalkerCmd(itorGPGPUWalkerCmd); + ASSERT_NE(cmdList.end(), itorGPGPUWalkerCmd); + + // Check MI_STORE_REGISTER_MEMs + auto itorBeforeMI = reverse_find(rItorGPGPUWalkerCmd, cmdList.rbegin()); + ASSERT_NE(cmdList.rbegin(), itorBeforeMI); + auto pBeforeMI = genCmdCast(*itorBeforeMI); + pBeforeMI = genCmdCast(*itorBeforeMI); + ASSERT_NE(nullptr, pBeforeMI); + EXPECT_EQ(GP_THREAD_TIME_REG_ADDRESS_OFFSET_LOW, pBeforeMI->getRegisterAddress()); + EXPECT_TRUE(pBeforeMI->getMmioRemapEnable()); + + auto itorAfterMI = find(itorGPGPUWalkerCmd, cmdList.end()); + ASSERT_NE(cmdList.end(), itorAfterMI); + auto pAfterMI = genCmdCast(*itorAfterMI); + ASSERT_NE(nullptr, pAfterMI); + EXPECT_EQ(GP_THREAD_TIME_REG_ADDRESS_OFFSET_LOW, pAfterMI->getRegisterAddress()); + EXPECT_TRUE(pAfterMI->getMmioRemapEnable()); + + ++itorAfterMI; + pAfterMI = genCmdCast(*itorAfterMI); + EXPECT_EQ(nullptr, pAfterMI); + + clReleaseEvent(event); +} \ No newline at end of file diff --git a/unit_tests/gen12lp/sampler_tests_gen12lp.cpp b/unit_tests/gen12lp/sampler_tests_gen12lp.cpp new file mode 100644 index 0000000000..840ad08116 --- /dev/null +++ b/unit_tests/gen12lp/sampler_tests_gen12lp.cpp @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "core/unit_tests/helpers/debug_manager_state_restore.h" +#include "core/unit_tests/utilities/base_object_utils.h" +#include "runtime/os_interface/debug_settings_manager.h" +#include "runtime/sampler/sampler.h" +#include "test.h" +#include "unit_tests/fixtures/device_fixture.h" +#include "unit_tests/mocks/mock_context.h" + +#include + +using namespace NEO; + +typedef Test Gen12LpSamplerTest; + +TGLLPTEST_F(Gen12LpSamplerTest, givenTglLpSamplerWhenUsingDefaultFilteringAndAppendSamplerStateParamsThenDisableLowQualityFilter) { + EXPECT_FALSE(DebugManager.flags.ForceSamplerLowFilteringPrecision.get()); + typedef typename FamilyType::SAMPLER_STATE SAMPLER_STATE; + auto context = clUniquePtr(new MockContext()); + auto sampler = clUniquePtr(new SamplerHw(context.get(), CL_FALSE, CL_ADDRESS_NONE, CL_FILTER_NEAREST)); + auto state = FamilyType::cmdInitSamplerState; + EXPECT_EQ(SAMPLER_STATE::LOW_QUALITY_FILTER_DISABLE, state.getLowQualityFilter()); + sampler->appendSamplerStateParams(&state); + EXPECT_EQ(SAMPLER_STATE::LOW_QUALITY_FILTER_DISABLE, state.getLowQualityFilter()); +} + +TGLLPTEST_F(Gen12LpSamplerTest, givenTglLpSamplerWhenForcingLowQualityFilteringAndAppendSamplerStateParamsThenEnableLowQualityFilter) { + DebugManagerStateRestore dbgRestore; + DebugManager.flags.ForceSamplerLowFilteringPrecision.set(true); + EXPECT_TRUE(DebugManager.flags.ForceSamplerLowFilteringPrecision.get()); + typedef typename FamilyType::SAMPLER_STATE SAMPLER_STATE; + auto context = clUniquePtr(new MockContext()); + auto sampler = clUniquePtr(new SamplerHw(context.get(), CL_FALSE, CL_ADDRESS_NONE, CL_FILTER_NEAREST)); + auto state = FamilyType::cmdInitSamplerState; + EXPECT_EQ(SAMPLER_STATE::LOW_QUALITY_FILTER_DISABLE, state.getLowQualityFilter()); + sampler->appendSamplerStateParams(&state); + EXPECT_EQ(SAMPLER_STATE::LOW_QUALITY_FILTER_ENABLE, state.getLowQualityFilter()); +} + +GEN12LPTEST_F(Gen12LpSamplerTest, defaultLowQualityFilter) { + typedef typename FamilyType::SAMPLER_STATE SAMPLER_STATE; + auto state = FamilyType::cmdInitSamplerState; + EXPECT_EQ(SAMPLER_STATE::LOW_QUALITY_FILTER_DISABLE, state.getLowQualityFilter()); +} + +GEN12LPTEST_F(Gen12LpSamplerTest, givenGen12LpSamplerWhenProgrammingLowQualityCubeCornerModeThenTheModeChangesAppropriately) { + typedef typename FamilyType::SAMPLER_STATE SAMPLER_STATE; + auto state = FamilyType::cmdInitSamplerState; + EXPECT_EQ(SAMPLER_STATE::LOW_QUALITY_CUBE_CORNER_MODE_ENABLE, state.getLowQualityCubeCornerMode()); + state.setLowQualityCubeCornerMode(SAMPLER_STATE::LOW_QUALITY_CUBE_CORNER_MODE_DISABLE); + EXPECT_EQ(SAMPLER_STATE::LOW_QUALITY_CUBE_CORNER_MODE_DISABLE, state.getLowQualityCubeCornerMode()); +} diff --git a/unit_tests/gen12lp/scheduler_source_tests_gen12lp.cpp b/unit_tests/gen12lp/scheduler_source_tests_gen12lp.cpp new file mode 100644 index 0000000000..c975fbbf09 --- /dev/null +++ b/unit_tests/gen12lp/scheduler_source_tests_gen12lp.cpp @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/device_queue/device_queue_hw.h" +#include "runtime/gen12lp/hw_cmds.h" + +// Keep the order of device_enqueue.h and scheduler_definitions.h as the latter uses defines from the first one +#include "runtime/gen12lp/device_enqueue.h" +#include "runtime/gen12lp/scheduler_definitions.h" +#include "unit_tests/scheduler/scheduler_source_tests.h" +// Keep this include below scheduler_definitions.h and device_enqueue.h headers as it depends on defines defined in them +#include "unit_tests/scheduler/scheduler_source_tests.inl" + +using namespace NEO; + +typedef SchedulerSourceTest SchedulerSourceTestGen12; +GEN12LPTEST_F(SchedulerSourceTestGen12, GivenDeviceQueueWhenCommandsSizeIsCalculatedThenItEqualsSpaceForEachEnqueueInSchedulerKernelCode) { + givenDeviceQueueWhenCommandsSizeIsCalculatedThenItEqualsSpaceForEachEnqueueInSchedulerKernelCodeTest(); +} + +GEN12LPTEST_F(SchedulerSourceTestGen12, GivenDeviceQueueWhenSlbDummyCommandsAreBuildThenSizeUsedIsCorrect) { + givenDeviceQueueWhenSlbDummyCommandsAreBuildThenSizeUsedIsCorrectTest(); +} + +GEN12LPTEST_F(SchedulerSourceTestGen12, GivenDeviceQueueThenNumberOfEnqueuesEqualsNumberOfEnqueuesInSchedulerKernelCode) { + givenDeviceQueueThenNumberOfEnqueuesEqualsNumberOfEnqueuesInSchedulerKernelCodeTest(); +} diff --git a/unit_tests/gen12lp/tbx_command_stream_receiver_tests_gen12lp.cpp b/unit_tests/gen12lp/tbx_command_stream_receiver_tests_gen12lp.cpp new file mode 100644 index 0000000000..2d4a1581f0 --- /dev/null +++ b/unit_tests/gen12lp/tbx_command_stream_receiver_tests_gen12lp.cpp @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/aub_mem_dump/page_table_entry_bits.h" +#include "runtime/command_stream/tbx_command_stream_receiver_hw.h" +#include "test.h" +#include "unit_tests/fixtures/device_fixture.h" +#include "unit_tests/mocks/mock_graphics_allocation.h" + +using namespace NEO; + +using Gen12LPTbxCommandStreamReceiverTests = Test; + +GEN12LPTEST_F(Gen12LPTbxCommandStreamReceiverTests, givenNullPtrGraphicsAlloctionWhenGetPPGTTAdditionalBitsIsCalledThenAppropriateValueIsReturned) { + auto tbxCsr = std::make_unique>(*pDevice->executionEnvironment); + GraphicsAllocation *allocation = nullptr; + auto bits = tbxCsr->getPPGTTAdditionalBits(allocation); + constexpr uint64_t expectedBits = BIT(PageTableEntry::presentBit) | BIT(PageTableEntry::writableBit); + + EXPECT_EQ(expectedBits, bits); +} + +GEN12LPTEST_F(Gen12LPTbxCommandStreamReceiverTests, givenGraphicsAlloctionWWhenGetPPGTTAdditionalBitsIsCalledThenAppropriateValueIsReturned) { + auto tbxCsr = std::make_unique>(*pDevice->executionEnvironment); + MockGraphicsAllocation allocation(nullptr, 0); + auto bits = tbxCsr->getPPGTTAdditionalBits(&allocation); + constexpr uint64_t expectedBits = BIT(PageTableEntry::presentBit) | BIT(PageTableEntry::writableBit); + + EXPECT_EQ(expectedBits, bits); +} + +GEN12LPTEST_F(Gen12LPTbxCommandStreamReceiverTests, whenAskedForPollForCompletionParametersThenReturnCorrectValues) { + class MyMockTbxHw : public TbxCommandStreamReceiverHw { + public: + MyMockTbxHw(ExecutionEnvironment &executionEnvironment) + : TbxCommandStreamReceiverHw(executionEnvironment) {} + using TbxCommandStreamReceiverHw::getpollNotEqualValueForPollForCompletion; + using TbxCommandStreamReceiverHw::getMaskAndValueForPollForCompletion; + }; + + MyMockTbxHw myMockTbxHw(*pDevice->executionEnvironment); + EXPECT_EQ(0x80u, myMockTbxHw.getMaskAndValueForPollForCompletion()); + EXPECT_TRUE(myMockTbxHw.getpollNotEqualValueForPollForCompletion()); +} diff --git a/unit_tests/gen12lp/test_device_caps_gen12lp.cpp b/unit_tests/gen12lp/test_device_caps_gen12lp.cpp new file mode 100644 index 0000000000..1e9072c521 --- /dev/null +++ b/unit_tests/gen12lp/test_device_caps_gen12lp.cpp @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/helpers/hw_helper.h" +#include "test.h" +#include "unit_tests/fixtures/device_fixture.h" + +using namespace NEO; + +typedef Test Gen12LpDeviceCaps; + +GEN12LPTEST_F(Gen12LpDeviceCaps, reportsOcl21) { + const auto &caps = pDevice->getDeviceInfo(); + EXPECT_STREQ("OpenCL 2.1 NEO ", caps.clVersion); + EXPECT_STREQ("OpenCL C 2.0 ", caps.clCVersion); +} + +TGLLPTEST_F(Gen12LpDeviceCaps, lpSkusDontSupportFP64) { + const auto &caps = pDevice->getDeviceInfo(); + std::string extensionString = caps.deviceExtensions; + + EXPECT_EQ(std::string::npos, extensionString.find(std::string("cl_khr_fp64"))); + EXPECT_EQ(0u, caps.doubleFpConfig); +} + +TGLLPTEST_F(Gen12LpDeviceCaps, allSkusSupportCorrectlyRoundedDivideSqrt) { + const auto &caps = pDevice->getDeviceInfo(); + EXPECT_EQ(0u, caps.singleFpConfig & CL_FP_CORRECTLY_ROUNDED_DIVIDE_SQRT); +} + +GEN12LPTEST_F(Gen12LpDeviceCaps, defaultPreemptionMode) { + EXPECT_EQ(PreemptionMode::ThreadGroup, pDevice->getHardwareInfo().capabilityTable.defaultPreemptionMode); +} + +GEN12LPTEST_F(Gen12LpDeviceCaps, profilingTimerResolution) { + const auto &caps = pDevice->getDeviceInfo(); + EXPECT_EQ(83u, caps.outProfilingTimerResolution); +} + +GEN12LPTEST_F(Gen12LpDeviceCaps, kmdNotifyMechanism) { + EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.enableKmdNotify); + EXPECT_EQ(0, pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.delayKmdNotifyMicroseconds); + EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.enableQuickKmdSleep); + EXPECT_EQ(0, pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.delayQuickKmdSleepMicroseconds); + EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.enableQuickKmdSleepForSporadicWaits); + EXPECT_EQ(0, pDevice->getHardwareInfo().capabilityTable.kmdNotifyProperties.delayQuickKmdSleepForSporadicWaitsMicroseconds); +} + +GEN12LPTEST_F(Gen12LpDeviceCaps, compression) { + EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.ftrRenderCompressedBuffers); + EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.ftrRenderCompressedImages); +} + +GEN12LPTEST_F(Gen12LpDeviceCaps, givenHwInfoWhenRequestedComputeUnitsUsedForScratchThenReturnValidValue) { + const auto &hwInfo = pDevice->getHardwareInfo(); + auto &hwHelper = HwHelper::get(hwInfo.platform.eRenderCoreFamily); + + uint32_t expectedValue = hwInfo.gtSystemInfo.MaxSubSlicesSupported * hwInfo.gtSystemInfo.MaxEuPerSubSlice * 8; + + EXPECT_EQ(expectedValue, hwHelper.getComputeUnitsUsedForScratch(&hwInfo)); + EXPECT_EQ(expectedValue, pDevice->getDeviceInfo().computeUnitsUsedForScratch); +} + +GEN12LPTEST_F(Gen12LpDeviceCaps, givenHwInfoWhenSlmSizeIsRequiredThenReturnCorrectValue) { + EXPECT_EQ(64u, pDevice->getHardwareInfo().capabilityTable.slmSize); +} + +GEN12LPTEST_F(Gen12LpDeviceCaps, givenGen12LpWhenCheckBlitterOperationsSupportThenReturnFalse) { + EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.blitterOperationsSupported); +} + +TGLLPTEST_F(Gen12LpDeviceCaps, givenTglLpWhenCheckSupportCacheFlushAfterWalkerThenFalse) { + EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.supportCacheFlushAfterWalker); +} + +using TglLpUsDeviceIdTest = Test; + +TGLLPTEST_F(TglLpUsDeviceIdTest, isSimulationCap) { + unsigned short tglLpSimulationIds[2] = { + IGEN12LP_GT1_MOB_DEVICE_F0_ID, + 0, // default, non-simulation + }; + NEO::MockDevice *mockDevice = nullptr; + + for (auto id : tglLpSimulationIds) { + mockDevice = createWithUsDeviceId(id); + ASSERT_NE(mockDevice, nullptr); + + if (id == 0) + EXPECT_FALSE(mockDevice->isSimulation()); + else + EXPECT_TRUE(mockDevice->isSimulation()); + delete mockDevice; + } +} + +TGLLPTEST_F(TglLpUsDeviceIdTest, GivenTGLLPWhenCheckftr64KBpagesThenTrue) { + EXPECT_TRUE(pDevice->getHardwareInfo().capabilityTable.ftr64KBpages); +} + +TGLLPTEST_F(TglLpUsDeviceIdTest, givenGen12lpWhenCheckFtrSupportsInteger64BitAtomicsThenReturnTrue) { + EXPECT_FALSE(pDevice->getHardwareInfo().capabilityTable.ftrSupportsInteger64BitAtomics); +} diff --git a/unit_tests/gen12lp/test_device_queue_hw_gen12lp.cpp b/unit_tests/gen12lp/test_device_queue_hw_gen12lp.cpp new file mode 100644 index 0000000000..7ce439d372 --- /dev/null +++ b/unit_tests/gen12lp/test_device_queue_hw_gen12lp.cpp @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_queue/gpgpu_walker.h" +#include "runtime/context/context.h" +#include "runtime/utilities/tag_allocator.h" +#include "unit_tests/fixtures/device_host_queue_fixture.h" +#include "unit_tests/helpers/hw_parse.h" +#include "unit_tests/mocks/mock_device_queue.h" +#include "unit_tests/mocks/mock_kernel.h" + +using namespace NEO; +using namespace DeviceHostQueue; + +typedef DeviceQueueHwTest Gen12LpDeviceQueueSlb; + +GEN12LPTEST_F(Gen12LpDeviceQueueSlb, expectedAllocationSize) { + deviceQueue = createQueueObject(); + ASSERT_NE(deviceQueue, nullptr); + + auto expectedSize = getMinimumSlbSize(); + expectedSize *= 128; //num of enqueues + expectedSize += sizeof(typename FamilyType::MI_BATCH_BUFFER_START); + expectedSize = alignUp(expectedSize, MemoryConstants::pageSize); + expectedSize += MockDeviceQueueHw::getExecutionModelCleanupSectionSize(); + expectedSize += (4 * MemoryConstants::pageSize); + expectedSize = alignUp(expectedSize, MemoryConstants::pageSize); + + ASSERT_NE(deviceQueue->getSlbBuffer(), nullptr); + EXPECT_EQ(deviceQueue->getSlbBuffer()->getUnderlyingBufferSize(), expectedSize); + + delete deviceQueue; +} + +GEN12LPTEST_F(Gen12LpDeviceQueueSlb, SlbCommandsWa) { + auto mockDeviceQueueHw = new MockDeviceQueueHw(pContext, device, + DeviceHostQueue::deviceQueueProperties::minimumProperties[0]); + EXPECT_FALSE(mockDeviceQueueHw->arbCheckWa); + EXPECT_FALSE(mockDeviceQueueHw->pipeControlWa); + EXPECT_FALSE(mockDeviceQueueHw->miAtomicWa); + EXPECT_FALSE(mockDeviceQueueHw->lriWa); + + delete mockDeviceQueueHw; +} + +GEN12LPTEST_F(Gen12LpDeviceQueueSlb, givenDeviceCommandQueueWithProfilingWhenBatchBufferIsBuiltThenOneMiStoreRegisterMemWithMmioRemapEnableIsPresent) { + using MI_BATCH_BUFFER_START = typename FamilyType::MI_BATCH_BUFFER_START; + using MI_STORE_REGISTER_MEM = typename FamilyType::MI_STORE_REGISTER_MEM; + + auto mockDeviceQueueHw = new MockDeviceQueueHw(pContext, device, deviceQueueProperties::minimumProperties[0]); + auto commandsSize = mockDeviceQueueHw->getMinimumSlbSize() + mockDeviceQueueHw->getWaCommandsSize(); + MockParentKernel *mockParentKernel = MockParentKernel::create(*pContext); + uint32_t taskCount = 7; + + auto hwTimeStamp = pCommandQueue->getGpgpuCommandStreamReceiver().getEventTsAllocator()->getTag(); + mockDeviceQueueHw->buildSlbDummyCommands(); + mockDeviceQueueHw->addExecutionModelCleanUpSection(mockParentKernel, hwTimeStamp, 0x123, taskCount); + + HardwareParse hwParser; + auto *slbCS = mockDeviceQueueHw->getSlbCS(); + size_t cleanupSectionOffset = alignUp(mockDeviceQueueHw->numberOfDeviceEnqueues * commandsSize + sizeof(MI_BATCH_BUFFER_START), MemoryConstants::pageSize); + size_t cleanupSectionOffsetToParse = cleanupSectionOffset; + + hwParser.parseCommands(*slbCS, cleanupSectionOffsetToParse); + hwParser.findHardwareCommands(); + + auto itorMiStore = find(hwParser.cmdList.begin(), hwParser.cmdList.end()); + ASSERT_NE(hwParser.cmdList.end(), itorMiStore); + auto pMiStore = genCmdCast(*itorMiStore); + ASSERT_NE(nullptr, pMiStore); + EXPECT_EQ(GP_THREAD_TIME_REG_ADDRESS_OFFSET_LOW, pMiStore->getRegisterAddress()); + EXPECT_TRUE(pMiStore->getMmioRemapEnable()); + + ++itorMiStore; + pMiStore = genCmdCast(*itorMiStore); + EXPECT_EQ(nullptr, pMiStore); + + delete mockParentKernel; + delete mockDeviceQueueHw; +} diff --git a/unit_tests/gen12lp/test_platform_caps_gen12lp.cpp b/unit_tests/gen12lp/test_platform_caps_gen12lp.cpp new file mode 100644 index 0000000000..2393676144 --- /dev/null +++ b/unit_tests/gen12lp/test_platform_caps_gen12lp.cpp @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/helpers/options.h" +#include "test.h" +#include "unit_tests/fixtures/platform_fixture.h" + +using namespace NEO; + +struct Gen12LpPlatformCaps : public PlatformFixture, public ::testing::Test { + void SetUp() override { + PlatformFixture::SetUp(); + } + + void TearDown() override { + PlatformFixture::TearDown(); + } +}; + +TGLLPTEST_F(Gen12LpPlatformCaps, lpSkusDontSupportFP64) { + const auto &caps = pPlatform->getPlatformInfo(); + + EXPECT_EQ(std::string::npos, caps.extensions.find(std::string("cl_khr_fp64"))); +} diff --git a/unit_tests/gen12lp/test_preamble_gen12lp.cpp b/unit_tests/gen12lp/test_preamble_gen12lp.cpp new file mode 100644 index 0000000000..2ade26d674 --- /dev/null +++ b/unit_tests/gen12lp/test_preamble_gen12lp.cpp @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/command_stream/preemption.h" +#include "unit_tests/preamble/preamble_fixture.h" + +#include "reg_configs_common.h" + +using namespace NEO; + +typedef PreambleFixture TglLpSlm; + +TGLLPTEST_F(TglLpSlm, givenTglLpWhenPreambleIsBeingProgrammedThenThreadArbitrationPolicyIsIgnored) { + typedef TGLLPFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM; + LinearStream &cs = linearStream; + uint32_t l3Config = PreambleHelper::getL3Config(pDevice->getHardwareInfo(), true); + MockDevice mockDevice; + PreambleHelper::programPreamble(&linearStream, mockDevice, l3Config, + ThreadArbitrationPolicy::RoundRobin, + nullptr, nullptr); + + parseCommands(cs); + + // parse through commands and ensure that 0xE404 is not being programmed + EXPECT_EQ(0U, countMmio(cmdList.begin(), cmdList.end(), 0xE404)); +} + +TGLLPTEST_F(TglLpSlm, givenTglLpIsL3Programing) { + bool isL3Programmable = + PreambleHelper::isL3Configurable(**platformDevices); + + EXPECT_FALSE(isL3Programmable); +} + +TGLLPTEST_F(TglLpSlm, shouldNotBeEnabledOnGen12) { + typedef TGLLPFamily::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM; + LinearStream &cs = linearStream; + uint32_t l3Config = PreambleHelper::getL3Config(pDevice->getHardwareInfo(), true); + PreambleHelper::programL3(&cs, l3Config); + + parseCommands(cs); + + auto itorLRI = find(cmdList.begin(), cmdList.end()); + ASSERT_EQ(cmdList.end(), itorLRI); +} + +typedef PreambleFixture Gen12LpUrbEntryAllocationSize; +TGLLPTEST_F(Gen12LpUrbEntryAllocationSize, getUrbEntryAllocationSize) { + uint32_t actualVal = PreambleHelper::getUrbEntryAllocationSize(); + EXPECT_EQ(1024u, actualVal); +} + +typedef PreambleVfeState Gen12LpPreambleVfeState; +TGLLPTEST_F(Gen12LpPreambleVfeState, WaOff) { + typedef typename FamilyType::PIPE_CONTROL PIPE_CONTROL; + testWaTable->waSendMIFLUSHBeforeVFE = 0; + LinearStream &cs = linearStream; + PreambleHelper::programVFEState(&linearStream, *pPlatform->peekExecutionEnvironment()->getHardwareInfo(), 0, 0, 672u); + + parseCommands(cs); + + auto itorPC = find(cmdList.begin(), cmdList.end()); + ASSERT_NE(cmdList.end(), itorPC); + + const auto &pc = *reinterpret_cast(*itorPC); + EXPECT_FALSE(pc.getRenderTargetCacheFlushEnable()); + EXPECT_FALSE(pc.getDepthCacheFlushEnable()); + EXPECT_FALSE(pc.getDcFlushEnable()); + EXPECT_EQ(1u, pc.getCommandStreamerStallEnable()); +} + +TGLLPTEST_F(Gen12LpPreambleVfeState, givenCcsEngineWhenWaIsSetThenAppropriatePipeControlFlushesAreSet) { + typedef typename FamilyType::PIPE_CONTROL PIPE_CONTROL; + testWaTable->waSendMIFLUSHBeforeVFE = 1; + LinearStream &cs = linearStream; + + EXPECT_EQ(aub_stream::ENGINE_CCS, platformDevices[0]->capabilityTable.defaultEngineType); + + PreambleHelper::programVFEState(&linearStream, *pPlatform->peekExecutionEnvironment()->getHardwareInfo(), 0, 0, 672u); + + parseCommands(cs); + + auto itorPC = find(cmdList.begin(), cmdList.end()); + ASSERT_NE(cmdList.end(), itorPC); + + const auto &pc = *reinterpret_cast(*itorPC); + EXPECT_FALSE(pc.getRenderTargetCacheFlushEnable()); + EXPECT_FALSE(pc.getDepthCacheFlushEnable()); + EXPECT_TRUE(pc.getDcFlushEnable()); + EXPECT_EQ(1u, pc.getCommandStreamerStallEnable()); +} + +TGLLPTEST_F(Gen12LpPreambleVfeState, givenRcsEngineWhenWaIsSetThenAppropriatePipeControlFlushesAreSet) { + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + testWaTable->waSendMIFLUSHBeforeVFE = 1; + LinearStream &cs = linearStream; + + HardwareInfo hwInfo = const_cast(pPlatform->getDevice(0)->getHardwareInfo()); + hwInfo.capabilityTable.defaultEngineType = aub_stream::ENGINE_RCS; + + PreambleHelper::programVFEState(&linearStream, hwInfo, 0, 0, 672u); + + parseCommands(cs); + + auto itorPC = find(cmdList.begin(), cmdList.end()); + ASSERT_NE(cmdList.end(), itorPC); + + const auto &pc = *reinterpret_cast(*itorPC); + EXPECT_TRUE(pc.getRenderTargetCacheFlushEnable()); + EXPECT_TRUE(pc.getDepthCacheFlushEnable()); + EXPECT_TRUE(pc.getDcFlushEnable()); + EXPECT_EQ(1u, pc.getCommandStreamerStallEnable()); +} + +TGLLPTEST_F(Gen12LpPreambleVfeState, givenDefaultPipeControlWhenItIsProgrammedThenCsStallBitIsSet) { + using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL; + + PIPE_CONTROL *pipeControl = static_cast(linearStream.getSpace(sizeof(PIPE_CONTROL))); + *pipeControl = FamilyType::cmdInitPipeControl; + + EXPECT_EQ(1u, pipeControl->getCommandStreamerStallEnable()); +} + +typedef PreambleFixture ThreadArbitrationGen12Lp; +GEN12LPTEST_F(ThreadArbitrationGen12Lp, givenPolicyWhenThreadArbitrationProgrammedThenDoNothing) { + LinearStream &cs = linearStream; + + PreambleHelper::programThreadArbitration(&cs, ThreadArbitrationPolicy::RoundRobin); + + EXPECT_EQ(0u, cs.getUsed()); + EXPECT_EQ(0u, PreambleHelper::getDefaultThreadArbitrationPolicy()); +} + +typedef PreambleFixture PreemptionWatermarkGen12LP; +GEN12LPTEST_F(PreemptionWatermarkGen12LP, givenPreambleThenPreambleWorkAroundsIsNotProgrammed) { + MockDevice mockDevice; + PreambleHelper::programGenSpecificPreambleWorkArounds(&linearStream, pDevice->getHardwareInfo()); + + parseCommands(linearStream); + + auto cmd = findMmioCmd(cmdList.begin(), cmdList.end(), FfSliceCsChknReg2::address); + ASSERT_EQ(nullptr, cmd); + + size_t expectedSize = PreemptionHelper::getRequiredPreambleSize(MockDevice()); + EXPECT_EQ(expectedSize, PreambleHelper::getAdditionalCommandsSize(MockDevice())); +} diff --git a/unit_tests/gen12lp/test_preemption_gen12lp.cpp b/unit_tests/gen12lp/test_preemption_gen12lp.cpp new file mode 100644 index 0000000000..befdeef83c --- /dev/null +++ b/unit_tests/gen12lp/test_preemption_gen12lp.cpp @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "unit_tests/fixtures/preemption_fixture.h" +#include "unit_tests/mocks/mock_buffer.h" +#include "unit_tests/mocks/mock_command_queue.h" +#include "unit_tests/mocks/mock_csr.h" + +using namespace NEO; + +using Gen12LpPreemptionTests = DevicePreemptionTests; + +template <> +PreemptionTestHwDetails GetPreemptionTestHwDetails() { + PreemptionTestHwDetails ret; + ret.defaultRegValue = 0; + ret.regAddress = 0u; + return ret; +} + +GEN12LPTEST_F(Gen12LpPreemptionTests, whenProgramStateSipIsCalledThenStateSipCmdIsNotAddedToStream) { + size_t requiredSize = PreemptionHelper::getRequiredStateSipCmdSize(*device); + EXPECT_EQ(0U, requiredSize); + + LinearStream cmdStream{nullptr, 0}; + PreemptionHelper::programStateSip(cmdStream, *device); + EXPECT_EQ(0U, cmdStream.getUsed()); +} + +GEN12LPTEST_F(Gen12LpPreemptionTests, getRequiredCmdQSize) { + size_t expectedSize = 0; + EXPECT_EQ(expectedSize, PreemptionHelper::getPreemptionWaCsSize(*device)); +} + +GEN12LPTEST_F(Gen12LpPreemptionTests, applyPreemptionWaCmds) { + size_t usedSize = 0; + auto &cmdStream = cmdQ->getCS(0); + + PreemptionHelper::applyPreemptionWaCmdsBegin(&cmdStream, *device); + EXPECT_EQ(usedSize, cmdStream.getUsed()); + PreemptionHelper::applyPreemptionWaCmdsEnd(&cmdStream, *device); + EXPECT_EQ(usedSize, cmdStream.getUsed()); +} + +GEN12LPTEST_F(Gen12LpPreemptionTests, givenInterfaceDescriptorDataWhenMidThreadPreemptionModeThenSetDisableThreadPreemptionBitToDisable) { + using INTERFACE_DESCRIPTOR_DATA = typename FamilyType::INTERFACE_DESCRIPTOR_DATA; + + INTERFACE_DESCRIPTOR_DATA iddArg; + iddArg = FamilyType::cmdInitInterfaceDescriptorData; + + iddArg.setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_ENABLE); + + PreemptionHelper::programInterfaceDescriptorDataPreemption(&iddArg, PreemptionMode::MidThread); + EXPECT_EQ(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_DISABLE, iddArg.getThreadPreemptionDisable()); +} + +GEN12LPTEST_F(Gen12LpPreemptionTests, givenInterfaceDescriptorDataWhenNoMidThreadPreemptionModeThenSetDisableThreadPreemptionBitToEnable) { + using INTERFACE_DESCRIPTOR_DATA = typename FamilyType::INTERFACE_DESCRIPTOR_DATA; + + INTERFACE_DESCRIPTOR_DATA iddArg; + iddArg = FamilyType::cmdInitInterfaceDescriptorData; + + iddArg.setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_DISABLE); + + PreemptionHelper::programInterfaceDescriptorDataPreemption(&iddArg, PreemptionMode::Disabled); + EXPECT_EQ(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_ENABLE, iddArg.getThreadPreemptionDisable()); + + iddArg.setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_DISABLE); + + PreemptionHelper::programInterfaceDescriptorDataPreemption(&iddArg, PreemptionMode::MidBatch); + EXPECT_EQ(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_ENABLE, iddArg.getThreadPreemptionDisable()); + + iddArg.setThreadPreemptionDisable(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_DISABLE); + + PreemptionHelper::programInterfaceDescriptorDataPreemption(&iddArg, PreemptionMode::ThreadGroup); + EXPECT_EQ(INTERFACE_DESCRIPTOR_DATA::THREAD_PREEMPTION_DISABLE_ENABLE, iddArg.getThreadPreemptionDisable()); +} diff --git a/unit_tests/gen12lp/test_sample_gen12lp.cpp b/unit_tests/gen12lp/test_sample_gen12lp.cpp new file mode 100644 index 0000000000..bbb9cde9d1 --- /dev/null +++ b/unit_tests/gen12lp/test_sample_gen12lp.cpp @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "test.h" +#include "unit_tests/fixtures/device_fixture.h" + +using namespace NEO; + +typedef Test TigerlakeLpOnlyTest; + +TGLLPTEST_F(TigerlakeLpOnlyTest, shouldPassOnTglLp) { + EXPECT_EQ(IGFX_TIGERLAKE_LP, pDevice->getHardwareInfo().platform.eProductFamily); +} + +typedef Test Gen12LpOnlyTeset; + +GEN12LPTEST_F(Gen12LpOnlyTeset, shouldPassOnGen12) { + EXPECT_NE(IGFX_GEN9_CORE, pDevice->getRenderCoreFamily()); + EXPECT_NE(IGFX_GEN11_CORE, pDevice->getRenderCoreFamily()); + EXPECT_EQ(IGFX_GEN12LP_CORE, pDevice->getRenderCoreFamily()); +} diff --git a/unit_tests/gen12lp/tgllp/CMakeLists.txt b/unit_tests/gen12lp/tgllp/CMakeLists.txt new file mode 100644 index 0000000000..a9a665346d --- /dev/null +++ b/unit_tests/gen12lp/tgllp/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (C) 2019 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +if(TESTS_TGLLP) + set(IGDRCL_SRCS_tests_gen12lp_tgllp + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/test_hw_info_config_tgllp.cpp + ) + target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen12lp_tgllp}) + add_subdirectories() +endif() diff --git a/unit_tests/gen12lp/tgllp/linux/CMakeLists.txt b/unit_tests/gen12lp/tgllp/linux/CMakeLists.txt new file mode 100644 index 0000000000..d4b5dad080 --- /dev/null +++ b/unit_tests/gen12lp/tgllp/linux/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (C) 2019 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +set(IGDRCL_SRCS_tests_gen12lp_tgllp_linux + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt +) +if(UNIX) + target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen12lp_tgllp_linux}) + add_subdirectories() +endif() diff --git a/unit_tests/gen12lp/tgllp/linux/dll/CMakeLists.txt b/unit_tests/gen12lp/tgllp/linux/dll/CMakeLists.txt new file mode 100644 index 0000000000..c9f7f5bdad --- /dev/null +++ b/unit_tests/gen12lp/tgllp/linux/dll/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (C) 2019 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +set(IGDRCL_SRCS_linux_dll_tests_gen12lp_tgllp + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/device_id_tests_tgllp.cpp +) +target_sources(igdrcl_linux_dll_tests PRIVATE ${IGDRCL_SRCS_linux_dll_tests_gen12lp_tgllp}) diff --git a/unit_tests/gen12lp/tgllp/linux/dll/device_id_tests_tgllp.cpp b/unit_tests/gen12lp/tgllp/linux/dll/device_id_tests_tgllp.cpp new file mode 100644 index 0000000000..b228b8b80b --- /dev/null +++ b/unit_tests/gen12lp/tgllp/linux/dll/device_id_tests_tgllp.cpp @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/os_interface/linux/drm_neo.h" +#include "test.h" + +#include "hw_cmds.h" + +#include + +using namespace NEO; + +TEST(TglLpDeviceIdTest, supportedDeviceId) { + std::array expectedDescriptors = {{ + {IGEN12LP_GT1_MOB_DEVICE_F0_ID, &TGLLP_1x6x16::hwInfo, &TGLLP_1x6x16::setupHardwareInfo, GTTYPE_GT2}, + {ITGL_LP_1x6x16_ULT_15W_DEVICE_F0_ID, &TGLLP_1x6x16::hwInfo, &TGLLP_1x6x16::setupHardwareInfo, GTTYPE_GT2}, + }}; + + auto compareStructs = [](const DeviceDescriptor *first, const DeviceDescriptor *second) { + return first->deviceId == second->deviceId && first->pHwInfo == second->pHwInfo && + first->setupHardwareInfo == second->setupHardwareInfo && first->eGtType == second->eGtType; + }; + + size_t startIndex = 0; + while (!compareStructs(&expectedDescriptors[0], &deviceDescriptorTable[startIndex]) && + deviceDescriptorTable[startIndex].deviceId != 0) { + startIndex++; + }; + EXPECT_NE(0u, deviceDescriptorTable[startIndex].deviceId); + + for (auto &expected : expectedDescriptors) { + EXPECT_TRUE(compareStructs(&expected, &deviceDescriptorTable[startIndex])); + startIndex++; + } +} diff --git a/unit_tests/gen12lp/tgllp/test_hw_info_config_tgllp.cpp b/unit_tests/gen12lp/tgllp/test_hw_info_config_tgllp.cpp new file mode 100644 index 0000000000..c03195c30a --- /dev/null +++ b/unit_tests/gen12lp/tgllp/test_hw_info_config_tgllp.cpp @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "test.h" + +using namespace NEO; + +TEST(TgllpHwInfoConfig, givenHwInfoConfigStringThenAfterSetupResultingHwInfoIsCorrect) { + if (IGFX_TIGERLAKE_LP != productFamily) { + return; + } + HardwareInfo hwInfo; + GT_SYSTEM_INFO >SystemInfo = hwInfo.gtSystemInfo; + + std::string strConfig = "1x6x16"; + hardwareInfoSetup[productFamily](&hwInfo, false, strConfig); + EXPECT_EQ(1u, gtSystemInfo.SliceCount); + EXPECT_EQ(6u, gtSystemInfo.SubSliceCount); + EXPECT_EQ(96u, gtSystemInfo.EUCount); + + strConfig = "default"; + gtSystemInfo = {0}; + hardwareInfoSetup[productFamily](&hwInfo, false, strConfig); + EXPECT_EQ(1u, gtSystemInfo.SliceCount); + EXPECT_EQ(6u, gtSystemInfo.SubSliceCount); + EXPECT_EQ(96u, gtSystemInfo.EUCount); + + strConfig = "erroneous"; + gtSystemInfo = {0}; + EXPECT_ANY_THROW(hardwareInfoSetup[productFamily](&hwInfo, false, strConfig)); + EXPECT_EQ(0u, gtSystemInfo.SliceCount); + EXPECT_EQ(0u, gtSystemInfo.SubSliceCount); + EXPECT_EQ(0u, gtSystemInfo.EUCount); +} + +using TgllpHwInfo = ::testing::Test; + +TGLLPTEST_F(TgllpHwInfo, givenBoolWhenCallTgllpHardwareInfoSetupThenFeatureTableAndWorkaroundTableAreSetCorrect) { + static bool boolValue[]{ + true, false}; + HardwareInfo hwInfo; + GT_SYSTEM_INFO >SystemInfo = hwInfo.gtSystemInfo; + FeatureTable &featureTable = hwInfo.featureTable; + WorkaroundTable &workaroundTable = hwInfo.workaroundTable; + + std::string strConfig = "1x6x16"; + for (auto setParamBool : boolValue) { + + gtSystemInfo = {0}; + featureTable = {}; + workaroundTable = {}; + hardwareInfoSetup[productFamily](&hwInfo, setParamBool, strConfig); + + EXPECT_EQ(setParamBool, featureTable.ftrL3IACoherency); + EXPECT_EQ(setParamBool, featureTable.ftrPPGTT); + EXPECT_EQ(setParamBool, featureTable.ftrSVM); + EXPECT_EQ(setParamBool, featureTable.ftrIA32eGfxPTEs); + EXPECT_EQ(setParamBool, featureTable.ftrStandardMipTailFormat); + EXPECT_EQ(setParamBool, featureTable.ftrTranslationTable); + EXPECT_EQ(setParamBool, featureTable.ftrUserModeTranslationTable); + EXPECT_EQ(setParamBool, featureTable.ftrTileMappedResource); + EXPECT_EQ(setParamBool, featureTable.ftrEnableGuC); + EXPECT_EQ(setParamBool, featureTable.ftrFbc); + EXPECT_EQ(setParamBool, featureTable.ftrFbc2AddressTranslation); + EXPECT_EQ(setParamBool, featureTable.ftrFbcBlitterTracking); + EXPECT_EQ(setParamBool, featureTable.ftrFbcCpuTracking); + EXPECT_EQ(setParamBool, featureTable.ftrTileY); + EXPECT_EQ(setParamBool, featureTable.ftrAstcHdr2D); + EXPECT_EQ(setParamBool, featureTable.ftrAstcLdr2D); + + EXPECT_EQ(setParamBool, workaroundTable.wa4kAlignUVOffsetNV12LinearSurface); + EXPECT_EQ(setParamBool, workaroundTable.waEnablePreemptionGranularityControlByUMD); + EXPECT_EQ(setParamBool, workaroundTable.waUntypedBufferCompression); + } +} + +TGLLPTEST_F(TgllpHwInfo, givenHwInfoConfigStringThenAfterSetupResultingVmeIsDisabled) { + HardwareInfo hwInfo; + + std::string strConfig = "1x6x16"; + hardwareInfoSetup[productFamily](&hwInfo, false, strConfig); + EXPECT_FALSE(hwInfo.capabilityTable.ftrSupportsVmeAvcTextureSampler); + EXPECT_FALSE(hwInfo.capabilityTable.ftrSupportsVmeAvcPreemption); + EXPECT_FALSE(hwInfo.capabilityTable.supportsVme); +} diff --git a/unit_tests/gen12lp/tgllp/windows/CMakeLists.txt b/unit_tests/gen12lp/tgllp/windows/CMakeLists.txt new file mode 100644 index 0000000000..478b32efb0 --- /dev/null +++ b/unit_tests/gen12lp/tgllp/windows/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (C) 2019 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +set(IGDRCL_SRCS_tests_gen12_tgllp_windows + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/hw_info_config_tests_tgllp.cpp +) +if(WIN32) + target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen12_tgllp_windows}) +endif() diff --git a/unit_tests/gen12lp/tgllp/windows/hw_info_config_tests_tgllp.cpp b/unit_tests/gen12lp/tgllp/windows/hw_info_config_tests_tgllp.cpp new file mode 100644 index 0000000000..c56079ef7e --- /dev/null +++ b/unit_tests/gen12lp/tgllp/windows/hw_info_config_tests_tgllp.cpp @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/os_interface/windows/os_interface.h" +#include "unit_tests/os_interface/windows/hw_info_config_win_tests.h" + +using namespace NEO; +using namespace std; + +using HwInfoConfigTestWindowsTgllp = HwInfoConfigTestWindows; + +TGLLPTEST_F(HwInfoConfigTestWindowsTgllp, whenCallAdjustPlatformThenSetGen12LpFamily) { + EXPECT_EQ(IGFX_TIGERLAKE_LP, productFamily); + + auto hwInfoConfig = HwInfoConfig::get(productFamily); + PLATFORM *testPlatform = &outHwInfo.platform; + testPlatform->eDisplayCoreFamily = IGFX_GEN11_CORE; + testPlatform->eRenderCoreFamily = IGFX_GEN11_CORE; + hwInfoConfig->adjustPlatformForProductFamily(&outHwInfo); + + EXPECT_EQ(IGFX_GEN12LP_CORE, testPlatform->eRenderCoreFamily); + EXPECT_EQ(IGFX_GEN12LP_CORE, testPlatform->eDisplayCoreFamily); +} diff --git a/unit_tests/gen12lp/unit_test_helper_gen12lp.cpp b/unit_tests/gen12lp/unit_test_helper_gen12lp.cpp new file mode 100644 index 0000000000..034ddfcfd7 --- /dev/null +++ b/unit_tests/gen12lp/unit_test_helper_gen12lp.cpp @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/gen12lp/hw_info.h" +#include "unit_tests/helpers/unit_test_helper.h" +#include "unit_tests/helpers/unit_test_helper.inl" + +namespace NEO { + +using Family = TGLLPFamily; + +template <> +bool UnitTestHelper::isL3ConfigProgrammable() { + return false; +}; + +template <> +bool UnitTestHelper::isPageTableManagerSupported(const HardwareInfo &hwInfo) { + return hwInfo.capabilityTable.ftrRenderCompressedBuffers || hwInfo.capabilityTable.ftrRenderCompressedImages; +} + +template <> +bool UnitTestHelper::isPipeControlWArequired(const HardwareInfo &hwInfo) { + if (hwInfo.platform.eProductFamily == IGFX_TIGERLAKE_LP) { + return true; + } + return false; +} + +template struct UnitTestHelper; +} // namespace NEO diff --git a/unit_tests/gen12lp/windows/CMakeLists.txt b/unit_tests/gen12lp/windows/CMakeLists.txt new file mode 100644 index 0000000000..e19034b8f8 --- /dev/null +++ b/unit_tests/gen12lp/windows/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (C) 2019 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +set(IGDRCL_SRCS_tests_gen12lp_windows + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/hw_info_config_tests_gen12lp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/gmm_callbacks_tests_gen12lp.cpp +) +if(WIN32) + target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_gen12lp_windows}) + add_subdirectories() +endif() diff --git a/unit_tests/gen12lp/windows/gmm_callbacks_tests_gen12lp.cpp b/unit_tests/gen12lp/windows/gmm_callbacks_tests_gen12lp.cpp new file mode 100644 index 0000000000..409770e050 --- /dev/null +++ b/unit_tests/gen12lp/windows/gmm_callbacks_tests_gen12lp.cpp @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "core/command_stream/linear_stream.h" +#include "core/unit_tests/helpers/debug_manager_state_restore.h" +#include "runtime/command_stream/aub_command_stream_receiver_hw.h" +#include "runtime/command_stream/command_stream_receiver_with_aub_dump.h" +#include "runtime/execution_environment/execution_environment.h" +#include "runtime/helpers/gmm_callbacks.h" +#include "runtime/helpers/hw_helper.h" +#include "runtime/os_interface/windows/wddm_device_command_stream.h" +#include "runtime/platform/platform.h" +#include "test.h" +#include "unit_tests/helpers/execution_environment_helper.h" +#include "unit_tests/helpers/hw_parse.h" +#include "unit_tests/libult/ult_command_stream_receiver.h" + +using namespace NEO; + +using Gen12LpGmmCallbacksTests = ::testing::Test; + +template +struct MockAubCsrToTestNotifyAubCapture : public AUBCommandStreamReceiverHw { + using AUBCommandStreamReceiverHw::AUBCommandStreamReceiverHw; + using AUBCommandStreamReceiverHw::externalAllocations; +}; + +GEN12LPTEST_F(Gen12LpGmmCallbacksTests, givenCsrWithoutAubDumpWhenNotifyAubCaptureCallbackIsCalledThenDoNothing) { + HardwareInfo *hwInfo = nullptr; + ExecutionEnvironment *executionEnvironment = getExecutionEnvironmentImpl(hwInfo); + executionEnvironment->initializeMemoryManager(); + auto csr = std::make_unique>(*executionEnvironment); + uint64_t address = 0xFEDCBA9876543210; + size_t size = 1024; + + auto res = DeviceCallbacks::notifyAubCapture(csr.get(), address, size, true); + + EXPECT_EQ(1, res); +} + +GEN12LPTEST_F(Gen12LpGmmCallbacksTests, givenWddmCsrWhenWriteL3CalledThenWriteTwoMmio) { + typedef typename FamilyType::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM; + ExecutionEnvironment *executionEnvironment = platformImpl->peekExecutionEnvironment(); + executionEnvironment->initializeMemoryManager(); + UltCommandStreamReceiver csr(*executionEnvironment); + uint8_t buffer[128] = {}; + csr.commandStream.replaceBuffer(buffer, 128); + + uint64_t address = 0x00234564002BCDEC; + uint64_t value = 0xFEDCBA987654321C; + + auto res = TTCallbacks::writeL3Address(&csr, value, address); + EXPECT_EQ(1, res); + EXPECT_EQ(2 * sizeof(MI_LOAD_REGISTER_IMM), csr.commandStream.getUsed()); + + HardwareParse hwParse; + hwParse.parseCommands(csr.commandStream, 0); + EXPECT_EQ(2u, hwParse.cmdList.size()); + + auto cmd = genCmdCast(*hwParse.cmdList.begin()); + ASSERT_NE(nullptr, cmd); + EXPECT_EQ(address & 0xFFFFFFFF, cmd->getRegisterOffset()); + EXPECT_EQ(value & 0xFFFFFFFF, cmd->getDataDword()); + + cmd = genCmdCast(*(++hwParse.cmdList.begin())); + ASSERT_NE(nullptr, cmd); + EXPECT_EQ(address >> 32, cmd->getRegisterOffset()); + EXPECT_EQ(value >> 32, cmd->getDataDword()); +} + +GEN12LPTEST_F(Gen12LpGmmCallbacksTests, givenCcsEnabledhenWriteL3CalledThenSetRemapBit) { + typedef typename FamilyType::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM; + HardwareInfo localHwInfo = **platformDevices; + localHwInfo.featureTable.ftrCCSNode = true; + ExecutionEnvironment executionEnvironment; + executionEnvironment.setHwInfo(&localHwInfo); + executionEnvironment.initializeMemoryManager(); + UltCommandStreamReceiver csr(executionEnvironment); + uint8_t buffer[128] = {}; + csr.commandStream.replaceBuffer(buffer, 128); + + auto res = TTCallbacks::writeL3Address(&csr, 1, 1); + EXPECT_EQ(1, res); + + HardwareParse hwParse; + hwParse.parseCommands(csr.commandStream, 0); + EXPECT_EQ(2u, hwParse.cmdList.size()); + + auto cmd = genCmdCast(*hwParse.cmdList.begin()); + ASSERT_NE(nullptr, cmd); + EXPECT_TRUE(cmd->getMmioRemapEnable()); + + cmd = genCmdCast(*(++hwParse.cmdList.begin())); + ASSERT_NE(nullptr, cmd); + EXPECT_TRUE(cmd->getMmioRemapEnable()); +} + +GEN12LPTEST_F(Gen12LpGmmCallbacksTests, givenCcsDisabledhenWriteL3CalledThenSetRemapBitToTrue) { + typedef typename FamilyType::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM; + HardwareInfo localHwInfo = **platformDevices; + localHwInfo.featureTable.ftrCCSNode = false; + ExecutionEnvironment executionEnvironment; + executionEnvironment.setHwInfo(&localHwInfo); + executionEnvironment.initializeMemoryManager(); + UltCommandStreamReceiver csr(executionEnvironment); + uint8_t buffer[128] = {}; + csr.commandStream.replaceBuffer(buffer, 128); + + auto res = TTCallbacks::writeL3Address(&csr, 1, 1); + EXPECT_EQ(1, res); + + HardwareParse hwParse; + hwParse.parseCommands(csr.commandStream, 0); + EXPECT_EQ(2u, hwParse.cmdList.size()); + + auto cmd = genCmdCast(*hwParse.cmdList.begin()); + ASSERT_NE(nullptr, cmd); + EXPECT_TRUE(cmd->getMmioRemapEnable()); + + cmd = genCmdCast(*(++hwParse.cmdList.begin())); + ASSERT_NE(nullptr, cmd); + EXPECT_TRUE(cmd->getMmioRemapEnable()); +} diff --git a/unit_tests/gen12lp/windows/hw_info_config_tests_gen12lp.cpp b/unit_tests/gen12lp/windows/hw_info_config_tests_gen12lp.cpp new file mode 100644 index 0000000000..a5a55f3cef --- /dev/null +++ b/unit_tests/gen12lp/windows/hw_info_config_tests_gen12lp.cpp @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "core/unit_tests/helpers/debug_manager_state_restore.h" +#include "runtime/os_interface/windows/os_interface.h" +#include "unit_tests/os_interface/windows/hw_info_config_win_tests.h" + +using namespace NEO; +using namespace std; + +using HwInfoConfigTestWindowsGen12lp = HwInfoConfigTestWindows; + +GEN12LPTEST_F(HwInfoConfigTestWindowsGen12lp, givenE2ECSetByKmdWhenConfiguringHwThenAdjustInternalImageFlag) { + FeatureTable &localFeatureTable = outHwInfo.featureTable; + + auto hwInfoConfig = HwInfoConfig::get(productFamily); + + localFeatureTable.ftrE2ECompression = true; + hwInfoConfig->configureHardwareCustom(&outHwInfo, nullptr); + EXPECT_TRUE(outHwInfo.capabilityTable.ftrRenderCompressedBuffers); + EXPECT_TRUE(outHwInfo.capabilityTable.ftrRenderCompressedImages); + + localFeatureTable.ftrE2ECompression = false; + hwInfoConfig->configureHardwareCustom(&outHwInfo, nullptr); + EXPECT_FALSE(outHwInfo.capabilityTable.ftrRenderCompressedBuffers); + EXPECT_FALSE(outHwInfo.capabilityTable.ftrRenderCompressedImages); +} diff --git a/unit_tests/gen_common/CMakeLists.txt b/unit_tests/gen_common/CMakeLists.txt index 328a44f15a..c231f9ca04 100644 --- a/unit_tests/gen_common/CMakeLists.txt +++ b/unit_tests/gen_common/CMakeLists.txt @@ -8,7 +8,9 @@ set(IGDRCL_SRCS_tests_gen_common ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt ${CMAKE_CURRENT_SOURCE_DIR}/cmd_parse_base.inl ${CMAKE_CURRENT_SOURCE_DIR}/cmd_parse_base_mi_arb.inl + ${CMAKE_CURRENT_SOURCE_DIR}/cmd_parse_compute_mode.inl ${CMAKE_CURRENT_SOURCE_DIR}/cmd_parse_gpgpu_walker.inl + ${CMAKE_CURRENT_SOURCE_DIR}/cmd_parse_mi_arb.inl ${CMAKE_CURRENT_SOURCE_DIR}/cmd_parse_sip.inl ${CMAKE_CURRENT_SOURCE_DIR}/exclude_tests/exclude_test_declare.cpp ${CMAKE_CURRENT_SOURCE_DIR}/exclude_tests/exclude_test_exclude.cpp diff --git a/unit_tests/gen_common/cmd_parse_compute_mode.inl b/unit_tests/gen_common/cmd_parse_compute_mode.inl new file mode 100644 index 0000000000..2545154a6e --- /dev/null +++ b/unit_tests/gen_common/cmd_parse_compute_mode.inl @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +// clang-format off +using namespace NEO; +using STATE_COMPUTE_MODE = GenStruct::STATE_COMPUTE_MODE; +// clang-format on + +template <> +STATE_COMPUTE_MODE *genCmdCast(void *buffer) { + auto pCmd = reinterpret_cast(buffer); + + return STATE_COMPUTE_MODE::COMMAND_TYPE_GFXPIPE == pCmd->TheStructure.Common.CommandType && + STATE_COMPUTE_MODE::COMMAND_SUBTYPE_GFXPIPE_COMMON == pCmd->TheStructure.Common.CommandSubtype && + STATE_COMPUTE_MODE::_3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED == pCmd->TheStructure.Common._3DCommandOpcode && + STATE_COMPUTE_MODE::_3D_COMMAND_SUB_OPCODE_STATE_COMPUTE_MODE == pCmd->TheStructure.Common._3DCommandSubOpcode + ? pCmd + : nullptr; +} diff --git a/unit_tests/gen_common/cmd_parse_mi_arb.inl b/unit_tests/gen_common/cmd_parse_mi_arb.inl new file mode 100644 index 0000000000..95bae9011f --- /dev/null +++ b/unit_tests/gen_common/cmd_parse_mi_arb.inl @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +template <> +MI_ARB_CHECK *genCmdCast(void *buffer) { + auto pCmd = reinterpret_cast(buffer); + + return MI_ARB_CHECK::COMMAND_TYPE_MI_COMMAND == pCmd->TheStructure.Common.CommandType && + MI_ARB_CHECK::MI_COMMAND_OPCODE_MI_ARB_CHECK == pCmd->TheStructure.Common.MiCommandOpcode + ? pCmd + : nullptr; +} diff --git a/unit_tests/gen_common/test.h b/unit_tests/gen_common/test.h index 7b68bf7775..4ab69af67e 100644 --- a/unit_tests/gen_common/test.h +++ b/unit_tests/gen_common/test.h @@ -41,6 +41,13 @@ extern GFXCORE_FAMILY renderCoreFamily; #define ICL_TYPED_TEST(method) #define ICL_SUPPORTED_TEST(cmdSetBase) false #endif +#ifdef TESTS_GEN12LP +#define TGLLP_TYPED_TEST(method) method::GfxFamily>(); +#define TGLLP_SUPPORTED_TEST(cmdSetBase) NEO::GfxFamilyMapper::GfxFamily::supportsCmdSet(cmdSetBase) +#else +#define TGLLP_TYPED_TEST(method) +#define TGLLP_SUPPORTED_TEST(cmdSetBase) false +#endif #define FAMILY_SELECTOR(family, methodName) \ switch (family) { \ @@ -53,6 +60,9 @@ extern GFXCORE_FAMILY renderCoreFamily; case IGFX_GEN11_CORE: \ ICL_TYPED_TEST(methodName) \ break; \ + case IGFX_GEN12LP_CORE: \ + TGLLP_TYPED_TEST(methodName) \ + break; \ default: \ ASSERT_TRUE((false && "Unknown hardware family")); \ break; \ @@ -209,6 +219,9 @@ extern GFXCORE_FAMILY renderCoreFamily; case IGFX_GEN11_CORE: \ supported = ICL_SUPPORTED_TEST(cmdSetBase); \ break; \ + case IGFX_GEN12LP_CORE: \ + supported = TGLLP_SUPPORTED_TEST(cmdSetBase); \ + break; \ default: \ ASSERT_TRUE((false && "Unknown hardware family")); \ break; \ @@ -519,7 +532,10 @@ extern GFXCORE_FAMILY renderCoreFamily; #define GEN11TEST_F(test_fixture, test_name) GENTEST_F(IGFX_GEN11_CORE, test_fixture, test_name) #define GEN11TEST_P(test_suite_name, test_name) GENTEST_P(IGFX_GEN11_CORE, test_fixture, test_name) #endif - +#ifdef TESTS_GEN12LP +#define GEN12LPTEST_F(test_fixture, test_name) GENTEST_F(IGFX_GEN12LP_CORE, test_fixture, test_name) +#define GEN12LPTEST_P(test_suite_name, test_name) GENTEST_P(IGFX_GEN12LP_CORE, test_fixture, test_name) +#endif #ifdef TESTS_GEN8 #define BDWTEST_F(test_fixture, test_name) \ FAMILYTEST_TEST_(test_fixture, test_name, test_fixture, \ @@ -606,6 +622,16 @@ extern GFXCORE_FAMILY renderCoreFamily; IGFX_GEN11_CORE, \ IGFX_ELKHARTLAKE) #endif +#ifdef TESTS_GEN12LP +#define TGLLPTEST_F(test_fixture, test_name) \ + FAMILYTEST_TEST_(test_fixture, test_name, test_fixture, \ + ::testing::internal::GetTypeId(), \ + IGFX_GEN12LP_CORE, IGFX_TIGERLAKE_LP) +#define TGLLPTEST_P(test_suite_name, test_name) \ + FAMILYTEST_TEST_P(test_suite_name, test_name, \ + IGFX_GEN12LP_CORE, \ + IGFX_TIGERLAKE_LP) +#endif #define HWTEST_TYPED_TEST(CaseName, TestName) \ CHECK_TEST_NAME_LENGTH(CaseName, TestName) \ template \ diff --git a/unit_tests/libult/gen12lp.cpp b/unit_tests/libult/gen12lp.cpp new file mode 100644 index 0000000000..031d2460d6 --- /dev/null +++ b/unit_tests/libult/gen12lp.cpp @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2019 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "runtime/helpers/base_object.h" +#include "unit_tests/libult/ult_command_stream_receiver.h" + +namespace NEO { + +typedef TGLLPFamily Family; + +static auto gfxCore = IGFX_GEN12LP_CORE; + +extern CommandStreamReceiverCreateFunc commandStreamReceiverFactory[2 * IGFX_MAX_CORE]; + +template <> +void populateFactoryTable>() { + commandStreamReceiverFactory[IGFX_MAX_CORE + gfxCore] = UltCommandStreamReceiver::create; +} + +struct enableGen12LP { + enableGen12LP() { + populateFactoryTable>(); + } +}; + +static enableGen12LP enable; + +template class UltCommandStreamReceiver; +} // namespace NEO diff --git a/unit_tests/os_interface/linux/drm_mapper_tests.cpp b/unit_tests/os_interface/linux/drm_mapper_tests.cpp index 8ef8a1a0ff..c5f8f0daef 100644 --- a/unit_tests/os_interface/linux/drm_mapper_tests.cpp +++ b/unit_tests/os_interface/linux/drm_mapper_tests.cpp @@ -15,10 +15,13 @@ using namespace NEO; TEST(DrmMapperTests, engineNodeMapPass) { unsigned int rcsFlag = DrmEngineMapper::engineNodeMap(aub_stream::ENGINE_RCS); unsigned int bcsFlag = DrmEngineMapper::engineNodeMap(aub_stream::ENGINE_BCS); + unsigned int ccsFlag = DrmEngineMapper::engineNodeMap(aub_stream::ENGINE_CCS); unsigned int expectedRcsFlag = I915_EXEC_RENDER; unsigned int expectedBcsFlag = I915_EXEC_BLT; + unsigned int expectedCcsFlag = I915_EXEC_COMPUTE; EXPECT_EQ(expectedRcsFlag, rcsFlag); EXPECT_EQ(expectedBcsFlag, bcsFlag); + EXPECT_EQ(expectedCcsFlag, ccsFlag); } TEST(DrmMapperTests, engineNodeMapNegative) { diff --git a/unit_tests/os_interface/windows/wddm_mapper_tests.cpp b/unit_tests/os_interface/windows/wddm_mapper_tests.cpp index 196f8c0bfb..60ae61330f 100644 --- a/unit_tests/os_interface/windows/wddm_mapper_tests.cpp +++ b/unit_tests/os_interface/windows/wddm_mapper_tests.cpp @@ -13,10 +13,13 @@ using namespace NEO; TEST(WddmMapperTests, givenRcsEngineTypeWhenAskedForNodeOrdinalThenReturn3d) { GPUNODE_ORDINAL rcsNode = WddmEngineMapper::engineNodeMap(aub_stream::ENGINE_RCS); GPUNODE_ORDINAL bcsNode = WddmEngineMapper::engineNodeMap(aub_stream::ENGINE_BCS); + GPUNODE_ORDINAL ccsNode = WddmEngineMapper::engineNodeMap(aub_stream::ENGINE_CCS); GPUNODE_ORDINAL expectedRcsNode = GPUNODE_3D; GPUNODE_ORDINAL expectedBcsNode = GPUNODE_BLT; + GPUNODE_ORDINAL expectedCcsNode = GPUNODE_CCS0; EXPECT_EQ(expectedRcsNode, rcsNode); EXPECT_EQ(expectedBcsNode, bcsNode); + EXPECT_EQ(expectedCcsNode, ccsNode); } TEST(WddmMapperTests, givenNotSupportedEngineWhenAskedForNodeThenAbort) { diff --git a/unit_tests/test_files/igdrcl.config b/unit_tests/test_files/igdrcl.config index 4f86946d26..a9e6a350fd 100644 --- a/unit_tests/test_files/igdrcl.config +++ b/unit_tests/test_files/igdrcl.config @@ -119,3 +119,4 @@ OverrideStatelessMocsIndex = -1 AllocateSharedAllocationsWithCpuAndGpuStorage = -1 EnableSharedSystemUsmSupport = -1 ForcePerDssBackedBufferProgramming = 0 +ForceSamplerLowFilteringPrecision = 0