mirror of
https://github.com/intel/compute-runtime.git
synced 2025-12-20 00:24:58 +08:00
feature: initial 64b in-order CmdList support
Related-To: NEO-7966 Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
This commit is contained in:
committed by
Compute-Runtime-Automation
parent
698a3ed3de
commit
d3d5da1f72
@@ -169,7 +169,7 @@ struct CommandListCoreFamily : CommandListImp {
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ze_result_t appendSignalEvent(ze_event_handle_t hEvent) override;
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ze_result_t appendSignalEvent(ze_event_handle_t hEvent) override;
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ze_result_t appendWaitOnEvents(uint32_t numEvents, ze_event_handle_t *phEvent, bool relaxedOrderingAllowed, bool trackDependencies, bool signalInOrderCompletion) override;
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ze_result_t appendWaitOnEvents(uint32_t numEvents, ze_event_handle_t *phEvent, bool relaxedOrderingAllowed, bool trackDependencies, bool signalInOrderCompletion) override;
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void appendWaitOnInOrderDependency(NEO::GraphicsAllocation *dependencyCounterAllocation, uint32_t waitValue, uint32_t offset, bool relaxedOrderingAllowed);
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void appendWaitOnInOrderDependency(NEO::GraphicsAllocation *dependencyCounterAllocation, uint64_t waitValue, uint32_t offset, bool relaxedOrderingAllowed);
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void appendSignalInOrderDependencyCounter();
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void appendSignalInOrderDependencyCounter();
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ze_result_t appendWriteGlobalTimestamp(uint64_t *dstptr, ze_event_handle_t hSignalEvent,
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ze_result_t appendWriteGlobalTimestamp(uint64_t *dstptr, ze_event_handle_t hSignalEvent,
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uint32_t numWaitEvents, ze_event_handle_t *phWaitEvents) override;
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uint32_t numWaitEvents, ze_event_handle_t *phWaitEvents) override;
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@@ -329,6 +329,7 @@ struct CommandListCoreFamily : CommandListImp {
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bool isInOrderEventWaitRequired(const Event &event) const;
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bool isInOrderEventWaitRequired(const Event &event) const;
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void handleInOrderImplicitDependencies(bool relaxedOrderingAllowed);
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void handleInOrderImplicitDependencies(bool relaxedOrderingAllowed);
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virtual void handleInOrderDependencyCounter();
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virtual void handleInOrderDependencyCounter();
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bool isQwordInOrderCounter() const { return GfxFamily::isQwordInOrderCounter; }
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};
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};
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template <PRODUCT_FAMILY gfxProductFamily>
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template <PRODUCT_FAMILY gfxProductFamily>
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@@ -150,7 +150,7 @@ ze_result_t CommandListCoreFamily<gfxCoreFamily>::reset() {
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template <GFXCORE_FAMILY gfxCoreFamily>
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template <GFXCORE_FAMILY gfxCoreFamily>
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void CommandListCoreFamily<gfxCoreFamily>::handleInOrderDependencyCounter() {
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void CommandListCoreFamily<gfxCoreFamily>::handleInOrderDependencyCounter() {
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if ((inOrderDependencyCounter + 1) == std::numeric_limits<uint32_t>::max()) {
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if (!isQwordInOrderCounter() && ((inOrderDependencyCounter + 1) == std::numeric_limits<uint32_t>::max())) {
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CommandListCoreFamily<gfxCoreFamily>::appendWaitOnInOrderDependency(inOrderDependencyCounterAllocation, inOrderDependencyCounter + 1, inOrderAllocationOffset, false);
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CommandListCoreFamily<gfxCoreFamily>::appendWaitOnInOrderDependency(inOrderDependencyCounterAllocation, inOrderDependencyCounter + 1, inOrderAllocationOffset, false);
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inOrderDependencyCounter = 0;
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inOrderDependencyCounter = 0;
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@@ -2297,7 +2297,7 @@ ze_result_t CommandListCoreFamily<gfxCoreFamily>::appendSignalEvent(ze_event_han
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}
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}
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template <GFXCORE_FAMILY gfxCoreFamily>
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template <GFXCORE_FAMILY gfxCoreFamily>
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void CommandListCoreFamily<gfxCoreFamily>::appendWaitOnInOrderDependency(NEO::GraphicsAllocation *dependencyCounterAllocation, uint32_t waitValue, uint32_t offset, bool relaxedOrderingAllowed) {
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void CommandListCoreFamily<gfxCoreFamily>::appendWaitOnInOrderDependency(NEO::GraphicsAllocation *dependencyCounterAllocation, uint64_t waitValue, uint32_t offset, bool relaxedOrderingAllowed) {
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using COMPARE_OPERATION = typename GfxFamily::MI_SEMAPHORE_WAIT::COMPARE_OPERATION;
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using COMPARE_OPERATION = typename GfxFamily::MI_SEMAPHORE_WAIT::COMPARE_OPERATION;
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UNRECOVERABLE_IF(waitValue > std::numeric_limits<uint32_t>::max());
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UNRECOVERABLE_IF(waitValue > std::numeric_limits<uint32_t>::max());
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@@ -2309,12 +2309,12 @@ void CommandListCoreFamily<gfxCoreFamily>::appendWaitOnInOrderDependency(NEO::Gr
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for (uint32_t i = 0; i < this->partitionCount; i++) {
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for (uint32_t i = 0; i < this->partitionCount; i++) {
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if (relaxedOrderingAllowed) {
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if (relaxedOrderingAllowed) {
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NEO::EncodeBatchBufferStartOrEnd<GfxFamily>::programConditionalDataMemBatchBufferStart(*commandContainer.getCommandStream(), 0, gpuAddress, waitValue, NEO::CompareOperation::Less, true, false);
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NEO::EncodeBatchBufferStartOrEnd<GfxFamily>::programConditionalDataMemBatchBufferStart(*commandContainer.getCommandStream(), 0, gpuAddress, waitValue, NEO::CompareOperation::Less, true, isQwordInOrderCounter());
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} else {
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} else {
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NEO::EncodeSemaphore<GfxFamily>::addMiSemaphoreWaitCommand(*commandContainer.getCommandStream(),
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NEO::EncodeSemaphore<GfxFamily>::addMiSemaphoreWaitCommand(*commandContainer.getCommandStream(),
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gpuAddress, waitValue,
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gpuAddress, waitValue,
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COMPARE_OPERATION::COMPARE_OPERATION_SAD_GREATER_THAN_OR_EQUAL_SDD, false, false, false);
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COMPARE_OPERATION::COMPARE_OPERATION_SAD_GREATER_THAN_OR_EQUAL_SDD, false, isQwordInOrderCounter(), false);
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}
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}
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gpuAddress += sizeof(uint64_t);
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gpuAddress += sizeof(uint64_t);
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@@ -2415,12 +2415,12 @@ ze_result_t CommandListCoreFamily<gfxCoreFamily>::appendWaitOnEvents(uint32_t nu
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template <GFXCORE_FAMILY gfxCoreFamily>
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template <GFXCORE_FAMILY gfxCoreFamily>
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void CommandListCoreFamily<gfxCoreFamily>::appendSignalInOrderDependencyCounter() {
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void CommandListCoreFamily<gfxCoreFamily>::appendSignalInOrderDependencyCounter() {
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uint32_t signalValue = this->inOrderDependencyCounter + 1;
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uint64_t signalValue = this->inOrderDependencyCounter + 1;
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uint64_t gpuVa = this->inOrderDependencyCounterAllocation->getGpuAddress() + this->inOrderAllocationOffset;
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uint64_t gpuVa = this->inOrderDependencyCounterAllocation->getGpuAddress() + this->inOrderAllocationOffset;
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NEO::EncodeStoreMemory<GfxFamily>::programStoreDataImm(*commandContainer.getCommandStream(), gpuVa,
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NEO::EncodeStoreMemory<GfxFamily>::programStoreDataImm(*commandContainer.getCommandStream(), gpuVa,
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signalValue, 0, false, (this->partitionCount > 1));
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getLowPart(signalValue), getHighPart(signalValue), isQwordInOrderCounter(), (this->partitionCount > 1));
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if (NEO::EncodeUserInterruptHelper::isOperationAllowed(NEO::EncodeUserInterruptHelper::onSignalingFenceMask)) {
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if (NEO::EncodeUserInterruptHelper::isOperationAllowed(NEO::EncodeUserInterruptHelper::onSignalingFenceMask)) {
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NEO::EnodeUserInterrupt<GfxFamily>::encode(*commandContainer.getCommandStream());
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NEO::EnodeUserInterrupt<GfxFamily>::encode(*commandContainer.getCommandStream());
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@@ -1238,10 +1238,10 @@ ze_result_t CommandListCoreFamilyImmediate<gfxCoreFamily>::synchronizeInOrderExe
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bool signaled = true;
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bool signaled = true;
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auto hostAddress = static_cast<uint32_t *>(ptrOffset(this->inOrderDependencyCounterAllocation->getUnderlyingBuffer(), this->inOrderAllocationOffset));
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auto hostAddress = static_cast<uint64_t *>(ptrOffset(this->inOrderDependencyCounterAllocation->getUnderlyingBuffer(), this->inOrderAllocationOffset));
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for (uint32_t i = 0; i < this->partitionCount; i++) {
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for (uint32_t i = 0; i < this->partitionCount; i++) {
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if (!NEO::WaitUtils::waitFunctionWithPredicate<const uint32_t>(hostAddress, waitValue, std::greater_equal<uint32_t>())) {
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if (!NEO::WaitUtils::waitFunctionWithPredicate<const uint64_t>(hostAddress, waitValue, std::greater_equal<uint64_t>())) {
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signaled = false;
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signaled = false;
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break;
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break;
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}
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}
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@@ -37,7 +37,7 @@ struct CommandListImp : CommandList {
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protected:
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protected:
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NEO::GraphicsAllocation *inOrderDependencyCounterAllocation = nullptr;
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NEO::GraphicsAllocation *inOrderDependencyCounterAllocation = nullptr;
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uint32_t inOrderDependencyCounter = 0;
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uint64_t inOrderDependencyCounter = 0;
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uint32_t inOrderAllocationOffset = 0;
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uint32_t inOrderAllocationOffset = 0;
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bool inOrderExecutionEnabled = false;
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bool inOrderExecutionEnabled = false;
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@@ -391,7 +391,7 @@ void Event::setIsCompleted() {
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unsetCmdQueue();
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unsetCmdQueue();
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}
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}
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void Event::updateInOrderExecState(NEO::GraphicsAllocation &inOrderDependenciesAllocation, uint32_t signalValue, uint32_t allocationOffset) {
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void Event::updateInOrderExecState(NEO::GraphicsAllocation &inOrderDependenciesAllocation, uint64_t signalValue, uint32_t allocationOffset) {
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inOrderExecSignalValue = signalValue;
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inOrderExecSignalValue = signalValue;
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inOrderExecDataAllocation = &inOrderDependenciesAllocation;
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inOrderExecDataAllocation = &inOrderDependenciesAllocation;
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inOrderAllocationOffset = allocationOffset;
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inOrderAllocationOffset = allocationOffset;
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@@ -215,10 +215,10 @@ struct Event : _ze_event_handle_t {
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void setMetricStreamer(MetricStreamer *metricStreamer) {
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void setMetricStreamer(MetricStreamer *metricStreamer) {
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this->metricStreamer = metricStreamer;
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this->metricStreamer = metricStreamer;
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}
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}
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void updateInOrderExecState(NEO::GraphicsAllocation &inOrderDependenciesAllocation, uint32_t signalValue, uint32_t allocationOffset);
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void updateInOrderExecState(NEO::GraphicsAllocation &inOrderDependenciesAllocation, uint64_t signalValue, uint32_t allocationOffset);
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bool isInOrderExecEvent() const { return inOrderExecEvent; }
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bool isInOrderExecEvent() const { return inOrderExecEvent; }
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NEO::GraphicsAllocation *getInOrderExecDataAllocation() const { return inOrderExecDataAllocation; }
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NEO::GraphicsAllocation *getInOrderExecDataAllocation() const { return inOrderExecDataAllocation; }
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uint32_t getInOrderExecSignalValue() const { return inOrderExecSignalValue; }
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uint64_t getInOrderExecSignalValue() const { return inOrderExecSignalValue; }
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uint32_t getInOrderAllocationOffset() const { return inOrderAllocationOffset; }
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uint32_t getInOrderAllocationOffset() const { return inOrderAllocationOffset; }
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void setLatestUsedCmdQueue(CommandQueue *newCmdQ);
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void setLatestUsedCmdQueue(CommandQueue *newCmdQ);
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NEO::TimeStampData *peekReferenceTs() {
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NEO::TimeStampData *peekReferenceTs() {
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@@ -238,7 +238,7 @@ struct Event : _ze_event_handle_t {
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uint64_t contextEndTS = 1;
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uint64_t contextEndTS = 1;
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NEO::TimeStampData referenceTs{};
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NEO::TimeStampData referenceTs{};
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uint32_t inOrderExecSignalValue = 0;
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uint64_t inOrderExecSignalValue = 0;
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uint32_t inOrderAllocationOffset = 0;
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uint32_t inOrderAllocationOffset = 0;
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std::chrono::microseconds gpuHangCheckPeriod{500'000};
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std::chrono::microseconds gpuHangCheckPeriod{500'000};
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@@ -148,11 +148,11 @@ void EventImp<TagSizeT>::assignKernelEventCompletionData(void *address) {
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template <typename TagSizeT>
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template <typename TagSizeT>
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ze_result_t EventImp<TagSizeT>::queryInOrderEventStatus() {
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ze_result_t EventImp<TagSizeT>::queryInOrderEventStatus() {
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auto hostAddress = static_cast<uint32_t *>(ptrOffset(this->inOrderExecDataAllocation->getUnderlyingBuffer(), this->inOrderAllocationOffset));
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auto hostAddress = static_cast<uint64_t *>(ptrOffset(this->inOrderExecDataAllocation->getUnderlyingBuffer(), this->inOrderAllocationOffset));
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bool signaled = true;
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bool signaled = true;
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for (uint32_t i = 0; i < this->getPacketsInUse(); i++) {
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for (uint32_t i = 0; i < this->getPacketsInUse(); i++) {
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if (!NEO::WaitUtils::waitFunctionWithPredicate<const uint32_t>(hostAddress, this->inOrderExecSignalValue, std::greater_equal<uint32_t>())) {
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if (!NEO::WaitUtils::waitFunctionWithPredicate<const uint64_t>(hostAddress, this->inOrderExecSignalValue, std::greater_equal<uint64_t>())) {
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signaled = false;
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signaled = false;
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break;
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break;
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}
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}
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@@ -80,6 +80,7 @@ struct WhiteBox<::L0::CommandListCoreFamily<gfxCoreFamily>>
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using BaseClass::inOrderDependencyCounter;
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using BaseClass::inOrderDependencyCounter;
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using BaseClass::inOrderDependencyCounterAllocation;
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using BaseClass::inOrderDependencyCounterAllocation;
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using BaseClass::isFlushTaskSubmissionEnabled;
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using BaseClass::isFlushTaskSubmissionEnabled;
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using BaseClass::isQwordInOrderCounter;
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using BaseClass::isRelaxedOrderingDispatchAllowed;
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using BaseClass::isRelaxedOrderingDispatchAllowed;
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using BaseClass::isSyncModeQueue;
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using BaseClass::isSyncModeQueue;
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using BaseClass::isTbxMode;
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using BaseClass::isTbxMode;
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@@ -172,6 +173,7 @@ struct WhiteBox<L0::CommandListCoreFamilyImmediate<gfxCoreFamily>>
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using BaseClass::inOrderDependencyCounterAllocation;
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using BaseClass::inOrderDependencyCounterAllocation;
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using BaseClass::isBcsSplitNeeded;
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using BaseClass::isBcsSplitNeeded;
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using BaseClass::isFlushTaskSubmissionEnabled;
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using BaseClass::isFlushTaskSubmissionEnabled;
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using BaseClass::isQwordInOrderCounter;
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using BaseClass::isSyncModeQueue;
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using BaseClass::isSyncModeQueue;
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using BaseClass::isTbxMode;
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using BaseClass::isTbxMode;
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using BaseClass::latestFlushIsHostVisible;
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using BaseClass::latestFlushIsHostVisible;
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@@ -1697,7 +1697,8 @@ HWTEST2_F(CommandListCreate, givenInOrderExecutionWhenDispatchingRelaxedOrdering
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lrrCmd++;
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lrrCmd++;
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lrrCmd++;
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lrrCmd++;
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EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(lrrCmd, 0, cmdList->inOrderDependencyCounterAllocation->getGpuAddress(), 2, NEO::CompareOperation::Less, true));
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EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(lrrCmd, 0, cmdList->inOrderDependencyCounterAllocation->getGpuAddress(), 2,
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NEO::CompareOperation::Less, true, cmdList->isQwordInOrderCounter()));
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}
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}
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TEST_F(CommandListCreate, GivenGpuHangWhenCreatingImmCmdListWithSyncModeAndAppendBarrierThenAppendBarrierReturnsDeviceLost) {
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TEST_F(CommandListCreate, GivenGpuHangWhenCreatingImmCmdListWithSyncModeAndAppendBarrierThenAppendBarrierReturnsDeviceLost) {
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@@ -796,6 +796,12 @@ struct InOrderCmdListTests : public CommandListAppendLaunchKernel {
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CmdListKernelLaunchParams launchParams = {};
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CmdListKernelLaunchParams launchParams = {};
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};
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};
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HWTEST2_F(InOrderCmdListTests, givenCmdListWhenAskingForQwordDataSizeThenReturnFalse, IsAtLeastSkl) {
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auto immCmdList = createImmCmdList<gfxCoreFamily>();
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EXPECT_FALSE(immCmdList->isQwordInOrderCounter());
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}
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HWTEST2_F(InOrderCmdListTests, givenQueueFlagWhenCreatingCmdListThenEnableRelaxedOrdering, IsAtLeastXeHpCore) {
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HWTEST2_F(InOrderCmdListTests, givenQueueFlagWhenCreatingCmdListThenEnableRelaxedOrdering, IsAtLeastXeHpCore) {
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NEO::DebugManager.flags.ForceInOrderImmediateCmdListExecution.set(-1);
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NEO::DebugManager.flags.ForceInOrderImmediateCmdListExecution.set(-1);
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@@ -1410,7 +1416,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingWalkerThenSignalSy
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EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress() + counterOffset, postSync.getDestinationAddress());
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EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress() + counterOffset, postSync.getDestinationAddress());
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}
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}
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auto hostAddress = static_cast<uint32_t *>(ptrOffset(immCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer(), counterOffset));
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auto hostAddress = static_cast<uint64_t *>(ptrOffset(immCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer(), counterOffset));
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*hostAddress = 1;
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*hostAddress = 1;
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EXPECT_EQ(ZE_RESULT_NOT_READY, events[0]->hostSynchronize(1));
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EXPECT_EQ(ZE_RESULT_NOT_READY, events[0]->hostSynchronize(1));
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@@ -1473,7 +1479,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingTimestampEventThen
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ASSERT_NE(nullptr, sdiCmd);
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ASSERT_NE(nullptr, sdiCmd);
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EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
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EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
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EXPECT_EQ(0u, sdiCmd->getStoreQword());
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EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
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EXPECT_EQ(1u, sdiCmd->getDataDword0());
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EXPECT_EQ(1u, sdiCmd->getDataDword0());
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}
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}
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@@ -1529,7 +1535,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingRegularEventThenCl
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ASSERT_NE(nullptr, sdiCmd);
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ASSERT_NE(nullptr, sdiCmd);
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EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
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EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
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EXPECT_EQ(0u, sdiCmd->getStoreQword());
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EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
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EXPECT_EQ(1u, sdiCmd->getDataDword0());
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EXPECT_EQ(1u, sdiCmd->getDataDword0());
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}
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}
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@@ -1645,7 +1651,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingKernelSplitThenPro
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uint64_t expectedAddress = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress() + immCmdList->inOrderAllocationOffset;
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uint64_t expectedAddress = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress() + immCmdList->inOrderAllocationOffset;
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EXPECT_EQ(expectedAddress, sdiCmd->getAddress());
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EXPECT_EQ(expectedAddress, sdiCmd->getAddress());
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EXPECT_EQ(0u, sdiCmd->getStoreQword());
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EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
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EXPECT_EQ(immCmdList->inOrderDependencyCounter, sdiCmd->getDataDword0());
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EXPECT_EQ(immCmdList->inOrderDependencyCounter, sdiCmd->getDataDword0());
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context->freeMem(hostAlloc);
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context->freeMem(hostAlloc);
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@@ -1699,7 +1705,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendSignalEventT
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ASSERT_NE(nullptr, sdiCmd);
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ASSERT_NE(nullptr, sdiCmd);
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EXPECT_EQ(inOrderSyncVa, sdiCmd->getAddress());
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EXPECT_EQ(inOrderSyncVa, sdiCmd->getAddress());
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EXPECT_EQ(0u, sdiCmd->getStoreQword());
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EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
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EXPECT_EQ(2u, sdiCmd->getDataDword0());
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EXPECT_EQ(2u, sdiCmd->getDataDword0());
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EXPECT_EQ(0u, sdiCmd->getDataDword1());
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EXPECT_EQ(0u, sdiCmd->getDataDword1());
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}
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}
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@@ -1723,17 +1729,17 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingNonKernelAppendThe
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uint32_t inOrderCounter = 1;
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uint32_t inOrderCounter = 1;
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auto verifySemaphore = [&inOrderSyncVa](const GenCmdList::iterator &iterator, uint32_t waitValue) {
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auto verifySemaphore = [&inOrderSyncVa](const GenCmdList::iterator &iterator, uint64_t waitValue) {
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auto semaphoreCmd = genCmdCast<MI_SEMAPHORE_WAIT *>(*iterator);
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auto semaphoreCmd = genCmdCast<MI_SEMAPHORE_WAIT *>(*iterator);
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ASSERT_NE(nullptr, semaphoreCmd);
|
ASSERT_NE(nullptr, semaphoreCmd);
|
||||||
|
|
||||||
EXPECT_EQ(waitValue, semaphoreCmd->getSemaphoreDataDword());
|
EXPECT_EQ(getLowPart(waitValue), semaphoreCmd->getSemaphoreDataDword());
|
||||||
EXPECT_EQ(inOrderSyncVa, semaphoreCmd->getSemaphoreGraphicsAddress());
|
EXPECT_EQ(inOrderSyncVa, semaphoreCmd->getSemaphoreGraphicsAddress());
|
||||||
EXPECT_EQ(MI_SEMAPHORE_WAIT::COMPARE_OPERATION::COMPARE_OPERATION_SAD_GREATER_THAN_OR_EQUAL_SDD, semaphoreCmd->getCompareOperation());
|
EXPECT_EQ(MI_SEMAPHORE_WAIT::COMPARE_OPERATION::COMPARE_OPERATION_SAD_GREATER_THAN_OR_EQUAL_SDD, semaphoreCmd->getCompareOperation());
|
||||||
};
|
};
|
||||||
|
|
||||||
auto verifySdi = [&inOrderSyncVa](GenCmdList::reverse_iterator rIterator, GenCmdList::reverse_iterator rEnd, uint32_t signalValue) {
|
auto verifySdi = [&inOrderSyncVa, &immCmdList](GenCmdList::reverse_iterator rIterator, GenCmdList::reverse_iterator rEnd, uint64_t signalValue) {
|
||||||
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*rIterator);
|
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*rIterator);
|
||||||
while (sdiCmd == nullptr) {
|
while (sdiCmd == nullptr) {
|
||||||
sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*(++rIterator));
|
sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*(++rIterator));
|
||||||
@@ -1745,9 +1751,9 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingNonKernelAppendThe
|
|||||||
ASSERT_NE(nullptr, sdiCmd);
|
ASSERT_NE(nullptr, sdiCmd);
|
||||||
|
|
||||||
EXPECT_EQ(inOrderSyncVa, sdiCmd->getAddress());
|
EXPECT_EQ(inOrderSyncVa, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(signalValue, sdiCmd->getDataDword0());
|
EXPECT_EQ(getLowPart(signalValue), sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(getHighPart(signalValue), sdiCmd->getDataDword1());
|
||||||
};
|
};
|
||||||
|
|
||||||
{
|
{
|
||||||
@@ -1817,7 +1823,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderRegularCmdListWhenProgrammingNonKerne
|
|||||||
ASSERT_NE(nullptr, pcCmd);
|
ASSERT_NE(nullptr, pcCmd);
|
||||||
};
|
};
|
||||||
|
|
||||||
auto verifySdi = [&inOrderSyncVa](GenCmdList::reverse_iterator rIterator, GenCmdList::reverse_iterator rEnd, uint32_t signalValue) {
|
auto verifySdi = [&inOrderSyncVa, ®ularCmdList](GenCmdList::reverse_iterator rIterator, GenCmdList::reverse_iterator rEnd, uint64_t signalValue) {
|
||||||
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*rIterator);
|
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*rIterator);
|
||||||
while (sdiCmd == nullptr) {
|
while (sdiCmd == nullptr) {
|
||||||
sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*(++rIterator));
|
sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*(++rIterator));
|
||||||
@@ -1829,9 +1835,9 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderRegularCmdListWhenProgrammingNonKerne
|
|||||||
ASSERT_NE(nullptr, sdiCmd);
|
ASSERT_NE(nullptr, sdiCmd);
|
||||||
|
|
||||||
EXPECT_EQ(inOrderSyncVa, sdiCmd->getAddress());
|
EXPECT_EQ(inOrderSyncVa, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(regularCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(signalValue, sdiCmd->getDataDword0());
|
EXPECT_EQ(getLowPart(signalValue), sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(getHighPart(signalValue), sdiCmd->getDataDword1());
|
||||||
};
|
};
|
||||||
|
|
||||||
{
|
{
|
||||||
@@ -1979,7 +1985,7 @@ HWTEST2_F(InOrderCmdListTests, givenCopyOnlyInOrderModeWhenProgrammingCopyThenSi
|
|||||||
uint64_t syncVa = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
uint64_t syncVa = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
||||||
|
|
||||||
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
}
|
}
|
||||||
@@ -2044,7 +2050,7 @@ HWTEST2_F(InOrderCmdListTests, givenCopyOnlyInOrderModeWhenProgrammingFillThenSi
|
|||||||
uint64_t syncVa = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
uint64_t syncVa = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
||||||
|
|
||||||
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
|
|
||||||
@@ -2095,7 +2101,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingFillWithSplitAndOu
|
|||||||
uint64_t syncVa = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
uint64_t syncVa = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
||||||
|
|
||||||
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
|
|
||||||
@@ -2136,7 +2142,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingFillWithSplitAndWi
|
|||||||
uint64_t syncVa = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
uint64_t syncVa = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
||||||
|
|
||||||
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
|
|
||||||
@@ -2209,7 +2215,7 @@ HWTEST2_F(InOrderCmdListTests, givenCopyOnlyInOrderModeWhenProgrammingCopyRegion
|
|||||||
uint64_t syncVa = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
uint64_t syncVa = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
||||||
|
|
||||||
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
}
|
}
|
||||||
@@ -2253,7 +2259,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendWaitOnEvents
|
|||||||
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
|
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
|
||||||
|
|
||||||
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(3u, sdiCmd->getDataDword0());
|
EXPECT_EQ(3u, sdiCmd->getDataDword0());
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -2297,7 +2303,7 @@ HWTEST2_F(InOrderCmdListTests, givenRegularInOrderCmdListWhenProgrammingAppendWa
|
|||||||
uint64_t syncVa = regularCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
uint64_t syncVa = regularCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
||||||
|
|
||||||
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
EXPECT_EQ(syncVa, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(regularCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(3u, sdiCmd->getDataDword0());
|
EXPECT_EQ(3u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
}
|
}
|
||||||
@@ -2306,6 +2312,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingCounterWithOverflo
|
|||||||
using MI_STORE_DATA_IMM = typename FamilyType::MI_STORE_DATA_IMM;
|
using MI_STORE_DATA_IMM = typename FamilyType::MI_STORE_DATA_IMM;
|
||||||
using MI_SEMAPHORE_WAIT = typename FamilyType::MI_SEMAPHORE_WAIT;
|
using MI_SEMAPHORE_WAIT = typename FamilyType::MI_SEMAPHORE_WAIT;
|
||||||
using COMPUTE_WALKER = typename FamilyType::COMPUTE_WALKER;
|
using COMPUTE_WALKER = typename FamilyType::COMPUTE_WALKER;
|
||||||
|
using POSTSYNC_DATA = typename FamilyType::POSTSYNC_DATA;
|
||||||
|
|
||||||
auto immCmdList = createImmCmdList<gfxCoreFamily>();
|
auto immCmdList = createImmCmdList<gfxCoreFamily>();
|
||||||
immCmdList->inOrderDependencyCounter = std::numeric_limits<uint32_t>::max() - 1;
|
immCmdList->inOrderDependencyCounter = std::numeric_limits<uint32_t>::max() - 1;
|
||||||
@@ -2333,26 +2340,43 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingCounterWithOverflo
|
|||||||
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), postSync.getDestinationAddress());
|
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), postSync.getDestinationAddress());
|
||||||
|
|
||||||
auto semaphoreItor = find<MI_SEMAPHORE_WAIT *>(walkerItor, cmdList.end());
|
auto semaphoreItor = find<MI_SEMAPHORE_WAIT *>(walkerItor, cmdList.end());
|
||||||
ASSERT_NE(cmdList.end(), semaphoreItor);
|
|
||||||
|
|
||||||
auto semaphoreCmd = genCmdCast<MI_SEMAPHORE_WAIT *>(*semaphoreItor);
|
uint64_t expectedCounter = 1;
|
||||||
ASSERT_NE(nullptr, semaphoreCmd);
|
uint32_t offset = 0;
|
||||||
|
|
||||||
EXPECT_EQ(std::numeric_limits<uint32_t>::max(), semaphoreCmd->getSemaphoreDataDword());
|
if (immCmdList->isQwordInOrderCounter()) {
|
||||||
EXPECT_EQ(baseGpuVa, semaphoreCmd->getSemaphoreGraphicsAddress());
|
expectedCounter = std::numeric_limits<uint32_t>::max();
|
||||||
|
|
||||||
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(++semaphoreCmd);
|
EXPECT_EQ(cmdList.end(), semaphoreItor);
|
||||||
ASSERT_NE(nullptr, sdiCmd);
|
|
||||||
|
|
||||||
uint32_t offset = static_cast<uint32_t>(sizeof(uint64_t));
|
auto walkerCmd = genCmdCast<COMPUTE_WALKER *>(*walkerItor);
|
||||||
|
auto &postSync = walkerCmd->getPostSync();
|
||||||
|
|
||||||
EXPECT_EQ(baseGpuVa + offset, sdiCmd->getAddress());
|
EXPECT_EQ(POSTSYNC_DATA::OPERATION_WRITE_IMMEDIATE_DATA, postSync.getOperation());
|
||||||
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
EXPECT_EQ(expectedCounter, postSync.getImmediateData());
|
||||||
|
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), postSync.getDestinationAddress());
|
||||||
|
} else {
|
||||||
|
ASSERT_NE(cmdList.end(), semaphoreItor);
|
||||||
|
|
||||||
EXPECT_EQ(1u, immCmdList->inOrderDependencyCounter);
|
auto semaphoreCmd = genCmdCast<MI_SEMAPHORE_WAIT *>(*semaphoreItor);
|
||||||
|
ASSERT_NE(nullptr, semaphoreCmd);
|
||||||
|
|
||||||
|
EXPECT_EQ(std::numeric_limits<uint32_t>::max(), semaphoreCmd->getSemaphoreDataDword());
|
||||||
|
EXPECT_EQ(baseGpuVa, semaphoreCmd->getSemaphoreGraphicsAddress());
|
||||||
|
|
||||||
|
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(++semaphoreCmd);
|
||||||
|
ASSERT_NE(nullptr, sdiCmd);
|
||||||
|
|
||||||
|
offset = static_cast<uint32_t>(sizeof(uint64_t));
|
||||||
|
|
||||||
|
EXPECT_EQ(baseGpuVa + offset, sdiCmd->getAddress());
|
||||||
|
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
||||||
|
}
|
||||||
|
|
||||||
|
EXPECT_EQ(expectedCounter, immCmdList->inOrderDependencyCounter);
|
||||||
EXPECT_EQ(offset, immCmdList->inOrderAllocationOffset);
|
EXPECT_EQ(offset, immCmdList->inOrderAllocationOffset);
|
||||||
|
|
||||||
EXPECT_EQ(1u, events[0]->inOrderExecSignalValue);
|
EXPECT_EQ(expectedCounter, events[0]->inOrderExecSignalValue);
|
||||||
EXPECT_EQ(offset, events[0]->inOrderAllocationOffset);
|
EXPECT_EQ(offset, events[0]->inOrderAllocationOffset);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -2387,7 +2411,7 @@ HWTEST2_F(InOrderCmdListTests, givenCopyOnlyInOrderModeWhenProgrammingBarrierThe
|
|||||||
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
|
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
|
||||||
|
|
||||||
EXPECT_EQ(immCmdList2->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
EXPECT_EQ(immCmdList2->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList2->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
}
|
}
|
||||||
@@ -2425,7 +2449,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendBarrierWithW
|
|||||||
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
|
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
|
||||||
|
|
||||||
EXPECT_EQ(immCmdList2->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
EXPECT_EQ(immCmdList2->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList2->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
}
|
}
|
||||||
@@ -2522,7 +2546,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendBarrierWitho
|
|||||||
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
|
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
|
||||||
|
|
||||||
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
}
|
}
|
||||||
@@ -2559,7 +2583,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingAppendBarrierWitho
|
|||||||
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
|
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(*sdiItor);
|
||||||
|
|
||||||
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
}
|
}
|
||||||
@@ -2576,7 +2600,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenCallingSyncThenHandleCompleti
|
|||||||
|
|
||||||
immCmdList->appendLaunchKernel(kernel->toHandle(), &groupCount, events[0]->toHandle(), 0, nullptr, launchParams, false);
|
immCmdList->appendLaunchKernel(kernel->toHandle(), &groupCount, events[0]->toHandle(), 0, nullptr, launchParams, false);
|
||||||
|
|
||||||
auto hostAddress = static_cast<uint32_t *>(ptrOffset(immCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer(), counterOffset));
|
auto hostAddress = static_cast<uint64_t *>(ptrOffset(immCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer(), counterOffset));
|
||||||
*hostAddress = 0;
|
*hostAddress = 0;
|
||||||
|
|
||||||
const uint32_t failCounter = 3;
|
const uint32_t failCounter = 3;
|
||||||
@@ -2650,7 +2674,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenDoingCpuCopyThenSynchronize,
|
|||||||
|
|
||||||
auto eventHandle = events[0]->toHandle();
|
auto eventHandle = events[0]->toHandle();
|
||||||
|
|
||||||
auto hostAddress = static_cast<uint32_t *>(immCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer());
|
auto hostAddress = static_cast<uint64_t *>(immCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer());
|
||||||
*hostAddress = 0;
|
*hostAddress = 0;
|
||||||
|
|
||||||
const uint32_t failCounter = 3;
|
const uint32_t failCounter = 3;
|
||||||
@@ -2695,7 +2719,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenGpuHangDetectedInCpuCopyPathT
|
|||||||
|
|
||||||
auto ultCsr = static_cast<UltCommandStreamReceiver<FamilyType> *>(device->getNEODevice()->getDefaultEngine().commandStreamReceiver);
|
auto ultCsr = static_cast<UltCommandStreamReceiver<FamilyType> *>(device->getNEODevice()->getDefaultEngine().commandStreamReceiver);
|
||||||
|
|
||||||
auto hostAddress = static_cast<uint32_t *>(immCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer());
|
auto hostAddress = static_cast<uint64_t *>(immCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer());
|
||||||
*hostAddress = 0;
|
*hostAddress = 0;
|
||||||
|
|
||||||
immCmdList->appendLaunchKernel(kernel->toHandle(), &groupCount, events[0]->toHandle(), 0, nullptr, launchParams, false);
|
immCmdList->appendLaunchKernel(kernel->toHandle(), &groupCount, events[0]->toHandle(), 0, nullptr, launchParams, false);
|
||||||
@@ -2751,7 +2775,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingKernelSplitWithout
|
|||||||
ASSERT_NE(nullptr, sdiCmd);
|
ASSERT_NE(nullptr, sdiCmd);
|
||||||
|
|
||||||
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
||||||
|
|
||||||
alignedFree(alignedPtr);
|
alignedFree(alignedPtr);
|
||||||
@@ -2801,7 +2825,7 @@ HWTEST2_F(InOrderCmdListTests, givenInOrderModeWhenProgrammingKernelSplitWithEve
|
|||||||
ASSERT_NE(nullptr, sdiCmd);
|
ASSERT_NE(nullptr, sdiCmd);
|
||||||
|
|
||||||
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
EXPECT_EQ(immCmdList->inOrderDependencyCounterAllocation->getGpuAddress(), sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
||||||
|
|
||||||
alignedFree(alignedPtr);
|
alignedFree(alignedPtr);
|
||||||
@@ -2892,7 +2916,7 @@ HWTEST2_F(MultiTileInOrderCmdListTests, givenMultiTileInOrderModeWhenCallingSync
|
|||||||
|
|
||||||
immCmdList->appendLaunchKernel(kernel->toHandle(), &groupCount, events[0]->toHandle(), 0, nullptr, launchParams, false);
|
immCmdList->appendLaunchKernel(kernel->toHandle(), &groupCount, events[0]->toHandle(), 0, nullptr, launchParams, false);
|
||||||
|
|
||||||
auto hostAddress0 = static_cast<uint32_t *>(immCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer());
|
auto hostAddress0 = static_cast<uint64_t *>(immCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer());
|
||||||
auto hostAddress1 = ptrOffset(hostAddress0, sizeof(uint64_t));
|
auto hostAddress1 = ptrOffset(hostAddress0, sizeof(uint64_t));
|
||||||
|
|
||||||
*hostAddress0 = 0;
|
*hostAddress0 = 0;
|
||||||
@@ -3107,7 +3131,7 @@ HWTEST2_F(BcsSplitInOrderCmdListTests, givenBcsSplitEnabledWhenDispatchingCopyTh
|
|||||||
auto gpuAddress = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
auto gpuAddress = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
||||||
|
|
||||||
EXPECT_EQ(gpuAddress, sdiCmd->getAddress());
|
EXPECT_EQ(gpuAddress, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
}
|
}
|
||||||
@@ -3147,7 +3171,7 @@ HWTEST2_F(BcsSplitInOrderCmdListTests, givenBcsSplitEnabledWhenDispatchingCopyRe
|
|||||||
auto gpuAddress = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
auto gpuAddress = immCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
||||||
|
|
||||||
EXPECT_EQ(gpuAddress, sdiCmd->getAddress());
|
EXPECT_EQ(gpuAddress, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(immCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
}
|
}
|
||||||
@@ -3230,7 +3254,7 @@ HWTEST2_F(InOrderRegularCmdListTests, givenInOrderModeWhenDispatchingRegularCmdL
|
|||||||
}
|
}
|
||||||
|
|
||||||
regularCmdList->inOrderAllocationOffset = 123;
|
regularCmdList->inOrderAllocationOffset = 123;
|
||||||
auto hostAddr = static_cast<uint32_t *>(regularCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer());
|
auto hostAddr = static_cast<uint64_t *>(regularCmdList->inOrderDependencyCounterAllocation->getUnderlyingBuffer());
|
||||||
*hostAddr = 0x1234;
|
*hostAddr = 0x1234;
|
||||||
|
|
||||||
regularCmdList->reset();
|
regularCmdList->reset();
|
||||||
@@ -3328,7 +3352,7 @@ HWTEST2_F(InOrderRegularCopyOnlyCmdListTests, givenInOrderModeWhenDispatchingReg
|
|||||||
auto gpuAddress = regularCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
auto gpuAddress = regularCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
||||||
|
|
||||||
EXPECT_EQ(gpuAddress, sdiCmd->getAddress());
|
EXPECT_EQ(gpuAddress, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(regularCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
EXPECT_EQ(1u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
}
|
}
|
||||||
@@ -3357,7 +3381,7 @@ HWTEST2_F(InOrderRegularCopyOnlyCmdListTests, givenInOrderModeWhenDispatchingReg
|
|||||||
auto gpuAddress = regularCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
auto gpuAddress = regularCmdList->inOrderDependencyCounterAllocation->getGpuAddress();
|
||||||
|
|
||||||
EXPECT_EQ(gpuAddress, sdiCmd->getAddress());
|
EXPECT_EQ(gpuAddress, sdiCmd->getAddress());
|
||||||
EXPECT_EQ(0u, sdiCmd->getStoreQword());
|
EXPECT_EQ(regularCmdList->isQwordInOrderCounter(), sdiCmd->getStoreQword());
|
||||||
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
EXPECT_EQ(2u, sdiCmd->getDataDword0());
|
||||||
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
EXPECT_EQ(0u, sdiCmd->getDataDword1());
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -1170,7 +1170,7 @@ HWTEST2_F(RelaxedOrderingEnqueueKernelTests, givenEnqueueKernelWhenProgrammingDe
|
|||||||
auto eventNode = castToObject<Event>(outEvent)->getTimestampPacketNodes()->peekNodes()[0];
|
auto eventNode = castToObject<Event>(outEvent)->getTimestampPacketNodes()->peekNodes()[0];
|
||||||
auto compareAddress = eventNode->getGpuAddress() + eventNode->getContextEndOffset();
|
auto compareAddress = eventNode->getGpuAddress() + eventNode->getContextEndOffset();
|
||||||
|
|
||||||
EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(++lrrCmd, 0, compareAddress, 1, CompareOperation::Equal, true));
|
EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(++lrrCmd, 0, compareAddress, 1, CompareOperation::Equal, true, false));
|
||||||
|
|
||||||
mockCmdQueueHw.enqueueBarrierWithWaitList(1, &outEvent, nullptr);
|
mockCmdQueueHw.enqueueBarrierWithWaitList(1, &outEvent, nullptr);
|
||||||
|
|
||||||
@@ -1267,10 +1267,10 @@ HWTEST2_F(RelaxedOrderingEnqueueKernelTests, givenBarrierWithDependenciesWhenFlu
|
|||||||
auto eventNode = castToObject<Event>(outEvent)->getTimestampPacketNodes()->peekNodes()[0];
|
auto eventNode = castToObject<Event>(outEvent)->getTimestampPacketNodes()->peekNodes()[0];
|
||||||
auto compareAddress = eventNode->getGpuAddress() + eventNode->getContextEndOffset();
|
auto compareAddress = eventNode->getGpuAddress() + eventNode->getContextEndOffset();
|
||||||
|
|
||||||
EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(++lrrCmd, 0, compareAddress, 1, CompareOperation::Equal, true));
|
EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(++lrrCmd, 0, compareAddress, 1, CompareOperation::Equal, true, false));
|
||||||
|
|
||||||
auto conditionalBbStart2 = reinterpret_cast<void *>(ptrOffset(lrrCmd, EncodeBatchBufferStartOrEnd<FamilyType>::getCmdSizeConditionalDataMemBatchBufferStart(false)));
|
auto conditionalBbStart2 = reinterpret_cast<void *>(ptrOffset(lrrCmd, EncodeBatchBufferStartOrEnd<FamilyType>::getCmdSizeConditionalDataMemBatchBufferStart(false)));
|
||||||
EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(conditionalBbStart2, 0, compareAddress, 1, CompareOperation::Equal, true));
|
EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(conditionalBbStart2, 0, compareAddress, 1, CompareOperation::Equal, true, false));
|
||||||
|
|
||||||
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(ptrOffset(conditionalBbStart2, EncodeBatchBufferStartOrEnd<FamilyType>::getCmdSizeConditionalDataMemBatchBufferStart(false)));
|
auto sdiCmd = genCmdCast<MI_STORE_DATA_IMM *>(ptrOffset(conditionalBbStart2, EncodeBatchBufferStartOrEnd<FamilyType>::getCmdSizeConditionalDataMemBatchBufferStart(false)));
|
||||||
EXPECT_NE(nullptr, sdiCmd);
|
EXPECT_NE(nullptr, sdiCmd);
|
||||||
|
|||||||
@@ -1118,7 +1118,7 @@ HWTEST2_F(RelaxedOrderingBcsTests, givenDependenciesWhenFlushingThenProgramCorre
|
|||||||
auto eventNode = timestamp.peekNodes()[0];
|
auto eventNode = timestamp.peekNodes()[0];
|
||||||
auto compareAddress = eventNode->getGpuAddress() + eventNode->getContextEndOffset();
|
auto compareAddress = eventNode->getGpuAddress() + eventNode->getContextEndOffset();
|
||||||
|
|
||||||
EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(++lrrCmd, 0, compareAddress, 1, CompareOperation::Equal, true));
|
EXPECT_TRUE(RelaxedOrderingCommandsHelper::verifyConditionalDataMemBbStart<FamilyType>(++lrrCmd, 0, compareAddress, 1, CompareOperation::Equal, true, false));
|
||||||
}
|
}
|
||||||
|
|
||||||
HWTEST2_F(RelaxedOrderingBcsTests, givenDependenciesWhenFlushingThenProgramProgramRelaxedOrderingOnlyIfAllowed, IsAtLeastXeHpcCore) {
|
HWTEST2_F(RelaxedOrderingBcsTests, givenDependenciesWhenFlushingThenProgramProgramRelaxedOrderingOnlyIfAllowed, IsAtLeastXeHpcCore) {
|
||||||
|
|||||||
@@ -129,6 +129,7 @@ struct Gen11Family : public Gen11 {
|
|||||||
static const XY_SRC_COPY_BLT cmdInitXyCopyBlt;
|
static const XY_SRC_COPY_BLT cmdInitXyCopyBlt;
|
||||||
static const MI_FLUSH_DW cmdInitMiFlushDw;
|
static const MI_FLUSH_DW cmdInitMiFlushDw;
|
||||||
static const XY_COLOR_BLT cmdInitXyColorBlt;
|
static const XY_COLOR_BLT cmdInitXyColorBlt;
|
||||||
|
static constexpr bool isQwordInOrderCounter = false;
|
||||||
|
|
||||||
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
||||||
return cmdSetBaseFamily == IGFX_GEN8_CORE;
|
return cmdSetBaseFamily == IGFX_GEN8_CORE;
|
||||||
|
|||||||
@@ -130,6 +130,7 @@ struct Gen12LpFamily : public Gen12Lp {
|
|||||||
static const XY_COPY_BLT cmdInitXyCopyBlt;
|
static const XY_COPY_BLT cmdInitXyCopyBlt;
|
||||||
static const MI_FLUSH_DW cmdInitMiFlushDw;
|
static const MI_FLUSH_DW cmdInitMiFlushDw;
|
||||||
static const XY_FAST_COLOR_BLT cmdInitXyColorBlt;
|
static const XY_FAST_COLOR_BLT cmdInitXyColorBlt;
|
||||||
|
static constexpr bool isQwordInOrderCounter = false;
|
||||||
|
|
||||||
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
||||||
return cmdSetBaseFamily == IGFX_GEN8_CORE;
|
return cmdSetBaseFamily == IGFX_GEN8_CORE;
|
||||||
|
|||||||
@@ -129,6 +129,7 @@ struct Gen8Family : public Gen8 {
|
|||||||
static const XY_SRC_COPY_BLT cmdInitXyCopyBlt;
|
static const XY_SRC_COPY_BLT cmdInitXyCopyBlt;
|
||||||
static const MI_FLUSH_DW cmdInitMiFlushDw;
|
static const MI_FLUSH_DW cmdInitMiFlushDw;
|
||||||
static const XY_COLOR_BLT cmdInitXyColorBlt;
|
static const XY_COLOR_BLT cmdInitXyColorBlt;
|
||||||
|
static constexpr bool isQwordInOrderCounter = false;
|
||||||
|
|
||||||
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
||||||
return cmdSetBaseFamily == IGFX_GEN8_CORE;
|
return cmdSetBaseFamily == IGFX_GEN8_CORE;
|
||||||
|
|||||||
@@ -129,6 +129,7 @@ struct Gen9Family : public Gen9 {
|
|||||||
static const XY_SRC_COPY_BLT cmdInitXyCopyBlt;
|
static const XY_SRC_COPY_BLT cmdInitXyCopyBlt;
|
||||||
static const MI_FLUSH_DW cmdInitMiFlushDw;
|
static const MI_FLUSH_DW cmdInitMiFlushDw;
|
||||||
static const XY_COLOR_BLT cmdInitXyColorBlt;
|
static const XY_COLOR_BLT cmdInitXyColorBlt;
|
||||||
|
static constexpr bool isQwordInOrderCounter = false;
|
||||||
|
|
||||||
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
||||||
return cmdSetBaseFamily == IGFX_GEN8_CORE;
|
return cmdSetBaseFamily == IGFX_GEN8_CORE;
|
||||||
|
|||||||
@@ -10,6 +10,7 @@
|
|||||||
|
|
||||||
#include <cstddef>
|
#include <cstddef>
|
||||||
#include <cstdint>
|
#include <cstdint>
|
||||||
|
#include <limits>
|
||||||
|
|
||||||
inline const int ptrGarbageContent[16] = {
|
inline const int ptrGarbageContent[16] = {
|
||||||
0x0131, 0x133, 0xA, 0xEF,
|
0x0131, 0x133, 0xA, 0xEF,
|
||||||
@@ -71,3 +72,11 @@ inline void patchWithRequiredSize(void *memoryToBePatched, uint32_t patchSize, u
|
|||||||
inline uint64_t castToUint64(const void *address) {
|
inline uint64_t castToUint64(const void *address) {
|
||||||
return static_cast<uint64_t>(reinterpret_cast<uintptr_t>(const_cast<void *>(address)));
|
return static_cast<uint64_t>(reinterpret_cast<uintptr_t>(const_cast<void *>(address)));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
inline uint32_t getLowPart(uint64_t value) {
|
||||||
|
return static_cast<uint32_t>(value & std::numeric_limits<uint32_t>::max());
|
||||||
|
}
|
||||||
|
|
||||||
|
inline uint32_t getHighPart(uint64_t value) {
|
||||||
|
return static_cast<uint32_t>(value >> 32);
|
||||||
|
}
|
||||||
@@ -140,6 +140,7 @@ struct XeHpFamily : public XeHpCore {
|
|||||||
static const _3DSTATE_BTD cmd3dStateBtd;
|
static const _3DSTATE_BTD cmd3dStateBtd;
|
||||||
static const _3DSTATE_BTD_BODY cmd3dStateBtdBody;
|
static const _3DSTATE_BTD_BODY cmd3dStateBtdBody;
|
||||||
static const STATE_SIP cmdInitStateSip;
|
static const STATE_SIP cmdInitStateSip;
|
||||||
|
static constexpr bool isQwordInOrderCounter = false;
|
||||||
|
|
||||||
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
||||||
return cmdSetBaseFamily == IGFX_XE_HP_CORE;
|
return cmdSetBaseFamily == IGFX_XE_HP_CORE;
|
||||||
|
|||||||
@@ -126,6 +126,7 @@ struct XeHpcCoreFamily : public XeHpcCore {
|
|||||||
static const MEM_SET cmdInitMemSet;
|
static const MEM_SET cmdInitMemSet;
|
||||||
static const STATE_SIP cmdInitStateSip;
|
static const STATE_SIP cmdInitStateSip;
|
||||||
static const STATE_SYSTEM_MEM_FENCE_ADDRESS cmdInitStateSystemMemFenceAddress;
|
static const STATE_SYSTEM_MEM_FENCE_ADDRESS cmdInitStateSystemMemFenceAddress;
|
||||||
|
static constexpr bool isQwordInOrderCounter = false;
|
||||||
|
|
||||||
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
||||||
return cmdSetBaseFamily == IGFX_XE_HP_CORE;
|
return cmdSetBaseFamily == IGFX_XE_HP_CORE;
|
||||||
|
|||||||
@@ -142,6 +142,7 @@ struct XeHpgCoreFamily : public XeHpgCore {
|
|||||||
static const _3DSTATE_BTD cmd3dStateBtd;
|
static const _3DSTATE_BTD cmd3dStateBtd;
|
||||||
static const _3DSTATE_BTD_BODY cmd3dStateBtdBody;
|
static const _3DSTATE_BTD_BODY cmd3dStateBtdBody;
|
||||||
static const STATE_SIP cmdInitStateSip;
|
static const STATE_SIP cmdInitStateSip;
|
||||||
|
static constexpr bool isQwordInOrderCounter = false;
|
||||||
|
|
||||||
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) {
|
||||||
return cmdSetBaseFamily == IGFX_XE_HP_CORE;
|
return cmdSetBaseFamily == IGFX_XE_HP_CORE;
|
||||||
|
|||||||
@@ -29,7 +29,7 @@ template <typename FamilyType>
|
|||||||
bool verifyConditionalDataRegBbStart(void *cmd, uint64_t startAddress, uint32_t compareReg, uint32_t compareData, CompareOperation compareOperation, bool indirect);
|
bool verifyConditionalDataRegBbStart(void *cmd, uint64_t startAddress, uint32_t compareReg, uint32_t compareData, CompareOperation compareOperation, bool indirect);
|
||||||
|
|
||||||
template <typename FamilyType>
|
template <typename FamilyType>
|
||||||
bool verifyConditionalDataMemBbStart(void *cmd, uint64_t startAddress, uint64_t compareAddress, uint32_t compareData, CompareOperation compareOperation, bool indirect);
|
bool verifyConditionalDataMemBbStart(void *cmd, uint64_t startAddress, uint64_t compareAddress, uint64_t compareData, CompareOperation compareOperation, bool indirect, bool qwordData);
|
||||||
|
|
||||||
template <typename FamilyType>
|
template <typename FamilyType>
|
||||||
bool verifyConditionalRegRegBbStart(void *cmd, uint64_t startAddress, AluRegisters compareReg0, AluRegisters compareReg1, CompareOperation compareOperation, bool indirect);
|
bool verifyConditionalRegRegBbStart(void *cmd, uint64_t startAddress, AluRegisters compareReg0, AluRegisters compareReg1, CompareOperation compareOperation, bool indirect);
|
||||||
@@ -224,7 +224,7 @@ bool verifyConditionalRegRegBbStart(void *cmd, uint64_t startAddress, AluRegiste
|
|||||||
}
|
}
|
||||||
|
|
||||||
template <typename FamilyType>
|
template <typename FamilyType>
|
||||||
bool verifyConditionalDataMemBbStart(void *cmd, uint64_t startAddress, uint64_t compareAddress, uint32_t compareData, CompareOperation compareOperation, bool indirect) {
|
bool verifyConditionalDataMemBbStart(void *cmd, uint64_t startAddress, uint64_t compareAddress, uint64_t compareData, CompareOperation compareOperation, bool indirect, bool qwordData) {
|
||||||
using MI_LOAD_REGISTER_MEM = typename FamilyType::MI_LOAD_REGISTER_MEM;
|
using MI_LOAD_REGISTER_MEM = typename FamilyType::MI_LOAD_REGISTER_MEM;
|
||||||
using MI_LOAD_REGISTER_IMM = typename FamilyType::MI_LOAD_REGISTER_IMM;
|
using MI_LOAD_REGISTER_IMM = typename FamilyType::MI_LOAD_REGISTER_IMM;
|
||||||
|
|
||||||
@@ -233,16 +233,29 @@ bool verifyConditionalDataMemBbStart(void *cmd, uint64_t startAddress, uint64_t
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
auto lriCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(++lrmCmd);
|
MI_LOAD_REGISTER_IMM *lriCmd = nullptr;
|
||||||
if (!verifyLri<FamilyType>(lriCmd, CS_GPR_R7 + 4, 0)) {
|
|
||||||
|
if (qwordData) {
|
||||||
|
lrmCmd++;
|
||||||
|
if ((lrmCmd->getRegisterAddress() != CS_GPR_R7 + 4) || (lrmCmd->getMemoryAddress() != compareAddress + 4)) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
lriCmd = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(++lrmCmd);
|
||||||
|
} else {
|
||||||
|
auto lriCmd2 = reinterpret_cast<MI_LOAD_REGISTER_IMM *>(++lrmCmd);
|
||||||
|
if (!verifyLri<FamilyType>(lriCmd2, CS_GPR_R7 + 4, 0)) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
lriCmd = ++lriCmd2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!verifyLri<FamilyType>(lriCmd, CS_GPR_R8, getLowPart(compareData))) {
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!verifyLri<FamilyType>(++lriCmd, CS_GPR_R8, compareData)) {
|
if (!verifyLri<FamilyType>(++lriCmd, CS_GPR_R8 + 4, qwordData ? getHighPart(compareData) : 0)) {
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!verifyLri<FamilyType>(++lriCmd, CS_GPR_R8 + 4, 0)) {
|
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@@ -38,6 +38,15 @@ TEST(PtrMath, WhenConvertingAddressToPtrThenPtrIsCorrect) {
|
|||||||
EXPECT_EQ(ptr64BitAddr, addrToPtr(addr64Bit));
|
EXPECT_EQ(ptr64BitAddr, addrToPtr(addr64Bit));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
TEST(PtrMath, given64bValueWhenConvertingToHighAndLowThenReturnCorrectValues) {
|
||||||
|
const uint32_t low = 0x98765432;
|
||||||
|
const uint32_t high = 0x12345678;
|
||||||
|
const uint64_t value = (static_cast<uint64_t>(high) << 32) | low;
|
||||||
|
|
||||||
|
EXPECT_EQ(low, getLowPart(value));
|
||||||
|
EXPECT_EQ(high, getHighPart(value));
|
||||||
|
}
|
||||||
|
|
||||||
TEST(PtrMath, givenCastToUint64FunctionWhenItIsCalledThenProperValueIsReturned) {
|
TEST(PtrMath, givenCastToUint64FunctionWhenItIsCalledThenProperValueIsReturned) {
|
||||||
uintptr_t address = 0xf0000000;
|
uintptr_t address = 0xf0000000;
|
||||||
void *addressWithTrailingBitSet = reinterpret_cast<void *>(address);
|
void *addressWithTrailingBitSet = reinterpret_cast<void *>(address);
|
||||||
|
|||||||
Reference in New Issue
Block a user